diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-09-29 11:03:11 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-20 11:36:56 +0200 |
| commit | e16a2c7aced8422cda2b7f13ea3f3daccb150db6 (patch) | |
| tree | 0a2124b9e736b88094ee318e6bf51febb175db95 /drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | |
| parent | 35406b1fd68dec6d8b1badd69fcfb65646745dfd (diff) | |
pinctrl: sh-pfc: Drop width parameter of sh_pfc_{read,write}_reg()
On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of
sh_pfc_{read,write}_reg() already operate on 32-bit registers only.
Hence make the 32-bit width implicit, and rename the functions to
sh_pfc_{read,write}() to shorten lines.
All accesses to 8-bit or 16-bit registers are still done using
sh_pfc_{read,write}_raw_reg().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index 0adca6a2b08b..bd0687ad4fd8 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -5671,9 +5671,9 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, reg = info->reg; bit = BIT(info->bit); - if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) + if (!(sh_pfc_read(pfc, PUEN + reg) & bit)) return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) + else if (sh_pfc_read(pfc, PUD + reg) & bit) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_PULL_DOWN; @@ -5694,16 +5694,16 @@ static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, reg = info->reg; bit = BIT(info->bit); - enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; + enable = sh_pfc_read(pfc, PUEN + reg) & ~bit; if (bias != PIN_CONFIG_BIAS_DISABLE) enable |= bit; - updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; + updown = sh_pfc_read(pfc, PUD + reg) & ~bit; if (bias == PIN_CONFIG_BIAS_PULL_UP) updown |= bit; - sh_pfc_write_reg(pfc, PUD + reg, 32, updown); - sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); + sh_pfc_write(pfc, PUD + reg, updown); + sh_pfc_write(pfc, PUEN + reg, enable); } static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = { |