diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2017-08-01 22:54:16 +0800 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-08-14 15:01:03 +0200 |
| commit | f547b3de907d45683fc4ff15315e11cb0a3df32d (patch) | |
| tree | 1544e14c210e6acd148f5102a1233d98380799c1 /drivers/pinctrl/sunxi | |
| parent | 3f713b7c223ebe5094973ce6e0272bd97363b552 (diff) | |
pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base
The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not worked around when
developing the driver, which makes IRQ not working.
Fix the IRQ bank base.
Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sunxi')
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index c86d3c42a905..496ba34e1f5f 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -297,6 +297,7 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { .pins = sun8i_v3s_pins, .npins = ARRAY_SIZE(sun8i_v3s_pins), .irq_banks = 2, + .irq_bank_base = 1, .irq_read_needs_mux = true }; |