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authorThierry Reding <treding@nvidia.com>2019-06-21 17:19:32 +0200
committerLinus Walleij <linus.walleij@linaro.org>2019-06-25 15:35:58 +0200
commitcf75b8f2cd8f1f9beb64c2fa2eb93a7c265b59c1 (patch)
tree51b11e4427e8b18a0b826a9f339286710f923e2f /drivers/pinctrl/tegra/pinctrl-tegra30.c
parent55bd054ce434bb4aad80f6b787d69d29342bd4a8 (diff)
pinctrl: tegra: Add bitmask support for parked bits
Some pin groups have park bits for multiple pins in one register. Support this by turning the parked bit field into a parked bitmask field. If no parked bits are supported, the bitmask can be 0. Update the pingroup table on Tegra210, which is the only generation where this is supported, with the parked bitmask. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/tegra/pinctrl-tegra30.c')
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra30.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra30.c b/drivers/pinctrl/tegra/pinctrl-tegra30.c
index 10e617003e9c..10e638198109 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra30.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra30.c
@@ -2141,8 +2141,8 @@ static struct tegra_function tegra30_functions[] = {
.lock_bit = 7, \
.ioreset_bit = PINGROUP_BIT_##ior(8), \
.rcv_sel_bit = -1, \
- .parked_bit = -1, \
.drv_reg = -1, \
+ .parked_bitmask = 0, \
}
#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
@@ -2162,7 +2162,6 @@ static struct tegra_function tegra30_functions[] = {
.rcv_sel_bit = -1, \
.drv_reg = DRV_PINGROUP_REG(r), \
.drv_bank = 0, \
- .parked_bit = -1, \
.hsm_bit = hsm_b, \
.schmitt_bit = schmitt_b, \
.lpmd_bit = lpmd_b, \
@@ -2175,6 +2174,7 @@ static struct tegra_function tegra30_functions[] = {
.slwf_bit = slwf_b, \
.slwf_width = slwf_w, \
.drvtype_bit = -1, \
+ .parked_bitmask = 0, \
}
static const struct tegra_pingroup tegra30_groups[] = {