diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-11-10 22:46:18 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-15 10:44:00 +0100 |
| commit | c76629a63b9c7cc52bb661aa36081c0c87780c3b (patch) | |
| tree | ea5aa4900fb2b8483e11942d64df5385a092ba23 /drivers/pinctrl | |
| parent | aa52b008441fb5a5df01c1d016e5172d2ebc6579 (diff) | |
pinctrl: renesas: rzg2l: Rename RZG2L_SINGLE_PIN_GET_PORT macro
Rename RZG2L_SINGLE_PIN_GET_PORT -> RZG2L_SINGLE_PIN_GET_PORT_OFFSET.
Also, rename port -> port_offset in rzg2l_pinctrl_pinconf_set/get for
readability.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211110224622.16022-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 20b2af889ca9..be9af717a497 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -77,7 +77,7 @@ #define RZG2L_SINGLE_PIN BIT(31) #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ ((p) << 24) | ((b) << 20) | (f)) -#define RZG2L_SINGLE_PIN_GET_PORT(x) (((x) & GENMASK(30, 24)) >> 24) +#define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) #define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) @@ -432,10 +432,10 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; + u32 port_offset = 0, reg; unsigned int arg = 0; unsigned long flags; void __iomem *addr; - u32 port = 0, reg; u32 cfg = 0; u8 bit = 0; @@ -443,7 +443,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; if (*pin_data & RZG2L_SINGLE_PIN) { - port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data); + port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); } @@ -454,7 +454,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; spin_lock_irqsave(&pctrl->lock, flags); /* handle _L/_H for 32-bit register read/write */ - addr = pctrl->base + IEN(port); + addr = pctrl->base + IEN(port_offset); if (bit >= 4) { bit -= 4; addr += 4; @@ -502,9 +502,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; enum pin_config_param param; + u32 port_offset = 0, reg; unsigned long flags; void __iomem *addr; - u32 port = 0, reg; unsigned int i; u32 cfg = 0; u8 bit = 0; @@ -513,7 +513,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, return -EINVAL; if (*pin_data & RZG2L_SINGLE_PIN) { - port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data); + port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); } @@ -529,7 +529,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, return -EINVAL; /* handle _L/_H for 32-bit register read/write */ - addr = pctrl->base + IEN(port); + addr = pctrl->base + IEN(port_offset); if (bit >= 4) { bit -= 4; addr += 4; |