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authorLiming Sun <limings@nvidia.com>2022-10-18 09:33:03 -0400
committerHans de Goede <hdegoede@redhat.com>2022-11-16 08:48:19 +0100
commitbc05ea63b39420fd561dcffba00753da90338ea8 (patch)
tree00cb80fe488e753c58dd78b1c3183b8ae54af781 /drivers/platform/mellanox/mlxbf-tmfifo-regs.h
parentdb5e2a4ca0a7a5fe54f410590292ea2e91de6798 (diff)
platform/mellanox: Add BlueField-3 support in the tmfifo driver
BlueField-3 uses the same control registers in tmfifo access but at different addresses. This commit replaces the offset reference with pointers, and set up these pointers in the probe functions accordingly. Signed-off-by: Liming Sun <limings@nvidia.com> Reviewed-by: David Thompson <davthompson@nvidia.com> Reviewed-by: Vadim Pasternak <vadimp@nvidia.com> Link: https://lore.kernel.org/r/20221018133303.243920-1-limings@nvidia.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform/mellanox/mlxbf-tmfifo-regs.h')
-rw-r--r--drivers/platform/mellanox/mlxbf-tmfifo-regs.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/platform/mellanox/mlxbf-tmfifo-regs.h b/drivers/platform/mellanox/mlxbf-tmfifo-regs.h
index e4f0d2eda714..44fb8c5b1484 100644
--- a/drivers/platform/mellanox/mlxbf-tmfifo-regs.h
+++ b/drivers/platform/mellanox/mlxbf-tmfifo-regs.h
@@ -60,4 +60,14 @@
#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
+/* BF3 register offsets within resource 0. */
+#define MLXBF_TMFIFO_RX_DATA_BF3 0x0000
+#define MLXBF_TMFIFO_TX_DATA_BF3 0x1000
+
+/* BF3 register offsets within resource 1. */
+#define MLXBF_TMFIFO_RX_STS_BF3 0x0000
+#define MLXBF_TMFIFO_RX_CTL_BF3 0x0008
+#define MLXBF_TMFIFO_TX_STS_BF3 0x0100
+#define MLXBF_TMFIFO_TX_CTL_BF3 0x0108
+
#endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */