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authorGayatri Kammela <gayatri.kammela@intel.com>2021-08-16 09:58:33 -0700
committerHans de Goede <hdegoede@redhat.com>2021-08-20 20:33:35 +0200
commit6cfce3ef806c1d458a816db7e63a1c13571abf86 (patch)
tree372df9fdd644bcba192353dc63542e705ec8b1bd /drivers/platform/x86/intel/pmc/core.h
parentee7e89ff80063616c7f81b97ce7d38733019531a (diff)
platform/x86/intel: pmc/core: Add Alder Lake low power mode support for pmc core
Alder Lake has 14 status registers that are memory mapped. These registers show the status of the low power mode requirements. The registers are latched on every C10 entry or exit and on every s0ix.y entry/exit. Accessing these registers is useful for debugging any low power related activities. Thus, add debugfs entry to access low power mode status registers. Cc: Chao Qin <chao.qin@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: David Box <david.e.box@intel.com> Tested-by: You-Sheng Yang <vicamo.yang@canonical.com> Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Link: https://lore.kernel.org/r/d27ec98589a5aaa569bbce0e937ed03779fc0a22.1629091915.git.gayatri.kammela@intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform/x86/intel/pmc/core.h')
-rw-r--r--drivers/platform/x86/intel/pmc/core.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index 6863f4de3070..a46d3b53bf61 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -224,6 +224,18 @@ enum ppfear_regs {
/* Extended Test Mode Register LPM bits (TGL and later */
#define ETR3_CLEAR_LPM_EVENTS BIT(28)
+/* Alder Lake Power Management Controller register offsets */
+#define ADL_LPM_EN_OFFSET 0x179C
+#define ADL_LPM_RESIDENCY_OFFSET 0x17A4
+#define ADL_LPM_NUM_MODES 2
+#define ADL_LPM_NUM_MAPS 14
+
+/* Alder Lake Low Power Mode debug registers */
+#define ADL_LPM_STATUS_OFFSET 0x170C
+#define ADL_LPM_PRI_OFFSET 0x17A0
+#define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704
+#define ADL_LPM_LIVE_STATUS_OFFSET 0x1764
+
const char *pmc_lpm_modes[] = {
"S0i2.0",
"S0i2.1",
@@ -283,6 +295,7 @@ struct pmc_reg_map {
const u32 pm_vric1_offset;
/* Low Power Mode registers */
const int lpm_num_maps;
+ const int lpm_num_modes;
const int lpm_res_counter_step_x2;
const u32 lpm_sts_latch_en_offset;
const u32 lpm_en_offset;