diff options
| author | Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> | 2016-10-07 16:01:15 +0530 |
|---|---|---|
| committer | Darren Hart <dvhart@linux.intel.com> | 2016-12-13 09:28:57 -0800 |
| commit | fe748227570107abaa4767c39be3eff934bdaf5c (patch) | |
| tree | d6c5862399ba106d9adfe539123f9f5b86a3333e /drivers/platform/x86/intel_pmc_core.h | |
| parent | 173943b3dae570d705e3f5237110a64a28c0bf74 (diff) | |
platform/x86: intel_pmc_core: Add MPHY PLL clock gating status
ModPhy Common lanes can provide the clock gating status for the important
system PLLs such as Gen2 USB3PCIE2 PLL, DMIPCIE3 PLL, SATA PLL and MIPI
PLL.
On SPT, in addition to the crystal oscillator clock, the 100Mhz Gen2
USB3PCI2 PLL clock is used as the PLL reference clock and Gen2 PLL idling
is a necessary condition for the platform to go into low power states like
PC10 and S0ix.
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
Diffstat (limited to 'drivers/platform/x86/intel_pmc_core.h')
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 62fe5d15a9b2..07161fb33bb6 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -32,6 +32,7 @@ #define SPT_PMC_MFPMC_OFFSET 0x38 #define SPT_PMC_MPHY_CORE_STS_0 0x1143 #define SPT_PMC_MPHY_CORE_STS_1 0x1142 +#define SPT_PMC_MPHY_COM_STS_0 0x1155 #define SPT_PMC_MMIO_REG_LEN 0x1000 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64 #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) @@ -113,6 +114,11 @@ enum ppfear_regs { #define SPT_PMC_BIT_MPHY_LANE14 BIT(6) #define SPT_PMC_BIT_MPHY_LANE15 BIT(7) +#define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0) +#define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1) +#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) +#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) + struct pmc_bit_map { const char *name; u32 bit_mask; @@ -121,6 +127,7 @@ struct pmc_bit_map { struct pmc_reg_map { const struct pmc_bit_map *pfear_sts; const struct pmc_bit_map *mphy_sts; + const struct pmc_bit_map *pll_sts; }; /** |