diff options
| author | Claudiu.Beznea@microchip.com <Claudiu.Beznea@microchip.com> | 2020-01-21 10:03:39 +0000 |
|---|---|---|
| committer | Sebastian Reichel <sebastian.reichel@collabora.com> | 2020-03-08 19:38:04 +0100 |
| commit | e48bbb52a2aad8613291a9e4e757bbf995769015 (patch) | |
| tree | 0e1de8f1cfc8711c26def74921bafb33874636c7 /drivers/power/reset | |
| parent | 766b0162e613a89a330382e566e29da57f5f0de5 (diff) | |
power: reset: at91-reset: handle nrst async for sam9x60
Handle NRST asynchronously for SAM9X60 to avoid problem with fast drop of
VDDCORE on shutdown operations in the first 100 us after CPU is shutdown.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Diffstat (limited to 'drivers/power/reset')
| -rw-r--r-- | drivers/power/reset/at91-reset.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index 537ccb180568..3ff9d93a5226 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -35,6 +35,7 @@ #define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */ #define AT91_RSTC_URSTEN BIT(0) /* User Reset Enable */ +#define AT91_RSTC_URSTASYNC BIT(2) /* User Reset Asynchronous Control */ #define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ #define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */ @@ -228,6 +229,13 @@ static int __init at91_reset_probe(struct platform_device *pdev) platform_set_drvdata(pdev, reset); + if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) { + u32 val = readl(reset->rstc_base + AT91_RSTC_MR); + + writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val, + reset->rstc_base + AT91_RSTC_MR); + } + ret = register_restart_handler(&reset->nb); if (ret) { clk_disable_unprepare(reset->sclk); |