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authorRahul Rameshbabu <rrameshbabu@nvidia.com>2023-06-12 14:14:59 -0700
committerDavid S. Miller <davem@davemloft.net>2023-06-20 09:02:33 +0100
commite156e4d2e43f8b57696ee155f8c3d026419d3363 (patch)
tree3b19f48744f49044eb252cfa88f11ee67edae616 /drivers/ptp/ptp_idt82p33.h
parentc066e74f34bc464bc1a077a688d7fa31a742d2d5 (diff)
ptp: idt82p33: Add .getmaxphase ptp_clock_info callback
Advertise the maximum offset the .adjphase callback is capable of supporting in nanoseconds for IDT devices. Refactor the negation of the offset stored in the register to be after the boundary check of the offset value rather than before. Boundary check based on the intended value rather than its device-specific representation. Depend on ptp_clock_adjtime for handling out-of-range offsets. ptp_clock_adjtime returns -ERANGE instead of clamping out-of-range offsets. Cc: Richard Cochran <richardcochran@gmail.com> Cc: Min Li <min.li.xe@renesas.com> Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ptp/ptp_idt82p33.h')
-rw-r--r--drivers/ptp/ptp_idt82p33.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h
index 8fcb0b17d207..6a63c14b6966 100644
--- a/drivers/ptp/ptp_idt82p33.h
+++ b/drivers/ptp/ptp_idt82p33.h
@@ -43,9 +43,9 @@
#define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0
/**
- * @brief Maximum absolute value for write phase offset in femtoseconds
+ * @brief Maximum absolute value for write phase offset in nanoseconds
*/
-#define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
+#define WRITE_PHASE_OFFSET_LIMIT (20000l)
/** @brief Phase offset resolution
*