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authorAmit Cohen <amcohen@nvidia.com>2023-07-25 14:04:02 +0200
committerJakub Kicinski <kuba@kernel.org>2023-07-26 21:49:27 -0700
commit7447eda4065e377e09d6ef9ecc8bf3219548d0ed (patch)
tree358e9140bda7deb6abb174221ae0cdfd5cc52945 /drivers/scsi/dc395x.c
parent68bf5100fadffbba297f9142bf005767e571d726 (diff)
mlxsw: reg: Add Management Capabilities Mask Register
MCAM register reports the device supported management features. Querying this register exposes if features are supported with the current firmware version in the current ASIC. Then, the driver can separate between different implementations dynamically. MCAM register supports querying whether the MCIA register supports 128 bytes payloads or only 48 bytes. Add support for the register as preparation for allowing larger MCIA transactions. Note that the access to the bits in the field 'mng_feature_cap_mask' is not same to other mask fields in other registers. In most of the cases bit #0 is the first one in the last dword, in MCAM register, bits #0-#31 are in the first dword and so on. Declare the mask field using bits arrays per dword to simplify the access. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Link: https://lore.kernel.org/r/1427a3f57ba93db1c5dd4f982bfb31dd5c82356e.1690281940.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/scsi/dc395x.c')
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