diff options
author | Dan Williams <dan.j.williams@intel.com> | 2011-03-11 10:43:57 -0800 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2011-07-03 03:55:31 -0700 |
commit | 4711ba10b13891edf228944a9d0a21dfe7fe90f0 (patch) | |
tree | c846eb029eb2bc827a614df963b00aa412b95956 /drivers/scsi/isci/core/scic_sds_controller.c | |
parent | 2e8320f751030a12efc3e64ee857bfa4647f81fe (diff) |
isci: fix oem parameter initialization and mode detection
1/ Since commit 858d4aa7 "isci: Move firmware loading to per PCI device" we have
been silently falling back to built-in defaults for the parameter settings by
skipping the call to scic_oem_parameters_set().
2/ The afe parameters from the firmware were not being honored
3/ The latest oem parameter definition flips the mode_type values which are
now 0: for APC 1: for MPC. For APC we need to make sure all the phys
default to the same address otherwise strict_wide_ports will cause duplicate
domains.
4/ Fix up the driver announcement to indicate the source of the
parameters.
5/ Fix up the sas addresses to be unique per controller (in the fallback case)
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/scsi/isci/core/scic_sds_controller.c')
-rw-r--r-- | drivers/scsi/isci/core/scic_sds_controller.c | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/drivers/scsi/isci/core/scic_sds_controller.c b/drivers/scsi/isci/core/scic_sds_controller.c index 12b2ad5a28b0..b0edd8408fe7 100644 --- a/drivers/scsi/isci/core/scic_sds_controller.c +++ b/drivers/scsi/isci/core/scic_sds_controller.c @@ -595,6 +595,7 @@ void scic_sds_controller_enable_port_task_scheduler( */ void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic) { + const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1; u32 afe_status; u32 phy_id; @@ -632,6 +633,8 @@ void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic) } for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) { + const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id]; + if (is_b0()) { /* Configure transmitter SSC parameters */ scu_afe_txreg_write(scic, phy_id, afe_tx_ssc_control, 0x00030000); @@ -691,16 +694,16 @@ void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic) } udelay(AFE_REGISTER_WRITE_DELAY); - scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, 0x000E7C03); + scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control0); udelay(AFE_REGISTER_WRITE_DELAY); - scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control1, 0x000E7C03); + scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control1); udelay(AFE_REGISTER_WRITE_DELAY); - scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control2, 0x000E7C03); + scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control2); udelay(AFE_REGISTER_WRITE_DELAY); - scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control3, 0x000E7C03); + scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control3); udelay(AFE_REGISTER_WRITE_DELAY); } @@ -2027,6 +2030,7 @@ void scic_sds_controller_release_frame( */ static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic) { + struct isci_host *ihost = sci_object_get_association(scic); u16 index; /* Default to APC mode. */ @@ -2058,7 +2062,7 @@ static void scic_sds_controller_set_default_config_parameters(struct scic_sds_co * is worked around by having the upper 32-bits of SAS address * with a value greater then the Vitesse company identifier. * Hence, usage of 0x5FCFFFFF. */ - scic->oem_parameters.sds1.phys[index].sas_address.low = 0x00000001; + scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id; scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF; } @@ -2604,14 +2608,11 @@ enum sci_status scic_oem_parameters_set( struct scic_sds_controller *scic, union scic_oem_parameters *scic_parms) { - if ( - (scic->parent.state_machine.current_state_id - == SCI_BASE_CONTROLLER_STATE_RESET) - || (scic->parent.state_machine.current_state_id - == SCI_BASE_CONTROLLER_STATE_INITIALIZING) - || (scic->parent.state_machine.current_state_id - == SCI_BASE_CONTROLLER_STATE_INITIALIZED) - ) { + u32 state = scic->parent.state_machine.current_state_id; + + if (state == SCI_BASE_CONTROLLER_STATE_RESET || + state == SCI_BASE_CONTROLLER_STATE_INITIALIZING || + state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) { u16 index; u8 combined_phy_mask = 0; @@ -2651,7 +2652,8 @@ enum sci_status scic_oem_parameters_set( if (scic_parms->sds1.controller.max_concurrent_dev_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT) return SCI_FAILURE_INVALID_PARAMETER_VALUE; - memcpy(&scic->oem_parameters, scic_parms, sizeof(*scic_parms)); + scic->oem_parameters.sds1 = scic_parms->sds1; + return SCI_SUCCESS; } |