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authorJohn Garry <john.garry@huawei.com>2016-10-04 19:11:11 +0800
committerMartin K. Petersen <martin.petersen@oracle.com>2016-11-08 17:29:46 -0500
commit3bc45af81d0dff722c5a2d5d009f2d2d91b52b56 (patch)
tree3bf9b1a03b0af9c1b510ab7c2320eaddca0dd4bd /drivers/scsi/libfc/fc_rport.c
parent039ae102a8d43bbaa00e678b37f58310f4674650 (diff)
scsi: hisi_sas: Add v2 hw support for different refclk
The hip06 D03 and hip07 D05 boards have different reference clock frequencies for the SAS controller. Register PHY_CTRL needs to be programmed differently according to this frequency, so add support for this. The default register setting in PHY_CTRL is for 50MHz, so only update this register when the refclk frequency is 66MHz. For ACPI we expect the _RST handler to set the correct value for PHY_CTRL (we're forced to take different approach for DT and ACPI as ACPI does not support fixed-clock device). Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/libfc/fc_rport.c')
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