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authorWill Deacon <will.deacon@arm.com>2019-02-22 17:18:02 +0000
committerWill Deacon <will.deacon@arm.com>2019-04-08 12:09:05 +0100
commit161861a4c8279f136e5419deb95c58176af83e48 (patch)
tree021f3aa8c03d950fbb530f05b1ce1fb6258643d4 /drivers/scsi/qla1280.c
parentfb24ea52f78e0d595852e09e3a55697c8f442189 (diff)
scsi/qla1280: Remove stale comment about mmiowb()
All mmiowb() invocations have been removed, so there's no need to keep banging on about it. Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/scsi/qla1280.c')
-rw-r--r--drivers/scsi/qla1280.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/scsi/qla1280.c b/drivers/scsi/qla1280.c
index 93acbc5094f0..327eff67a1ee 100644
--- a/drivers/scsi/qla1280.c
+++ b/drivers/scsi/qla1280.c
@@ -3363,16 +3363,6 @@ qla1280_isp_cmd(struct scsi_qla_host *ha)
/*
* Update request index to mailbox4 (Request Queue In).
- * The mmiowb() ensures that this write is ordered with writes by other
- * CPUs. Without the mmiowb(), it is possible for the following:
- * CPUA posts write of index 5 to mailbox4
- * CPUA releases host lock
- * CPUB acquires host lock
- * CPUB posts write of index 6 to mailbox4
- * On PCI bus, order reverses and write of 6 posts, then index 5,
- * causing chip to issue full queue of stale commands
- * The mmiowb() prevents future writes from crossing the barrier.
- * See Documentation/driver-api/device-io.rst for more information.
*/
WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);