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authorLucas Stach <l.stach@pengutronix.de>2022-12-16 21:08:20 +0100
committerShawn Guo <shawnguo@kernel.org>2023-01-01 11:12:03 +0800
commit2cbee26e5d592da942a995ddee78ea3eb97ad2fa (patch)
treee889922b969b099a1a2aaee0c8d63ade97eb8b42 /drivers/soc/imx/Kconfig
parentf4b3948e5a90f49b33e89b019d3c641ab9a6fc59 (diff)
soc: imx: imx8mp-blk-ctrl: expose high performance PLL clock
Expose the high performance PLL as a regular Linux clock, so the PCIe PHY can use it when there is no external refclock provided. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Lukas F. Hartmann <lukas@mntre.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/soc/imx/Kconfig')
-rw-r--r--drivers/soc/imx/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig
index 179bcc896ea2..a8742fc58f01 100644
--- a/drivers/soc/imx/Kconfig
+++ b/drivers/soc/imx/Kconfig
@@ -32,6 +32,7 @@ config IMX8M_BLK_CTRL
bool
default SOC_IMX8M && IMX_GPCV2_PM_DOMAINS
depends on PM_GENERIC_DOMAINS
+ depends on COMMON_CLK
config IMX9_BLK_CTRL
bool