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| author | Ingo Molnar <mingo@kernel.org> | 2018-07-17 09:27:43 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2018-07-17 09:27:43 +0200 |
| commit | 52b544bd386688177c41d53e748111c29d0ccc98 (patch) | |
| tree | c2083582176e773084364af93cc44e0f94b6cde8 /drivers/soc/imx/gpcv2.c | |
| parent | afed7bcf9487bb28e2e2b016a195085c07416c0b (diff) | |
| parent | 9d3cce1e8b8561fed5f383d22a4d6949db4eadbe (diff) | |
Merge tag 'v4.18-rc5' into locking/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/soc/imx/gpcv2.c')
| -rw-r--r-- | drivers/soc/imx/gpcv2.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index f4e3bd40c72e..6ef18cf8f243 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -39,10 +39,15 @@ #define GPC_M4_PU_PDN_FLG 0x1bc - -#define PGC_MIPI 4 -#define PGC_PCIE 5 -#define PGC_USB_HSIC 8 +/* + * The PGC offset values in Reference Manual + * (Rev. 1, 01/2018 and the older ones) GPC chapter's + * GPC_PGC memory map are incorrect, below offset + * values are from design RTL. + */ +#define PGC_MIPI 16 +#define PGC_PCIE 17 +#define PGC_USB_HSIC 20 #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) |