diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2019-03-21 09:57:12 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-03-21 15:02:28 +0000 |
| commit | 69c8a9bcb03222ad3b949064ac05de463c7c9aa3 (patch) | |
| tree | 2d2fc0763f1d4882342cf4769c21e92b060683c9 /drivers/spi/spi-fsl-lpspi.c | |
| parent | f37d8e67f39e6d3eaf4cc5471e8a3d21209843c6 (diff) | |
spi: lpspi: fix dataloss when SS is inactivated between every words
If we don't use CONT to keep SS activated or use DMA mode without
cs-gpio, SS will be inactivated between every words. The word here
means the data sent once which length can be set as 1/2/4 bytes.
In the isr function, we read the FSR_RXCOUNT just behind the
fsl_lpspi_read_rx_fifo. This causes the value of FSR_RXCOUNT cannot
reflect whether there is still data not sent timely. So do this
judgement by FSR_TXCOUNT.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-fsl-lpspi.c')
| -rw-r--r-- | drivers/spi/spi-fsl-lpspi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index 391863914043..9e117c4635d8 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -62,7 +62,7 @@ #define CFGR1_PCSPOL BIT(8) #define CFGR1_NOSTALL BIT(3) #define CFGR1_MASTER BIT(0) -#define FSR_RXCOUNT (BIT(16)|BIT(17)|BIT(18)) +#define FSR_TXCOUNT (0xFF) #define RSR_RXEMPTY BIT(1) #define TCR_CPOL BIT(31) #define TCR_CPHA BIT(30) @@ -452,7 +452,7 @@ static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id) } if (temp_SR & SR_MBF || - readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) { + readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) { writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); return IRQ_HANDLED; |