diff options
| author | Evan Green <evgreen@chromium.org> | 2020-04-27 16:32:48 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-04-30 15:22:58 +0100 |
| commit | 6eefaee4f2d366a389da0eb95e524ba82bf358c4 (patch) | |
| tree | 13374b8dad2fa03d559671d763f224bfe63df853 /drivers/spi/spi-pxa2xx.c | |
| parent | be6ef160840f23d9723d9bd008ca08e864ce4745 (diff) | |
spi: pxa2xx: Apply CS clk quirk to BXT
With a couple allies at Intel, and much badgering, I got confirmation
from Intel that at least BXT suffers from the same SPI chip-select
issue as Cannonlake (and beyond). The issue being that after going
through runtime suspend/resume, toggling the chip-select line without
also sending data does nothing.
Add the quirk to BXT to briefly toggle dynamic clock gating off and
on, forcing the fabric to wake up enough to notice the CS register
change.
Signed-off-by: Evan Green <evgreen@chromium.org>
Cc: Shobhit Srivastava <shobhit.srivastava@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200427163238.1.Ib1faaabe236e37ea73be9b8dcc6aa034cb3c8804@changeid
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-pxa2xx.c')
| -rw-r--r-- | drivers/spi/spi-pxa2xx.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 73d2a65d0b6e..20dcbd35611a 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -150,6 +150,7 @@ static const struct lpss_config lpss_platforms[] = { .tx_threshold_hi = 48, .cs_sel_shift = 8, .cs_sel_mask = 3 << 8, + .cs_clk_stays_gated = true, }, { /* LPSS_CNL_SSP */ .offset = 0x200, |