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authorJarkko Nikula <jarkko.nikula@linux.intel.com>2016-01-26 15:33:21 +0200
committerMark Brown <broonie@kernel.org>2016-01-27 11:29:25 +0000
commitee03672d961bdac2ac1e593e9c29b0d3b7320409 (patch)
tree69b275e221e05cbee56be39e583cea560012fc4e /drivers/spi/spi-pxa2xx.c
parent22a33632fb607a18148815548478265a672d5295 (diff)
spi: pxa2xx: Print actual DMA/PIO transfer mode in debug messages
Transfer debug messages don't actually show is the transfer really using DMA. Driver may fall back to PIO in case transfer size is not within the certain limits or fails to map DMA buffers but debug messages don't reveal that. Move these debug messages further in pump_transfers() where the actual transfer mode is known and use drv_data->dma_mapped flag instead of chip->enable_dma for printing the mode. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-pxa2xx.c')
-rw-r--r--drivers/spi/spi-pxa2xx.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index ab9914ad8365..227e8bad19e6 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1001,19 +1001,6 @@ static void pump_transfers(unsigned long data)
"pump_transfers: DMA burst size reduced to match bits_per_word\n");
}
- /* NOTE: PXA25x_SSP _could_ use external clocking ... */
- cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
- if (!pxa25x_ssp_comp(drv_data))
- dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
- drv_data->master->max_speed_hz
- / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
- chip->enable_dma ? "DMA" : "PIO");
- else
- dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
- drv_data->master->max_speed_hz / 2
- / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
- chip->enable_dma ? "DMA" : "PIO");
-
message->state = RUNNING_STATE;
drv_data->dma_mapped = 0;
@@ -1040,6 +1027,19 @@ static void pump_transfers(unsigned long data)
write_SSSR_CS(drv_data, drv_data->clear_sr);
}
+ /* NOTE: PXA25x_SSP _could_ use external clocking ... */
+ cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
+ if (!pxa25x_ssp_comp(drv_data))
+ dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
+ drv_data->master->max_speed_hz
+ / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
+ drv_data->dma_mapped ? "DMA" : "PIO");
+ else
+ dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
+ drv_data->master->max_speed_hz / 2
+ / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
+ drv_data->dma_mapped ? "DMA" : "PIO");
+
if (is_lpss_ssp(drv_data)) {
if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
!= chip->lpss_rx_threshold)