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authorMark Brown <broonie@opensource.wolfsonmicro.com>2013-04-01 14:17:37 +0100
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-04-01 14:17:37 +0100
commite761f4236e94f2dd36316f9892583b29ce986031 (patch)
treeb5dbda1e8286034df9bc05471fd96d65a7f82ef4 /drivers/spi/spi-s3c64xx.c
parentf4b97eb5061256045e0f031b6a4bcf8c722b35ff (diff)
spi/s3c64xx: Convert to bits_per_word_mask
The core can do the validation for us. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'drivers/spi/spi-s3c64xx.c')
-rw-r--r--drivers/spi/spi-s3c64xx.c10
1 files changed, 1 insertions, 9 deletions
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 7f5f8ee68840..27ff669f0937 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -911,15 +911,6 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
spin_unlock_irqrestore(&sdd->lock, flags);
- if (spi->bits_per_word != 8
- && spi->bits_per_word != 16
- && spi->bits_per_word != 32) {
- dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
- spi->bits_per_word);
- err = -EINVAL;
- goto setup_exit;
- }
-
pm_runtime_get_sync(&sdd->pdev->dev);
/* Check if we can provide the requested rate */
@@ -1237,6 +1228,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
master->num_chipselect = sci->num_cs;
master->dma_alignment = 8;
+ master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
/* the spi->mode bits understood by this driver: */
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;