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authorMurali Karicheri <m-karicheri2@ti.com>2015-06-10 03:23:42 -0400
committerMark Brown <broonie@kernel.org>2015-06-10 18:28:04 +0100
commite0b047bd8fc73b35ba1081097e0223eb778d982c (patch)
treebba7b831a8ef4af5f6bfd7083b1e7907db426065 /drivers/spi
parentb787f68c36d49bb1d9236f403813641efa74a031 (diff)
spi: davinci: change the lower limit of pre-scale divider to 1
SPI hardware spec for Keystone specify a lower value of 0 for pre-scale divider which determine what max value of spi clock (spi-max-frequency) the device can support. This translates to a clock divider of 2. So fix the lower limit value used for the boundary check in davinci_spi_get_prescale() function to 1 so that a maximum of spi device clock rate / 2 is possible to be set for spi-max-frequency. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-davinci.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 5e991065f5b0..987afebea093 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -265,7 +265,7 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
- if (ret < 3 || ret > 256)
+ if (ret < 1 || ret > 256)
return -EINVAL;
return ret - 1;