diff options
| author | Jacob Feder <jacobsfeder@gmail.com> | 2018-07-22 21:27:37 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-07-24 14:14:13 +0200 |
| commit | 4a965c5f89decd636129cddc47e5f2c61e8f13e6 (patch) | |
| tree | 865033e3702811c95989d03adbe89bfd831cf093 /drivers/staging/Makefile | |
| parent | 670c6365c91e345582bf905e946ed35fb684891e (diff) | |
staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core
This IP core has read and write AXI-Stream FIFOs, the contents of which can
be accessed from the AXI4 memory-mapped interface. This is useful for
transferring data from a processor into the FPGA fabric. The driver creates
a character device that can be read/written to with standard
open/read/write/close.
See Xilinx PG080 document for IP details.
https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf
The driver currently supports only store-forward mode with a 32-bit
AXI4 Lite interface. DOES NOT support:
- cut-through mode
- AXI4 (non-lite)
Signed-off-by: Jacob Feder <jacobsfeder@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/Makefile')
| -rw-r--r-- | drivers/staging/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 7a0ff10f5ebb..231698f2da7d 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_SOC_MT7621) += mt7621-mmc/ obj-$(CONFIG_SOC_MT7621) += mt7621-eth/ obj-$(CONFIG_SOC_MT7621) += mt7621-dts/ obj-$(CONFIG_STAGING_GASKET_FRAMEWORK) += gasket/ +obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/ |