diff options
| author | Vipin Mehta <vmehta@atheros.com> | 2010-09-01 12:06:33 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-09-02 11:43:26 -0700 |
| commit | 30295c8936f3a426985e99bebb17d72bd7847910 (patch) | |
| tree | 28ff0c23bfa931b73a35e7b11df1bf104260c6fa /drivers/staging/ath6kl/include/common | |
| parent | 9b9913d80b2896ecd9e0a1a8f167ccad66fac79c (diff) | |
staging: add ath6kl driver for AR6003 chip
AR6003 is a single stream, SDIO based 802.11 chipset from
Atheros optimized for mobile and embedded devices. ath6kl is a
cfg80211 driver for AR6003 and supports both the station and
AP mode of operation.
Station mode supports 802.11 a/b/g/n with HT20 on 2.4/5GHz and
HT40 only on 5GHz. Some of the other features include WPA/WPA2,
WPS, WMM, WMM-PS, and BT coexistence. AP mode can be operated
only in b/g mode with support for a subset of features mentioned
above.
The driver supports cfg80211 but comes with its own set of
wext ioctls which have historically supported some of our
customers with features like BT 3.0 and AP mode of operation.
For further details, please refer to:
http://wireless.kernel.org/en/users/Drivers/ath6kl
The driver requires firmware that runs on the chip's network
processor. The majority of it is stored in ROM. The binaries
that are downloaded and executed from RAM are as follows:
1) Patch against the code in ROM for bug fixes and feature
enhancements.
2) Code to copy the data from the OTP region of the memory
into RAM.
3) Calibration file carrying board specific data.
The above files need to be present in the directory
'/lib/firmware/ath6k/AR6003/hw2.0/' for the driver to initialize
the chip upon enumeration. The files can be downloaded from the
link specified at the following location:
http://wireless.kernel.org/en/users/Drivers/ath6kl#Download
This driver is only provided in the interim while we work on
the mac80211 replacement, ath6k. Once the mac80211 driver
achieves feature parity with the ath6kl driver, the ath6kl will
be deprecated and removed from staging.
Signed-off-by: Vipin Mehta <vmehta@atheros.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/ath6kl/include/common')
68 files changed, 40596 insertions, 0 deletions
diff --git a/drivers/staging/ath6kl/include/common/AR6002/AR6002_regdump.h b/drivers/staging/ath6kl/include/common/AR6002/AR6002_regdump.h new file mode 100644 index 000000000000..e3291cf4dbd4 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/AR6002_regdump.h @@ -0,0 +1,60 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2006-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __AR6002_REGDUMP_H__ +#define __AR6002_REGDUMP_H__ + +#if !defined(__ASSEMBLER__) +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ +struct XTensa_exception_frame_s { + A_UINT32 xt_pc; + A_UINT32 xt_ps; + A_UINT32 xt_sar; + A_UINT32 xt_vpri; + A_UINT32 xt_a2; + A_UINT32 xt_a3; + A_UINT32 xt_a4; + A_UINT32 xt_a5; + A_UINT32 xt_exccause; + A_UINT32 xt_lcount; + A_UINT32 xt_lbeg; + A_UINT32 xt_lend; + + A_UINT32 epc1, epc2, epc3, epc4; + + /* Extra info to simplify post-mortem stack walkback */ +#define AR6002_REGDUMP_FRAMES 10 + struct { + A_UINT32 a0; /* pc */ + A_UINT32 a1; /* sp */ + A_UINT32 a2; + A_UINT32 a3; + } wb[AR6002_REGDUMP_FRAMES]; +}; +typedef struct XTensa_exception_frame_s CPU_exception_frame_t; +#define RD_SIZE sizeof(CPU_exception_frame_t) + +#endif +#endif /* __AR6002_REGDUMP_H__ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/AR6K_version.h b/drivers/staging/ath6kl/include/common/AR6002/AR6K_version.h new file mode 100644 index 000000000000..5407e05d9b05 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/AR6K_version.h @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// <copyright file="AR6K_version.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#define __VER_MAJOR_ 3 +#define __VER_MINOR_ 0 +#define __VER_PATCH_ 0 + +/* The makear6ksdk script (used for release builds) modifies the following line. */ +#define __BUILD_NUMBER_ 233 + + +/* Format of the version number. */ +#define VER_MAJOR_BIT_OFFSET 28 +#define VER_MINOR_BIT_OFFSET 24 +#define VER_PATCH_BIT_OFFSET 16 +#define VER_BUILD_NUM_BIT_OFFSET 0 + + +/* + * The version has the following format: + * Bits 28-31: Major version + * Bits 24-27: Minor version + * Bits 16-23: Patch version + * Bits 0-15: Build number (automatically generated during build process ) + * E.g. Build 1.1.3.7 would be represented as 0x11030007. + * + * DO NOT split the following macro into multiple lines as this may confuse the build scripts. + */ +#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) ) + +/* ABI Version. Reflects the version of binary interface exposed by AR6K target firmware. Needs to be incremented by 1 for any change in the firmware that requires upgrade of the driver on the host side for the change to work correctly */ +#define AR6K_ABI_VERSION 1 diff --git a/drivers/staging/ath6kl/include/common/AR6002/addrs.h b/drivers/staging/ath6kl/include/common/AR6002/addrs.h new file mode 100644 index 000000000000..eaaccf4cad7b --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/addrs.h @@ -0,0 +1,90 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// +// Author(s): ="Atheros" +//------------------------------------------------------------------------------ + +#ifndef __ADDRS_H__ +#define __ADDRS_H__ + +/* + * Special AR6002 Addresses that may be needed by special + * applications (e.g. ART) on the Host as well as Target. + */ + +#if defined(AR6002_REV2) +#define AR6K_RAM_START 0x00500000 +#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff) +#define TARG_RAM_SZ (184*1024) +#define TARG_ROM_SZ (80*1024) +#endif +#if defined(AR6002_REV4) || defined(AR6003) +#define AR6K_RAM_START 0x00540000 +#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000) +#define TARG_RAM_SZ (256*1024) +#define TARG_ROM_SZ (256*1024) +#endif + +#define AR6002_BOARD_DATA_SZ 768 +#define AR6002_BOARD_EXT_DATA_SZ 0 +#define AR6003_BOARD_DATA_SZ 1024 +#define AR6003_BOARD_EXT_DATA_SZ 768 + +#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset)) +#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset) + +#define AR6K_ROM_START 0x004e0000 +#define TARG_ROM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0x1fffff) - 0xe0000) +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +/* + * At this ROM address is a pointer to the start of the ROM DataSet Index. + * If there are no ROM DataSets, there's a 0 at this address. + */ +#define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8) +#define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4) + +/* + * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to + * board data. + */ + +/* Size of Board Data, in bytes */ +#if defined(AR6002_REV4) || defined(AR6003) +#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ +#else +#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ +#endif + + +/* + * Constants used by ASM code to access fields of host_interest_s, + * which is at a fixed location in RAM. + */ +#if defined(AR6002_REV4) || defined(AR6003) +#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x60c) +#else +#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c) +#endif +#define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR + +#endif /* __ADDRS_H__ */ + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/analog_intf_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/analog_intf_reg.h new file mode 100644 index 000000000000..9c82767b6efb --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/analog_intf_reg.h @@ -0,0 +1,64 @@ +#ifndef _ANALOG_INTF_REG_REG_H_ +#define _ANALOG_INTF_REG_REG_H_ + +#define SW_OVERRIDE_ADDRESS 0x00000080 +#define SW_OVERRIDE_OFFSET 0x00000080 +#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002 +#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB) +#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK) +#define SW_OVERRIDE_ENABLE_MSB 0 +#define SW_OVERRIDE_ENABLE_LSB 0 +#define SW_OVERRIDE_ENABLE_MASK 0x00000001 +#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB) +#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK) + +#define SIN_VAL_ADDRESS 0x00000084 +#define SIN_VAL_OFFSET 0x00000084 +#define SIN_VAL_SIN_MSB 0 +#define SIN_VAL_SIN_LSB 0 +#define SIN_VAL_SIN_MASK 0x00000001 +#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB) +#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK) + +#define SW_SCLK_ADDRESS 0x00000088 +#define SW_SCLK_OFFSET 0x00000088 +#define SW_SCLK_SW_SCLK_MSB 0 +#define SW_SCLK_SW_SCLK_LSB 0 +#define SW_SCLK_SW_SCLK_MASK 0x00000001 +#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB) +#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK) + +#define SW_CNTL_ADDRESS 0x0000008c +#define SW_CNTL_OFFSET 0x0000008c +#define SW_CNTL_SW_SCAPTURE_MSB 2 +#define SW_CNTL_SW_SCAPTURE_LSB 2 +#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004 +#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB) +#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK) +#define SW_CNTL_SW_SUPDATE_MSB 1 +#define SW_CNTL_SW_SUPDATE_LSB 1 +#define SW_CNTL_SW_SUPDATE_MASK 0x00000002 +#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB) +#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK) +#define SW_CNTL_SW_SOUT_MSB 0 +#define SW_CNTL_SW_SOUT_LSB 0 +#define SW_CNTL_SW_SOUT_MASK 0x00000001 +#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB) +#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_reg_reg_s { + unsigned char pad0[128]; /* pad to 0x80 */ + volatile unsigned int sw_override; + volatile unsigned int sin_val; + volatile unsigned int sw_sclk; + volatile unsigned int sw_cntl; +} analog_intf_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/analog_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/analog_reg.h new file mode 100644 index 000000000000..cf562b86f655 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/analog_reg.h @@ -0,0 +1,1932 @@ +#ifndef _ANALOG_REG_REG_H_ +#define _ANALOG_REG_REG_H_ + +#define SYNTH_SYNTH1_ADDRESS 0x00000000 +#define SYNTH_SYNTH1_OFFSET 0x00000000 +#define SYNTH_SYNTH1_PWD_BIAS_MSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_LSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB) +#define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK) +#define SYNTH_SYNTH1_PWD_CP_MSB 30 +#define SYNTH_SYNTH1_PWD_CP_LSB 30 +#define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000 +#define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB) +#define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK) +#define SYNTH_SYNTH1_PWD_VCMON_MSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_LSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB) +#define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK) +#define SYNTH_SYNTH1_PWD_VCO_MSB 28 +#define SYNTH_SYNTH1_PWD_VCO_LSB 28 +#define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000 +#define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB) +#define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK) +#define SYNTH_SYNTH1_PWD_PRESC_MSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_LSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB) +#define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK) +#define SYNTH_SYNTH1_PWD_LODIV_MSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_LSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000 +#define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB) +#define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK) +#define SYNTH_SYNTH1_PWD_LOMIX_MSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_LSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000 +#define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB) +#define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK) +#define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000 +#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB) +#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) +#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000 +#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB) +#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) +#define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000 +#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB) +#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) +#define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21 +#define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20 +#define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000 +#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB) +#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) +#define SYNTH_SYNTH1_VCOREGBIAS_MSB 19 +#define SYNTH_SYNTH1_VCOREGBIAS_LSB 18 +#define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000 +#define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB) +#define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK) +#define SYNTH_SYNTH1_SLIDINGIF_MSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_LSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000 +#define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB) +#define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK) +#define SYNTH_SYNTH1_SPARE_PWD_MSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_LSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000 +#define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB) +#define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK) +#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000 +#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB) +#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOREG_MSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_LSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000 +#define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB) +#define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000 +#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB) +#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) +#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12 +#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10 +#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00 +#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB) +#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_MSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_LSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020 +#define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK) +#define SYNTH_SYNTH1_MONITOR_REF_MSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_LSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010 +#define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB) +#define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) + +#define SYNTH_SYNTH2_ADDRESS 0x00000004 +#define SYNTH_SYNTH2_OFFSET 0x00000004 +#define SYNTH_SYNTH2_VC_CAL_REF_MSB 31 +#define SYNTH_SYNTH2_VC_CAL_REF_LSB 29 +#define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB) +#define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK) +#define SYNTH_SYNTH2_VC_HI_REF_MSB 28 +#define SYNTH_SYNTH2_VC_HI_REF_LSB 26 +#define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB) +#define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK) +#define SYNTH_SYNTH2_VC_MID_REF_MSB 25 +#define SYNTH_SYNTH2_VC_MID_REF_LSB 23 +#define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB) +#define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK) +#define SYNTH_SYNTH2_VC_LOW_REF_MSB 22 +#define SYNTH_SYNTH2_VC_LOW_REF_LSB 20 +#define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB) +#define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) +#define SYNTH_SYNTH2_LOOP_CP_MSB 14 +#define SYNTH_SYNTH2_LOOP_CP_LSB 10 +#define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00 +#define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB) +#define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK) +#define SYNTH_SYNTH2_LOOP_RS_MSB 9 +#define SYNTH_SYNTH2_LOOP_RS_LSB 5 +#define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0 +#define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB) +#define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK) +#define SYNTH_SYNTH2_LOOP_CS_MSB 4 +#define SYNTH_SYNTH2_LOOP_CS_LSB 3 +#define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018 +#define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB) +#define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK) +#define SYNTH_SYNTH2_SPARE_BITS_MSB 2 +#define SYNTH_SYNTH2_SPARE_BITS_LSB 0 +#define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007 +#define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB) +#define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK) + +#define SYNTH_SYNTH3_ADDRESS 0x00000008 +#define SYNTH_SYNTH3_OFFSET 0x00000008 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) +#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23 +#define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18 +#define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) + +#define SYNTH_SYNTH4_ADDRESS 0x0000000c +#define SYNTH_SYNTH4_OFFSET 0x0000000c +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) +#define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB) +#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) +#define SYNTH_SYNTH4_FORCE_PINVC_MSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_LSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB) +#define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK) +#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB) +#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) +#define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25 +#define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18 +#define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB) +#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) +#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB) +#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) +#define SYNTH_SYNTH4_REFDIVSEL_MSB 16 +#define SYNTH_SYNTH4_REFDIVSEL_LSB 15 +#define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000 +#define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB) +#define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK) +#define SYNTH_SYNTH4_PFDDELAY_MSB 14 +#define SYNTH_SYNTH4_PFDDELAY_LSB 14 +#define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000 +#define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB) +#define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK) +#define SYNTH_SYNTH4_PFD_DISABLE_MSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_LSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB) +#define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK) +#define SYNTH_SYNTH4_PRESCSEL_MSB 12 +#define SYNTH_SYNTH4_PRESCSEL_LSB 11 +#define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800 +#define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB) +#define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK) +#define SYNTH_SYNTH4_RESET_PRESC_MSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_LSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB) +#define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK) +#define SYNTH_SYNTH4_SDM_DISABLE_MSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_LSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB) +#define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK) +#define SYNTH_SYNTH4_SDM_MODE_MSB 8 +#define SYNTH_SYNTH4_SDM_MODE_LSB 8 +#define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100 +#define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB) +#define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK) +#define SYNTH_SYNTH4_SDM_DITHER_MSB 7 +#define SYNTH_SYNTH4_SDM_DITHER_LSB 6 +#define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0 +#define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB) +#define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) +#define SYNTH_SYNTH4_SPARE_MISC_MSB 3 +#define SYNTH_SYNTH4_SPARE_MISC_LSB 2 +#define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c +#define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB) +#define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK) +#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB) +#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) + +#define SYNTH_SYNTH5_ADDRESS 0x00000010 +#define SYNTH_SYNTH5_OFFSET 0x00000010 +#define SYNTH_SYNTH5_LOOP_IP0_MSB 31 +#define SYNTH_SYNTH5_LOOP_IP0_LSB 28 +#define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000 +#define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB) +#define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK) +#define SYNTH_SYNTH5_SLOPE_IP_MSB 27 +#define SYNTH_SYNTH5_SLOPE_IP_LSB 25 +#define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000 +#define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB) +#define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK) +#define SYNTH_SYNTH5_CPBIAS_MSB 24 +#define SYNTH_SYNTH5_CPBIAS_LSB 23 +#define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000 +#define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB) +#define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK) +#define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000 +#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB) +#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) +#define SYNTH_SYNTH5_CPLOWLK_MSB 21 +#define SYNTH_SYNTH5_CPLOWLK_LSB 21 +#define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000 +#define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB) +#define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK) +#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20 +#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17 +#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000 +#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB) +#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) +#define SYNTH_SYNTH5_CAPRANGE1_MSB 16 +#define SYNTH_SYNTH5_CAPRANGE1_LSB 13 +#define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000 +#define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB) +#define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK) +#define SYNTH_SYNTH5_CAPRANGE2_MSB 12 +#define SYNTH_SYNTH5_CAPRANGE2_LSB 9 +#define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00 +#define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB) +#define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK) +#define SYNTH_SYNTH5_CAPRANGE3_MSB 8 +#define SYNTH_SYNTH5_CAPRANGE3_LSB 5 +#define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0 +#define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB) +#define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) +#define SYNTH_SYNTH5_SPARE_MSB 1 +#define SYNTH_SYNTH5_SPARE_LSB 0 +#define SYNTH_SYNTH5_SPARE_MASK 0x00000003 +#define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB) +#define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK) + +#define SYNTH_SYNTH6_ADDRESS 0x00000014 +#define SYNTH_SYNTH6_OFFSET 0x00000014 +#define SYNTH_SYNTH6_IRCP_MSB 31 +#define SYNTH_SYNTH6_IRCP_LSB 29 +#define SYNTH_SYNTH6_IRCP_MASK 0xe0000000 +#define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB) +#define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK) +#define SYNTH_SYNTH6_IRVCMON_MSB 28 +#define SYNTH_SYNTH6_IRVCMON_LSB 26 +#define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000 +#define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB) +#define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK) +#define SYNTH_SYNTH6_IRSPARE_MSB 25 +#define SYNTH_SYNTH6_IRSPARE_LSB 23 +#define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000 +#define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB) +#define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK) +#define SYNTH_SYNTH6_ICPRESC_MSB 22 +#define SYNTH_SYNTH6_ICPRESC_LSB 20 +#define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000 +#define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB) +#define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK) +#define SYNTH_SYNTH6_ICLODIV_MSB 19 +#define SYNTH_SYNTH6_ICLODIV_LSB 17 +#define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000 +#define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB) +#define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK) +#define SYNTH_SYNTH6_ICLOMIX_MSB 16 +#define SYNTH_SYNTH6_ICLOMIX_LSB 14 +#define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000 +#define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB) +#define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK) +#define SYNTH_SYNTH6_ICSPAREA_MSB 13 +#define SYNTH_SYNTH6_ICSPAREA_LSB 11 +#define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800 +#define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB) +#define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK) +#define SYNTH_SYNTH6_ICSPAREB_MSB 10 +#define SYNTH_SYNTH6_ICSPAREB_LSB 8 +#define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700 +#define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB) +#define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK) +#define SYNTH_SYNTH6_ICVCO_MSB 7 +#define SYNTH_SYNTH6_ICVCO_LSB 5 +#define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0 +#define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB) +#define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK) +#define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4 +#define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3 +#define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018 +#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB) +#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) +#define SYNTH_SYNTH6_SPARE_BIAS_MSB 2 +#define SYNTH_SYNTH6_SPARE_BIAS_LSB 0 +#define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007 +#define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB) +#define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK) + +#define SYNTH_SYNTH7_ADDRESS 0x00000018 +#define SYNTH_SYNTH7_OFFSET 0x00000018 +#define SYNTH_SYNTH7_SYNTH_ON_MSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_LSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000 +#define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB) +#define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) +#define SYNTH_SYNTH7_CAP_SEARCH_MSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_LSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000 +#define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB) +#define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) +#define SYNTH_SYNTH7_PIN_VC_MSB 24 +#define SYNTH_SYNTH7_PIN_VC_LSB 24 +#define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000 +#define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB) +#define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK) +#define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23 +#define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16 +#define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000 +#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB) +#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) +#define SYNTH_SYNTH7_SHORT_R_MSB 15 +#define SYNTH_SYNTH7_SHORT_R_LSB 15 +#define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000 +#define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB) +#define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK) +#define SYNTH_SYNTH7_RESET_RFD_MSB 14 +#define SYNTH_SYNTH7_RESET_RFD_LSB 14 +#define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000 +#define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB) +#define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK) +#define SYNTH_SYNTH7_RESET_PFD_MSB 13 +#define SYNTH_SYNTH7_RESET_PFD_LSB 13 +#define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000 +#define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB) +#define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) +#define SYNTH_SYNTH7_RESET_SDM_B_MSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_LSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800 +#define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB) +#define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK) +#define SYNTH_SYNTH7_VC2HIGH_MSB 10 +#define SYNTH_SYNTH7_VC2HIGH_LSB 10 +#define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400 +#define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB) +#define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK) +#define SYNTH_SYNTH7_VC2LOW_MSB 9 +#define SYNTH_SYNTH7_VC2LOW_LSB 9 +#define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200 +#define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB) +#define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK) +#define SYNTH_SYNTH7_LOOP_IP_MSB 8 +#define SYNTH_SYNTH7_LOOP_IP_LSB 5 +#define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0 +#define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB) +#define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK) +#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3 +#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018 +#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH7_SPARE_READ_MSB 2 +#define SYNTH_SYNTH7_SPARE_READ_LSB 0 +#define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007 +#define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB) +#define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK) + +#define SYNTH_SYNTH8_ADDRESS 0x0000001c +#define SYNTH_SYNTH8_OFFSET 0x0000001c +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) +#define SYNTH_SYNTH8_FRACMODE_MSB 30 +#define SYNTH_SYNTH8_FRACMODE_LSB 30 +#define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000 +#define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB) +#define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK) +#define SYNTH_SYNTH8_AMODEREFSEL_MSB 29 +#define SYNTH_SYNTH8_AMODEREFSEL_LSB 28 +#define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000 +#define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB) +#define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK) +#define SYNTH_SYNTH8_SPARE_MSB 27 +#define SYNTH_SYNTH8_SPARE_LSB 27 +#define SYNTH_SYNTH8_SPARE_MASK 0x08000000 +#define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB) +#define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK) +#define SYNTH_SYNTH8_CHANSEL_MSB 26 +#define SYNTH_SYNTH8_CHANSEL_LSB 18 +#define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000 +#define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB) +#define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK) +#define SYNTH_SYNTH8_CHANFRAC_MSB 17 +#define SYNTH_SYNTH8_CHANFRAC_LSB 1 +#define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe +#define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB) +#define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK) +#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001 +#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB) +#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) + +#define RF5G_RF5G1_ADDRESS 0x00000020 +#define RF5G_RF5G1_OFFSET 0x00000020 +#define RF5G_RF5G1_PDTXLO5_MSB 31 +#define RF5G_RF5G1_PDTXLO5_LSB 31 +#define RF5G_RF5G1_PDTXLO5_MASK 0x80000000 +#define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB) +#define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK) +#define RF5G_RF5G1_PDTXMIX5_MSB 30 +#define RF5G_RF5G1_PDTXMIX5_LSB 30 +#define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000 +#define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB) +#define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK) +#define RF5G_RF5G1_PDTXBUF5_MSB 29 +#define RF5G_RF5G1_PDTXBUF5_LSB 29 +#define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000 +#define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB) +#define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK) +#define RF5G_RF5G1_PDPADRV5_MSB 28 +#define RF5G_RF5G1_PDPADRV5_LSB 28 +#define RF5G_RF5G1_PDPADRV5_MASK 0x10000000 +#define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB) +#define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK) +#define RF5G_RF5G1_PDPAOUT5_MSB 27 +#define RF5G_RF5G1_PDPAOUT5_LSB 27 +#define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000 +#define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB) +#define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK) +#define RF5G_RF5G1_TUNE_PADRV5_MSB 26 +#define RF5G_RF5G1_TUNE_PADRV5_LSB 24 +#define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000 +#define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB) +#define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK) +#define RF5G_RF5G1_PWDTXPKD_MSB 23 +#define RF5G_RF5G1_PWDTXPKD_LSB 21 +#define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000 +#define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB) +#define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK) +#define RF5G_RF5G1_DB5_MSB 20 +#define RF5G_RF5G1_DB5_LSB 18 +#define RF5G_RF5G1_DB5_MASK 0x001c0000 +#define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB) +#define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK) +#define RF5G_RF5G1_OB5_MSB 17 +#define RF5G_RF5G1_OB5_LSB 15 +#define RF5G_RF5G1_OB5_MASK 0x00038000 +#define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB) +#define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK) +#define RF5G_RF5G1_TX5_ATB_SEL_MSB 14 +#define RF5G_RF5G1_TX5_ATB_SEL_LSB 12 +#define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000 +#define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB) +#define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK) +#define RF5G_RF5G1_PDLO5DIV_MSB 11 +#define RF5G_RF5G1_PDLO5DIV_LSB 11 +#define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800 +#define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB) +#define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK) +#define RF5G_RF5G1_PDLO5MIX_MSB 10 +#define RF5G_RF5G1_PDLO5MIX_LSB 10 +#define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400 +#define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB) +#define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK) +#define RF5G_RF5G1_PDQBUF5_MSB 9 +#define RF5G_RF5G1_PDQBUF5_LSB 9 +#define RF5G_RF5G1_PDQBUF5_MASK 0x00000200 +#define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB) +#define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK) +#define RF5G_RF5G1_PDLO5AGC_MSB 8 +#define RF5G_RF5G1_PDLO5AGC_LSB 8 +#define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100 +#define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB) +#define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK) +#define RF5G_RF5G1_PDREGLO5_MSB 7 +#define RF5G_RF5G1_PDREGLO5_LSB 7 +#define RF5G_RF5G1_PDREGLO5_MASK 0x00000080 +#define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB) +#define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK) +#define RF5G_RF5G1_LO5_ATB_SEL_MSB 6 +#define RF5G_RF5G1_LO5_ATB_SEL_LSB 4 +#define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070 +#define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB) +#define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK) +#define RF5G_RF5G1_LO5CONTROL_MSB 3 +#define RF5G_RF5G1_LO5CONTROL_LSB 3 +#define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008 +#define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB) +#define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK) +#define RF5G_RF5G1_REGLO_BYPASS5_MSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_LSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004 +#define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB) +#define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK) +#define RF5G_RF5G1_SPARE_MSB 1 +#define RF5G_RF5G1_SPARE_LSB 0 +#define RF5G_RF5G1_SPARE_MASK 0x00000003 +#define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB) +#define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK) + +#define RF5G_RF5G2_ADDRESS 0x00000024 +#define RF5G_RF5G2_OFFSET 0x00000024 +#define RF5G_RF5G2_AGCLO_B_MSB 31 +#define RF5G_RF5G2_AGCLO_B_LSB 29 +#define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000 +#define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB) +#define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK) +#define RF5G_RF5G2_RX5_ATB_SEL_MSB 28 +#define RF5G_RF5G2_RX5_ATB_SEL_LSB 26 +#define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000 +#define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB) +#define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK) +#define RF5G_RF5G2_PDCMOSLO5_MSB 25 +#define RF5G_RF5G2_PDCMOSLO5_LSB 25 +#define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000 +#define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB) +#define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK) +#define RF5G_RF5G2_PDVGM5_MSB 24 +#define RF5G_RF5G2_PDVGM5_LSB 24 +#define RF5G_RF5G2_PDVGM5_MASK 0x01000000 +#define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB) +#define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK) +#define RF5G_RF5G2_PDCSLNA5_MSB 23 +#define RF5G_RF5G2_PDCSLNA5_LSB 23 +#define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000 +#define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB) +#define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK) +#define RF5G_RF5G2_PDRFVGA5_MSB 22 +#define RF5G_RF5G2_PDRFVGA5_LSB 22 +#define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000 +#define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB) +#define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK) +#define RF5G_RF5G2_PDREGFE5_MSB 21 +#define RF5G_RF5G2_PDREGFE5_LSB 21 +#define RF5G_RF5G2_PDREGFE5_MASK 0x00200000 +#define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB) +#define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK) +#define RF5G_RF5G2_TUNE_RFVGA5_MSB 20 +#define RF5G_RF5G2_TUNE_RFVGA5_LSB 18 +#define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000 +#define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB) +#define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK) +#define RF5G_RF5G2_BRFVGA5_MSB 17 +#define RF5G_RF5G2_BRFVGA5_LSB 15 +#define RF5G_RF5G2_BRFVGA5_MASK 0x00038000 +#define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB) +#define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK) +#define RF5G_RF5G2_BCSLNA5_MSB 14 +#define RF5G_RF5G2_BCSLNA5_LSB 12 +#define RF5G_RF5G2_BCSLNA5_MASK 0x00007000 +#define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB) +#define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK) +#define RF5G_RF5G2_BVGM5_MSB 11 +#define RF5G_RF5G2_BVGM5_LSB 9 +#define RF5G_RF5G2_BVGM5_MASK 0x00000e00 +#define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB) +#define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK) +#define RF5G_RF5G2_REGFE_BYPASS5_MSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_LSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100 +#define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB) +#define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK) +#define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7 +#define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6 +#define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0 +#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB) +#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) +#define RF5G_RF5G2_ENABLE_PCA_MSB 5 +#define RF5G_RF5G2_ENABLE_PCA_LSB 5 +#define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020 +#define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB) +#define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK) +#define RF5G_RF5G2_TUNE_LO_MSB 4 +#define RF5G_RF5G2_TUNE_LO_LSB 2 +#define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c +#define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB) +#define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK) +#define RF5G_RF5G2_SPARE_MSB 1 +#define RF5G_RF5G2_SPARE_LSB 0 +#define RF5G_RF5G2_SPARE_MASK 0x00000003 +#define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB) +#define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK) + +#define RF2G_RF2G1_ADDRESS 0x00000028 +#define RF2G_RF2G1_OFFSET 0x00000028 +#define RF2G_RF2G1_BLNA1_MSB 31 +#define RF2G_RF2G1_BLNA1_LSB 29 +#define RF2G_RF2G1_BLNA1_MASK 0xe0000000 +#define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB) +#define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK) +#define RF2G_RF2G1_BLNA1F_MSB 28 +#define RF2G_RF2G1_BLNA1F_LSB 26 +#define RF2G_RF2G1_BLNA1F_MASK 0x1c000000 +#define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB) +#define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK) +#define RF2G_RF2G1_BLNA1BUF_MSB 25 +#define RF2G_RF2G1_BLNA1BUF_LSB 23 +#define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000 +#define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB) +#define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK) +#define RF2G_RF2G1_BLNA2_MSB 22 +#define RF2G_RF2G1_BLNA2_LSB 20 +#define RF2G_RF2G1_BLNA2_MASK 0x00700000 +#define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB) +#define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK) +#define RF2G_RF2G1_DB_MSB 19 +#define RF2G_RF2G1_DB_LSB 17 +#define RF2G_RF2G1_DB_MASK 0x000e0000 +#define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB) +#define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK) +#define RF2G_RF2G1_OB_MSB 16 +#define RF2G_RF2G1_OB_LSB 14 +#define RF2G_RF2G1_OB_MASK 0x0001c000 +#define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB) +#define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK) +#define RF2G_RF2G1_FE_ATB_SEL_MSB 13 +#define RF2G_RF2G1_FE_ATB_SEL_LSB 11 +#define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800 +#define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB) +#define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK) +#define RF2G_RF2G1_RF_ATB_SEL_MSB 10 +#define RF2G_RF2G1_RF_ATB_SEL_LSB 8 +#define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700 +#define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB) +#define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK) +#define RF2G_RF2G1_SELLNA_MSB 7 +#define RF2G_RF2G1_SELLNA_LSB 7 +#define RF2G_RF2G1_SELLNA_MASK 0x00000080 +#define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB) +#define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK) +#define RF2G_RF2G1_LOCONTROL_MSB 6 +#define RF2G_RF2G1_LOCONTROL_LSB 6 +#define RF2G_RF2G1_LOCONTROL_MASK 0x00000040 +#define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB) +#define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK) +#define RF2G_RF2G1_SHORTLNA2_MSB 5 +#define RF2G_RF2G1_SHORTLNA2_LSB 5 +#define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020 +#define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB) +#define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK) +#define RF2G_RF2G1_SPARE_MSB 4 +#define RF2G_RF2G1_SPARE_LSB 0 +#define RF2G_RF2G1_SPARE_MASK 0x0000001f +#define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB) +#define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK) + +#define RF2G_RF2G2_ADDRESS 0x0000002c +#define RF2G_RF2G2_OFFSET 0x0000002c +#define RF2G_RF2G2_PDCGLNA_MSB 31 +#define RF2G_RF2G2_PDCGLNA_LSB 31 +#define RF2G_RF2G2_PDCGLNA_MASK 0x80000000 +#define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB) +#define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK) +#define RF2G_RF2G2_PDCGLNABUF_MSB 30 +#define RF2G_RF2G2_PDCGLNABUF_LSB 30 +#define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000 +#define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB) +#define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK) +#define RF2G_RF2G2_PDCSLNA_MSB 29 +#define RF2G_RF2G2_PDCSLNA_LSB 29 +#define RF2G_RF2G2_PDCSLNA_MASK 0x20000000 +#define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB) +#define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK) +#define RF2G_RF2G2_PDDIV_MSB 28 +#define RF2G_RF2G2_PDDIV_LSB 28 +#define RF2G_RF2G2_PDDIV_MASK 0x10000000 +#define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB) +#define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK) +#define RF2G_RF2G2_PDPADRV_MSB 27 +#define RF2G_RF2G2_PDPADRV_LSB 27 +#define RF2G_RF2G2_PDPADRV_MASK 0x08000000 +#define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB) +#define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK) +#define RF2G_RF2G2_PDPAOUT_MSB 26 +#define RF2G_RF2G2_PDPAOUT_LSB 26 +#define RF2G_RF2G2_PDPAOUT_MASK 0x04000000 +#define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB) +#define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK) +#define RF2G_RF2G2_PDREGLNA_MSB 25 +#define RF2G_RF2G2_PDREGLNA_LSB 25 +#define RF2G_RF2G2_PDREGLNA_MASK 0x02000000 +#define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB) +#define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK) +#define RF2G_RF2G2_PDREGLO_MSB 24 +#define RF2G_RF2G2_PDREGLO_LSB 24 +#define RF2G_RF2G2_PDREGLO_MASK 0x01000000 +#define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB) +#define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK) +#define RF2G_RF2G2_PDRFGM_MSB 23 +#define RF2G_RF2G2_PDRFGM_LSB 23 +#define RF2G_RF2G2_PDRFGM_MASK 0x00800000 +#define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB) +#define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK) +#define RF2G_RF2G2_PDRXLO_MSB 22 +#define RF2G_RF2G2_PDRXLO_LSB 22 +#define RF2G_RF2G2_PDRXLO_MASK 0x00400000 +#define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB) +#define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK) +#define RF2G_RF2G2_PDTXLO_MSB 21 +#define RF2G_RF2G2_PDTXLO_LSB 21 +#define RF2G_RF2G2_PDTXLO_MASK 0x00200000 +#define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB) +#define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK) +#define RF2G_RF2G2_PDTXMIX_MSB 20 +#define RF2G_RF2G2_PDTXMIX_LSB 20 +#define RF2G_RF2G2_PDTXMIX_MASK 0x00100000 +#define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB) +#define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK) +#define RF2G_RF2G2_REGLNA_BYPASS_MSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_LSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000 +#define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB) +#define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK) +#define RF2G_RF2G2_REGLO_BYPASS_MSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_LSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000 +#define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB) +#define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK) +#define RF2G_RF2G2_ENABLE_PCB_MSB 17 +#define RF2G_RF2G2_ENABLE_PCB_LSB 17 +#define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000 +#define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB) +#define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK) +#define RF2G_RF2G2_SPARE_MSB 16 +#define RF2G_RF2G2_SPARE_LSB 0 +#define RF2G_RF2G2_SPARE_MASK 0x0001ffff +#define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB) +#define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK) + +#define TOP_GAIN_ADDRESS 0x00000030 +#define TOP_GAIN_OFFSET 0x00000030 +#define TOP_GAIN_TX6DBLOQGAIN_MSB 31 +#define TOP_GAIN_TX6DBLOQGAIN_LSB 30 +#define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000 +#define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB) +#define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK) +#define TOP_GAIN_TX1DBLOQGAIN_MSB 29 +#define TOP_GAIN_TX1DBLOQGAIN_LSB 27 +#define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000 +#define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB) +#define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK) +#define TOP_GAIN_TXV2IGAIN_MSB 26 +#define TOP_GAIN_TXV2IGAIN_LSB 25 +#define TOP_GAIN_TXV2IGAIN_MASK 0x06000000 +#define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB) +#define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK) +#define TOP_GAIN_PABUF5GN_MSB 24 +#define TOP_GAIN_PABUF5GN_LSB 24 +#define TOP_GAIN_PABUF5GN_MASK 0x01000000 +#define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB) +#define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK) +#define TOP_GAIN_PADRVGN_MSB 23 +#define TOP_GAIN_PADRVGN_LSB 21 +#define TOP_GAIN_PADRVGN_MASK 0x00e00000 +#define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB) +#define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK) +#define TOP_GAIN_PAOUT2GN_MSB 20 +#define TOP_GAIN_PAOUT2GN_LSB 18 +#define TOP_GAIN_PAOUT2GN_MASK 0x001c0000 +#define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB) +#define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK) +#define TOP_GAIN_LNAON_MSB 17 +#define TOP_GAIN_LNAON_LSB 17 +#define TOP_GAIN_LNAON_MASK 0x00020000 +#define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB) +#define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK) +#define TOP_GAIN_LNAGAIN_MSB 16 +#define TOP_GAIN_LNAGAIN_LSB 13 +#define TOP_GAIN_LNAGAIN_MASK 0x0001e000 +#define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB) +#define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK) +#define TOP_GAIN_RFVGA5GAIN_MSB 12 +#define TOP_GAIN_RFVGA5GAIN_LSB 11 +#define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800 +#define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB) +#define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK) +#define TOP_GAIN_RFGMGN_MSB 10 +#define TOP_GAIN_RFGMGN_LSB 8 +#define TOP_GAIN_RFGMGN_MASK 0x00000700 +#define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB) +#define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK) +#define TOP_GAIN_RX6DBLOQGAIN_MSB 7 +#define TOP_GAIN_RX6DBLOQGAIN_LSB 6 +#define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0 +#define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB) +#define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK) +#define TOP_GAIN_RX1DBLOQGAIN_MSB 5 +#define TOP_GAIN_RX1DBLOQGAIN_LSB 3 +#define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038 +#define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB) +#define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK) +#define TOP_GAIN_RX6DBHIQGAIN_MSB 2 +#define TOP_GAIN_RX6DBHIQGAIN_LSB 1 +#define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006 +#define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB) +#define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK) +#define TOP_GAIN_SPARE_MSB 0 +#define TOP_GAIN_SPARE_LSB 0 +#define TOP_GAIN_SPARE_MASK 0x00000001 +#define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB) +#define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK) + +#define TOP_TOP_ADDRESS 0x00000034 +#define TOP_TOP_OFFSET 0x00000034 +#define TOP_TOP_LOCALTXGAIN_MSB 31 +#define TOP_TOP_LOCALTXGAIN_LSB 31 +#define TOP_TOP_LOCALTXGAIN_MASK 0x80000000 +#define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB) +#define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK) +#define TOP_TOP_LOCALRXGAIN_MSB 30 +#define TOP_TOP_LOCALRXGAIN_LSB 30 +#define TOP_TOP_LOCALRXGAIN_MASK 0x40000000 +#define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB) +#define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK) +#define TOP_TOP_LOCALMODE_MSB 29 +#define TOP_TOP_LOCALMODE_LSB 29 +#define TOP_TOP_LOCALMODE_MASK 0x20000000 +#define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB) +#define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK) +#define TOP_TOP_CALFC_MSB 28 +#define TOP_TOP_CALFC_LSB 28 +#define TOP_TOP_CALFC_MASK 0x10000000 +#define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB) +#define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK) +#define TOP_TOP_CALDC_MSB 27 +#define TOP_TOP_CALDC_LSB 27 +#define TOP_TOP_CALDC_MASK 0x08000000 +#define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB) +#define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK) +#define TOP_TOP_CAL_RESIDUE_MSB 26 +#define TOP_TOP_CAL_RESIDUE_LSB 26 +#define TOP_TOP_CAL_RESIDUE_MASK 0x04000000 +#define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB) +#define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK) +#define TOP_TOP_BMODE_MSB 25 +#define TOP_TOP_BMODE_LSB 25 +#define TOP_TOP_BMODE_MASK 0x02000000 +#define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB) +#define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK) +#define TOP_TOP_SYNTHON_MSB 24 +#define TOP_TOP_SYNTHON_LSB 24 +#define TOP_TOP_SYNTHON_MASK 0x01000000 +#define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB) +#define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK) +#define TOP_TOP_RXON_MSB 23 +#define TOP_TOP_RXON_LSB 23 +#define TOP_TOP_RXON_MASK 0x00800000 +#define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB) +#define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK) +#define TOP_TOP_TXON_MSB 22 +#define TOP_TOP_TXON_LSB 22 +#define TOP_TOP_TXON_MASK 0x00400000 +#define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB) +#define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK) +#define TOP_TOP_PAON_MSB 21 +#define TOP_TOP_PAON_LSB 21 +#define TOP_TOP_PAON_MASK 0x00200000 +#define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB) +#define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK) +#define TOP_TOP_CALTX_MSB 20 +#define TOP_TOP_CALTX_LSB 20 +#define TOP_TOP_CALTX_MASK 0x00100000 +#define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB) +#define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK) +#define TOP_TOP_LOCALADDAC_MSB 19 +#define TOP_TOP_LOCALADDAC_LSB 19 +#define TOP_TOP_LOCALADDAC_MASK 0x00080000 +#define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB) +#define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK) +#define TOP_TOP_PWDPLL_MSB 18 +#define TOP_TOP_PWDPLL_LSB 18 +#define TOP_TOP_PWDPLL_MASK 0x00040000 +#define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB) +#define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK) +#define TOP_TOP_PWDADC_MSB 17 +#define TOP_TOP_PWDADC_LSB 17 +#define TOP_TOP_PWDADC_MASK 0x00020000 +#define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB) +#define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK) +#define TOP_TOP_PWDDAC_MSB 16 +#define TOP_TOP_PWDDAC_LSB 16 +#define TOP_TOP_PWDDAC_MASK 0x00010000 +#define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB) +#define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK) +#define TOP_TOP_LOCALXTAL_MSB 15 +#define TOP_TOP_LOCALXTAL_LSB 15 +#define TOP_TOP_LOCALXTAL_MASK 0x00008000 +#define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB) +#define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK) +#define TOP_TOP_PWDCLKIN_MSB 14 +#define TOP_TOP_PWDCLKIN_LSB 14 +#define TOP_TOP_PWDCLKIN_MASK 0x00004000 +#define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB) +#define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK) +#define TOP_TOP_OSCON_MSB 13 +#define TOP_TOP_OSCON_LSB 13 +#define TOP_TOP_OSCON_MASK 0x00002000 +#define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB) +#define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK) +#define TOP_TOP_SCLKEN_FORCE_MSB 12 +#define TOP_TOP_SCLKEN_FORCE_LSB 12 +#define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000 +#define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB) +#define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK) +#define TOP_TOP_SYNTHON_FORCE_MSB 11 +#define TOP_TOP_SYNTHON_FORCE_LSB 11 +#define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800 +#define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB) +#define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK) +#define TOP_TOP_PDBIAS_MSB 10 +#define TOP_TOP_PDBIAS_LSB 10 +#define TOP_TOP_PDBIAS_MASK 0x00000400 +#define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB) +#define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK) +#define TOP_TOP_DATAOUTSEL_MSB 9 +#define TOP_TOP_DATAOUTSEL_LSB 8 +#define TOP_TOP_DATAOUTSEL_MASK 0x00000300 +#define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB) +#define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK) +#define TOP_TOP_REVID_MSB 7 +#define TOP_TOP_REVID_LSB 5 +#define TOP_TOP_REVID_MASK 0x000000e0 +#define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB) +#define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK) +#define TOP_TOP_INT2PAD_MSB 4 +#define TOP_TOP_INT2PAD_LSB 4 +#define TOP_TOP_INT2PAD_MASK 0x00000010 +#define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB) +#define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK) +#define TOP_TOP_INTH2PAD_MSB 3 +#define TOP_TOP_INTH2PAD_LSB 3 +#define TOP_TOP_INTH2PAD_MASK 0x00000008 +#define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB) +#define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK) +#define TOP_TOP_PAD2GND_MSB 2 +#define TOP_TOP_PAD2GND_LSB 2 +#define TOP_TOP_PAD2GND_MASK 0x00000004 +#define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB) +#define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK) +#define TOP_TOP_INT2GND_MSB 1 +#define TOP_TOP_INT2GND_LSB 1 +#define TOP_TOP_INT2GND_MASK 0x00000002 +#define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB) +#define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK) +#define TOP_TOP_FORCE_XPAON_MSB 0 +#define TOP_TOP_FORCE_XPAON_LSB 0 +#define TOP_TOP_FORCE_XPAON_MASK 0x00000001 +#define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB) +#define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK) + +#define BIAS_BIAS_SEL_ADDRESS 0x00000038 +#define BIAS_BIAS_SEL_OFFSET 0x00000038 +#define BIAS_BIAS_SEL_PADON_MSB 31 +#define BIAS_BIAS_SEL_PADON_LSB 31 +#define BIAS_BIAS_SEL_PADON_MASK 0x80000000 +#define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB) +#define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK) +#define BIAS_BIAS_SEL_SEL_BIAS_MSB 30 +#define BIAS_BIAS_SEL_SEL_BIAS_LSB 25 +#define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000 +#define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB) +#define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK) +#define BIAS_BIAS_SEL_SEL_SPARE_MSB 24 +#define BIAS_BIAS_SEL_SEL_SPARE_LSB 21 +#define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000 +#define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_SPARE_MSB 20 +#define BIAS_BIAS_SEL_SPARE_LSB 20 +#define BIAS_BIAS_SEL_SPARE_MASK 0x00100000 +#define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e +#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) +#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001 +#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB) +#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) + +#define BIAS_BIAS1_ADDRESS 0x0000003c +#define BIAS_BIAS1_OFFSET 0x0000003c +#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31 +#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29 +#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000 +#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB) +#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) +#define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28 +#define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26 +#define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000 +#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB) +#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) +#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25 +#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23 +#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000 +#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB) +#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) +#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22 +#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20 +#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000 +#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000 +#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000 +#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) +#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000 +#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB) +#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13 +#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11 +#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800 +#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) +#define BIAS_BIAS1_PWD_IC5GQB25_MSB 7 +#define BIAS_BIAS1_PWD_IC5GQB25_LSB 5 +#define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0 +#define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB) +#define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c +#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) +#define BIAS_BIAS1_SPARE_MSB 1 +#define BIAS_BIAS1_SPARE_LSB 0 +#define BIAS_BIAS1_SPARE_MASK 0x00000003 +#define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB) +#define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK) + +#define BIAS_BIAS2_ADDRESS 0x00000040 +#define BIAS_BIAS2_OFFSET 0x00000040 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31 +#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000 +#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB) +#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) +#define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28 +#define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26 +#define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000 +#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB) +#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) +#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25 +#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23 +#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000 +#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IRPLL25_MSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_LSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000 +#define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB) +#define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK) +#define BIAS_BIAS2_PWD_IRXTAL25_MSB 21 +#define BIAS_BIAS2_PWD_IRXTAL25_LSB 19 +#define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000 +#define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB) +#define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK) +#define BIAS_BIAS2_PWD_IRTSENS25_MSB 18 +#define BIAS_BIAS2_PWD_IRTSENS25_LSB 16 +#define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000 +#define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB) +#define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK) +#define BIAS_BIAS2_PWD_IRTXPC25_MSB 15 +#define BIAS_BIAS2_PWD_IRTXPC25_LSB 13 +#define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000 +#define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB) +#define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK) +#define BIAS_BIAS2_PWD_IRLDO25_MSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_LSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000 +#define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB) +#define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) +#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8 +#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6 +#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0 +#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) + +#define BIAS_BIAS3_ADDRESS 0x00000044 +#define BIAS_BIAS3_OFFSET 0x00000044 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) +#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) +#define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28 +#define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26 +#define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000 +#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB) +#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) +#define BIAS_BIAS3_PWD_ICDAC50_MSB 25 +#define BIAS_BIAS3_PWD_ICDAC50_LSB 23 +#define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000 +#define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB) +#define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK) +#define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000 +#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB) +#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) +#define BIAS_BIAS3_PWD_ICBB50_MSB 21 +#define BIAS_BIAS3_PWD_ICBB50_LSB 21 +#define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000 +#define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB) +#define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK) +#define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20 +#define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18 +#define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000 +#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB) +#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) +#define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000 +#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB) +#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) +#define BIAS_BIAS3_PWD_IRBB50_MSB 16 +#define BIAS_BIAS3_PWD_IRBB50_LSB 16 +#define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000 +#define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB) +#define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15 +#define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13 +#define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000 +#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12 +#define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10 +#define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00 +#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9 +#define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7 +#define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380 +#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6 +#define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4 +#define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070 +#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) +#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3 +#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1 +#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e +#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB) +#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) +#define BIAS_BIAS3_SPARE_MSB 0 +#define BIAS_BIAS3_SPARE_LSB 0 +#define BIAS_BIAS3_SPARE_MASK 0x00000001 +#define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB) +#define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK) + +#define TXPC_TXPC_ADDRESS 0x00000048 +#define TXPC_TXPC_OFFSET 0x00000048 +#define TXPC_TXPC_SELINTPD_MSB 31 +#define TXPC_TXPC_SELINTPD_LSB 31 +#define TXPC_TXPC_SELINTPD_MASK 0x80000000 +#define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB) +#define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK) +#define TXPC_TXPC_TEST_MSB 30 +#define TXPC_TXPC_TEST_LSB 30 +#define TXPC_TXPC_TEST_MASK 0x40000000 +#define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB) +#define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK) +#define TXPC_TXPC_TESTGAIN_MSB 29 +#define TXPC_TXPC_TESTGAIN_LSB 28 +#define TXPC_TXPC_TESTGAIN_MASK 0x30000000 +#define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB) +#define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK) +#define TXPC_TXPC_TESTDAC_MSB 27 +#define TXPC_TXPC_TESTDAC_LSB 22 +#define TXPC_TXPC_TESTDAC_MASK 0x0fc00000 +#define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB) +#define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK) +#define TXPC_TXPC_TESTPWDPC_MSB 21 +#define TXPC_TXPC_TESTPWDPC_LSB 21 +#define TXPC_TXPC_TESTPWDPC_MASK 0x00200000 +#define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB) +#define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK) +#define TXPC_TXPC_CURHALF_MSB 20 +#define TXPC_TXPC_CURHALF_LSB 20 +#define TXPC_TXPC_CURHALF_MASK 0x00100000 +#define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB) +#define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK) +#define TXPC_TXPC_NEGOUT_MSB 19 +#define TXPC_TXPC_NEGOUT_LSB 19 +#define TXPC_TXPC_NEGOUT_MASK 0x00080000 +#define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB) +#define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK) +#define TXPC_TXPC_CLKDELAY_MSB 18 +#define TXPC_TXPC_CLKDELAY_LSB 18 +#define TXPC_TXPC_CLKDELAY_MASK 0x00040000 +#define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB) +#define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK) +#define TXPC_TXPC_SELMODREF_MSB 17 +#define TXPC_TXPC_SELMODREF_LSB 17 +#define TXPC_TXPC_SELMODREF_MASK 0x00020000 +#define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB) +#define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK) +#define TXPC_TXPC_SELCMOUT_MSB 16 +#define TXPC_TXPC_SELCMOUT_LSB 16 +#define TXPC_TXPC_SELCMOUT_MASK 0x00010000 +#define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB) +#define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK) +#define TXPC_TXPC_TSMODE_MSB 15 +#define TXPC_TXPC_TSMODE_LSB 14 +#define TXPC_TXPC_TSMODE_MASK 0x0000c000 +#define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB) +#define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK) +#define TXPC_TXPC_N_MSB 13 +#define TXPC_TXPC_N_LSB 6 +#define TXPC_TXPC_N_MASK 0x00003fc0 +#define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB) +#define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK) +#define TXPC_TXPC_ON1STSYNTHON_MSB 5 +#define TXPC_TXPC_ON1STSYNTHON_LSB 5 +#define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020 +#define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB) +#define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK) +#define TXPC_TXPC_SELINIT_MSB 4 +#define TXPC_TXPC_SELINIT_LSB 3 +#define TXPC_TXPC_SELINIT_MASK 0x00000018 +#define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB) +#define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK) +#define TXPC_TXPC_SELCOUNT_MSB 2 +#define TXPC_TXPC_SELCOUNT_LSB 2 +#define TXPC_TXPC_SELCOUNT_MASK 0x00000004 +#define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB) +#define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK) +#define TXPC_TXPC_ATBSEL_MSB 1 +#define TXPC_TXPC_ATBSEL_LSB 0 +#define TXPC_TXPC_ATBSEL_MASK 0x00000003 +#define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB) +#define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK) + +#define TXPC_MISC_ADDRESS 0x0000004c +#define TXPC_MISC_OFFSET 0x0000004c +#define TXPC_MISC_FLIPBMODE_MSB 31 +#define TXPC_MISC_FLIPBMODE_LSB 31 +#define TXPC_MISC_FLIPBMODE_MASK 0x80000000 +#define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB) +#define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK) +#define TXPC_MISC_LEVEL_MSB 30 +#define TXPC_MISC_LEVEL_LSB 29 +#define TXPC_MISC_LEVEL_MASK 0x60000000 +#define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB) +#define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK) +#define TXPC_MISC_LDO_TEST_MODE_MSB 28 +#define TXPC_MISC_LDO_TEST_MODE_LSB 28 +#define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000 +#define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB) +#define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK) +#define TXPC_MISC_NOTCXODET_MSB 27 +#define TXPC_MISC_NOTCXODET_LSB 27 +#define TXPC_MISC_NOTCXODET_MASK 0x08000000 +#define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB) +#define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK) +#define TXPC_MISC_PWDCLKIND_MSB 26 +#define TXPC_MISC_PWDCLKIND_LSB 26 +#define TXPC_MISC_PWDCLKIND_MASK 0x04000000 +#define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB) +#define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK) +#define TXPC_MISC_PWDXINPAD_MSB 25 +#define TXPC_MISC_PWDXINPAD_LSB 25 +#define TXPC_MISC_PWDXINPAD_MASK 0x02000000 +#define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB) +#define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK) +#define TXPC_MISC_LOCALBIAS_MSB 24 +#define TXPC_MISC_LOCALBIAS_LSB 24 +#define TXPC_MISC_LOCALBIAS_MASK 0x01000000 +#define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB) +#define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK) +#define TXPC_MISC_LOCALBIAS2X_MSB 23 +#define TXPC_MISC_LOCALBIAS2X_LSB 23 +#define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000 +#define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB) +#define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK) +#define TXPC_MISC_SELTSP_MSB 22 +#define TXPC_MISC_SELTSP_LSB 22 +#define TXPC_MISC_SELTSP_MASK 0x00400000 +#define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB) +#define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK) +#define TXPC_MISC_SELTSN_MSB 21 +#define TXPC_MISC_SELTSN_LSB 21 +#define TXPC_MISC_SELTSN_MASK 0x00200000 +#define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB) +#define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK) +#define TXPC_MISC_SPARE_A_MSB 20 +#define TXPC_MISC_SPARE_A_LSB 18 +#define TXPC_MISC_SPARE_A_MASK 0x001c0000 +#define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB) +#define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK) +#define TXPC_MISC_DECOUT_MSB 17 +#define TXPC_MISC_DECOUT_LSB 8 +#define TXPC_MISC_DECOUT_MASK 0x0003ff00 +#define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB) +#define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK) +#define TXPC_MISC_XTALDIV_MSB 7 +#define TXPC_MISC_XTALDIV_LSB 6 +#define TXPC_MISC_XTALDIV_MASK 0x000000c0 +#define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB) +#define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK) +#define TXPC_MISC_SPARE_MSB 5 +#define TXPC_MISC_SPARE_LSB 0 +#define TXPC_MISC_SPARE_MASK 0x0000003f +#define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB) +#define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK) + +#define RXTXBB_RXTXBB1_ADDRESS 0x00000050 +#define RXTXBB_RXTXBB1_OFFSET 0x00000050 +#define RXTXBB_RXTXBB1_SPARE_MSB 31 +#define RXTXBB_RXTXBB1_SPARE_LSB 19 +#define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000 +#define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB) +#define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK) +#define RXTXBB_RXTXBB1_FNOTCH_MSB 18 +#define RXTXBB_RXTXBB1_FNOTCH_LSB 17 +#define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000 +#define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB) +#define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK) +#define RXTXBB_RXTXBB1_SEL_ATB_MSB 16 +#define RXTXBB_RXTXBB1_SEL_ATB_LSB 9 +#define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00 +#define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB) +#define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) +#define RXTXBB_RXTXBB1_PDV2I_MSB 7 +#define RXTXBB_RXTXBB1_PDV2I_LSB 7 +#define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080 +#define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB) +#define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK) +#define RXTXBB_RXTXBB1_PDI2V_MSB 6 +#define RXTXBB_RXTXBB1_PDI2V_LSB 6 +#define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040 +#define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB) +#define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK) +#define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020 +#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB) +#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) +#define RXTXBB_RXTXBB1_PDLOQ_MSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_LSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002 +#define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB) +#define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK) +#define RXTXBB_RXTXBB1_PDHIQ_MSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_LSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001 +#define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB) +#define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK) + +#define RXTXBB_RXTXBB2_ADDRESS 0x00000054 +#define RXTXBB_RXTXBB2_OFFSET 0x00000054 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) +#define RXTXBB_RXTXBB2_SPARE_MSB 22 +#define RXTXBB_RXTXBB2_SPARE_LSB 21 +#define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000 +#define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB) +#define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK) +#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000 +#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB) +#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) +#define RXTXBB_RXTXBB2_SELBUFFER_MSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_LSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000 +#define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB) +#define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) +#define RXTXBB_RXTXBB2_CMSEL_MSB 14 +#define RXTXBB_RXTXBB2_CMSEL_LSB 13 +#define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000 +#define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB) +#define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK) +#define RXTXBB_RXTXBB2_FILTERFC_MSB 12 +#define RXTXBB_RXTXBB2_FILTERFC_LSB 8 +#define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00 +#define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB) +#define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) + +#define RXTXBB_RXTXBB3_ADDRESS 0x00000058 +#define RXTXBB_RXTXBB3_OFFSET 0x00000058 +#define RXTXBB_RXTXBB3_SPARE_MSB 31 +#define RXTXBB_RXTXBB3_SPARE_LSB 27 +#define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000 +#define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB) +#define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) + +#define RXTXBB_RXTXBB4_ADDRESS 0x0000005c +#define RXTXBB_RXTXBB4_OFFSET 0x0000005c +#define RXTXBB_RXTXBB4_SPARE_MSB 31 +#define RXTXBB_RXTXBB4_SPARE_LSB 31 +#define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000 +#define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB) +#define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK) +#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000 +#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB) +#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29 +#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25 +#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000 +#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) + +#define ADDAC_ADDAC1_ADDRESS 0x00000060 +#define ADDAC_ADDAC1_OFFSET 0x00000060 +#define ADDAC_ADDAC1_PLL_SVREG_MSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_LSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000 +#define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB) +#define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK) +#define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30 +#define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28 +#define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000 +#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB) +#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) +#define ADDAC_ADDAC1_PLL_ATB_MSB 27 +#define ADDAC_ADDAC1_PLL_ATB_LSB 26 +#define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000 +#define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB) +#define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK) +#define ADDAC_ADDAC1_PLL_ICP_MSB 25 +#define ADDAC_ADDAC1_PLL_ICP_LSB 23 +#define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000 +#define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB) +#define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK) +#define ADDAC_ADDAC1_PLL_FILTER_MSB 22 +#define ADDAC_ADDAC1_PLL_FILTER_LSB 15 +#define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000 +#define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB) +#define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK) +#define ADDAC_ADDAC1_PWDPLL_MSB 14 +#define ADDAC_ADDAC1_PWDPLL_LSB 14 +#define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000 +#define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB) +#define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK) +#define ADDAC_ADDAC1_PWDADC_MSB 13 +#define ADDAC_ADDAC1_PWDADC_LSB 13 +#define ADDAC_ADDAC1_PWDADC_MASK 0x00002000 +#define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB) +#define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK) +#define ADDAC_ADDAC1_PWDDAC_MSB 12 +#define ADDAC_ADDAC1_PWDDAC_LSB 12 +#define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000 +#define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB) +#define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK) +#define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800 +#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB) +#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) +#define ADDAC_ADDAC1_SELMANPWDS_MSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_LSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400 +#define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB) +#define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK) +#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200 +#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB) +#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) +#define ADDAC_ADDAC1_CM_SEL_MSB 8 +#define ADDAC_ADDAC1_CM_SEL_LSB 7 +#define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180 +#define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB) +#define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) +#define ADDAC_ADDAC1_SPARE_MSB 5 +#define ADDAC_ADDAC1_SPARE_LSB 0 +#define ADDAC_ADDAC1_SPARE_MASK 0x0000003f +#define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB) +#define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_reg_reg_s { + volatile unsigned int synth_synth1; + volatile unsigned int synth_synth2; + volatile unsigned int synth_synth3; + volatile unsigned int synth_synth4; + volatile unsigned int synth_synth5; + volatile unsigned int synth_synth6; + volatile unsigned int synth_synth7; + volatile unsigned int synth_synth8; + volatile unsigned int rf5g_rf5g1; + volatile unsigned int rf5g_rf5g2; + volatile unsigned int rf2g_rf2g1; + volatile unsigned int rf2g_rf2g2; + volatile unsigned int top_gain; + volatile unsigned int top_top; + volatile unsigned int bias_bias_sel; + volatile unsigned int bias_bias1; + volatile unsigned int bias_bias2; + volatile unsigned int bias_bias3; + volatile unsigned int txpc_txpc; + volatile unsigned int txpc_misc; + volatile unsigned int rxtxbb_rxtxbb1; + volatile unsigned int rxtxbb_rxtxbb2; + volatile unsigned int rxtxbb_rxtxbb3; + volatile unsigned int rxtxbb_rxtxbb4; + volatile unsigned int addac_addac1; +} analog_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/apb_map.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/apb_map.h new file mode 100644 index 000000000000..f3bf6d6cc82b --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/apb_map.h @@ -0,0 +1,13 @@ +#ifndef _APB_MAP_H_ +#define _APB_MAP_H_ + +#define RTC_BASE_ADDRESS 0x00004000 +#define VMC_BASE_ADDRESS 0x00008000 +#define UART_BASE_ADDRESS 0x0000c000 +#define SI_BASE_ADDRESS 0x00010000 +#define GPIO_BASE_ADDRESS 0x00014000 +#define MBOX_BASE_ADDRESS 0x00018000 +#define ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define MAC_BASE_ADDRESS 0x00020000 + +#endif /* _APB_MAP_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/gpio_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/gpio_reg.h new file mode 100644 index 000000000000..4f2b964b7df3 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/gpio_reg.h @@ -0,0 +1,977 @@ +#ifndef _GPIO_REG_REG_H_ +#define _GPIO_REG_REG_H_ + +#define GPIO_OUT_ADDRESS 0x00000000 +#define GPIO_OUT_OFFSET 0x00000000 +#define GPIO_OUT_DATA_MSB 17 +#define GPIO_OUT_DATA_LSB 0 +#define GPIO_OUT_DATA_MASK 0x0003ffff +#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB) +#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK) + +#define GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define GPIO_OUT_W1TS_OFFSET 0x00000004 +#define GPIO_OUT_W1TS_DATA_MSB 17 +#define GPIO_OUT_W1TS_DATA_LSB 0 +#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB) +#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK) + +#define GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define GPIO_OUT_W1TC_OFFSET 0x00000008 +#define GPIO_OUT_W1TC_DATA_MSB 17 +#define GPIO_OUT_W1TC_DATA_LSB 0 +#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB) +#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK) + +#define GPIO_ENABLE_ADDRESS 0x0000000c +#define GPIO_ENABLE_OFFSET 0x0000000c +#define GPIO_ENABLE_DATA_MSB 17 +#define GPIO_ENABLE_DATA_LSB 0 +#define GPIO_ENABLE_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB) +#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK) + +#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define GPIO_ENABLE_W1TS_DATA_MSB 17 +#define GPIO_ENABLE_W1TS_DATA_LSB 0 +#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB) +#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK) + +#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define GPIO_ENABLE_W1TC_DATA_MSB 17 +#define GPIO_ENABLE_W1TC_DATA_LSB 0 +#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB) +#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK) + +#define GPIO_IN_ADDRESS 0x00000018 +#define GPIO_IN_OFFSET 0x00000018 +#define GPIO_IN_DATA_MSB 17 +#define GPIO_IN_DATA_LSB 0 +#define GPIO_IN_DATA_MASK 0x0003ffff +#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB) +#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK) + +#define GPIO_STATUS_ADDRESS 0x0000001c +#define GPIO_STATUS_OFFSET 0x0000001c +#define GPIO_STATUS_INTERRUPT_MSB 17 +#define GPIO_STATUS_INTERRUPT_LSB 0 +#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB) +#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define GPIO_PIN0_ADDRESS 0x00000028 +#define GPIO_PIN0_OFFSET 0x00000028 +#define GPIO_PIN0_CONFIG_MSB 12 +#define GPIO_PIN0_CONFIG_LSB 11 +#define GPIO_PIN0_CONFIG_MASK 0x00001800 +#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB) +#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define GPIO_PIN0_INT_TYPE_MSB 9 +#define GPIO_PIN0_INT_TYPE_LSB 7 +#define GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB) +#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK) +#define GPIO_PIN0_PAD_DRIVER_MSB 2 +#define GPIO_PIN0_PAD_DRIVER_LSB 2 +#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB) +#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK) +#define GPIO_PIN0_SOURCE_MSB 0 +#define GPIO_PIN0_SOURCE_LSB 0 +#define GPIO_PIN0_SOURCE_MASK 0x00000001 +#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB) +#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK) + +#define GPIO_PIN1_ADDRESS 0x0000002c +#define GPIO_PIN1_OFFSET 0x0000002c +#define GPIO_PIN1_CONFIG_MSB 12 +#define GPIO_PIN1_CONFIG_LSB 11 +#define GPIO_PIN1_CONFIG_MASK 0x00001800 +#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB) +#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define GPIO_PIN1_INT_TYPE_MSB 9 +#define GPIO_PIN1_INT_TYPE_LSB 7 +#define GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB) +#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK) +#define GPIO_PIN1_PAD_DRIVER_MSB 2 +#define GPIO_PIN1_PAD_DRIVER_LSB 2 +#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB) +#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK) +#define GPIO_PIN1_SOURCE_MSB 0 +#define GPIO_PIN1_SOURCE_LSB 0 +#define GPIO_PIN1_SOURCE_MASK 0x00000001 +#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB) +#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK) + +#define GPIO_PIN2_ADDRESS 0x00000030 +#define GPIO_PIN2_OFFSET 0x00000030 +#define GPIO_PIN2_CONFIG_MSB 12 +#define GPIO_PIN2_CONFIG_LSB 11 +#define GPIO_PIN2_CONFIG_MASK 0x00001800 +#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB) +#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define GPIO_PIN2_INT_TYPE_MSB 9 +#define GPIO_PIN2_INT_TYPE_LSB 7 +#define GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB) +#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK) +#define GPIO_PIN2_PAD_DRIVER_MSB 2 +#define GPIO_PIN2_PAD_DRIVER_LSB 2 +#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB) +#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK) +#define GPIO_PIN2_SOURCE_MSB 0 +#define GPIO_PIN2_SOURCE_LSB 0 +#define GPIO_PIN2_SOURCE_MASK 0x00000001 +#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB) +#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK) + +#define GPIO_PIN3_ADDRESS 0x00000034 +#define GPIO_PIN3_OFFSET 0x00000034 +#define GPIO_PIN3_CONFIG_MSB 12 +#define GPIO_PIN3_CONFIG_LSB 11 +#define GPIO_PIN3_CONFIG_MASK 0x00001800 +#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB) +#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define GPIO_PIN3_INT_TYPE_MSB 9 +#define GPIO_PIN3_INT_TYPE_LSB 7 +#define GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB) +#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK) +#define GPIO_PIN3_PAD_DRIVER_MSB 2 +#define GPIO_PIN3_PAD_DRIVER_LSB 2 +#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB) +#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK) +#define GPIO_PIN3_SOURCE_MSB 0 +#define GPIO_PIN3_SOURCE_LSB 0 +#define GPIO_PIN3_SOURCE_MASK 0x00000001 +#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB) +#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK) + +#define GPIO_PIN4_ADDRESS 0x00000038 +#define GPIO_PIN4_OFFSET 0x00000038 +#define GPIO_PIN4_CONFIG_MSB 12 +#define GPIO_PIN4_CONFIG_LSB 11 +#define GPIO_PIN4_CONFIG_MASK 0x00001800 +#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB) +#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define GPIO_PIN4_INT_TYPE_MSB 9 +#define GPIO_PIN4_INT_TYPE_LSB 7 +#define GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB) +#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK) +#define GPIO_PIN4_PAD_DRIVER_MSB 2 +#define GPIO_PIN4_PAD_DRIVER_LSB 2 +#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB) +#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK) +#define GPIO_PIN4_SOURCE_MSB 0 +#define GPIO_PIN4_SOURCE_LSB 0 +#define GPIO_PIN4_SOURCE_MASK 0x00000001 +#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB) +#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK) + +#define GPIO_PIN5_ADDRESS 0x0000003c +#define GPIO_PIN5_OFFSET 0x0000003c +#define GPIO_PIN5_CONFIG_MSB 12 +#define GPIO_PIN5_CONFIG_LSB 11 +#define GPIO_PIN5_CONFIG_MASK 0x00001800 +#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB) +#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define GPIO_PIN5_INT_TYPE_MSB 9 +#define GPIO_PIN5_INT_TYPE_LSB 7 +#define GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB) +#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK) +#define GPIO_PIN5_PAD_DRIVER_MSB 2 +#define GPIO_PIN5_PAD_DRIVER_LSB 2 +#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB) +#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK) +#define GPIO_PIN5_SOURCE_MSB 0 +#define GPIO_PIN5_SOURCE_LSB 0 +#define GPIO_PIN5_SOURCE_MASK 0x00000001 +#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB) +#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK) + +#define GPIO_PIN6_ADDRESS 0x00000040 +#define GPIO_PIN6_OFFSET 0x00000040 +#define GPIO_PIN6_CONFIG_MSB 12 +#define GPIO_PIN6_CONFIG_LSB 11 +#define GPIO_PIN6_CONFIG_MASK 0x00001800 +#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB) +#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define GPIO_PIN6_INT_TYPE_MSB 9 +#define GPIO_PIN6_INT_TYPE_LSB 7 +#define GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB) +#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK) +#define GPIO_PIN6_PAD_DRIVER_MSB 2 +#define GPIO_PIN6_PAD_DRIVER_LSB 2 +#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB) +#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK) +#define GPIO_PIN6_SOURCE_MSB 0 +#define GPIO_PIN6_SOURCE_LSB 0 +#define GPIO_PIN6_SOURCE_MASK 0x00000001 +#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB) +#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK) + +#define GPIO_PIN7_ADDRESS 0x00000044 +#define GPIO_PIN7_OFFSET 0x00000044 +#define GPIO_PIN7_CONFIG_MSB 12 +#define GPIO_PIN7_CONFIG_LSB 11 +#define GPIO_PIN7_CONFIG_MASK 0x00001800 +#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB) +#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define GPIO_PIN7_INT_TYPE_MSB 9 +#define GPIO_PIN7_INT_TYPE_LSB 7 +#define GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB) +#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK) +#define GPIO_PIN7_PAD_DRIVER_MSB 2 +#define GPIO_PIN7_PAD_DRIVER_LSB 2 +#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB) +#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK) +#define GPIO_PIN7_SOURCE_MSB 0 +#define GPIO_PIN7_SOURCE_LSB 0 +#define GPIO_PIN7_SOURCE_MASK 0x00000001 +#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB) +#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK) + +#define GPIO_PIN8_ADDRESS 0x00000048 +#define GPIO_PIN8_OFFSET 0x00000048 +#define GPIO_PIN8_CONFIG_MSB 12 +#define GPIO_PIN8_CONFIG_LSB 11 +#define GPIO_PIN8_CONFIG_MASK 0x00001800 +#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB) +#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define GPIO_PIN8_INT_TYPE_MSB 9 +#define GPIO_PIN8_INT_TYPE_LSB 7 +#define GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB) +#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK) +#define GPIO_PIN8_PAD_DRIVER_MSB 2 +#define GPIO_PIN8_PAD_DRIVER_LSB 2 +#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB) +#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK) +#define GPIO_PIN8_SOURCE_MSB 0 +#define GPIO_PIN8_SOURCE_LSB 0 +#define GPIO_PIN8_SOURCE_MASK 0x00000001 +#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB) +#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK) + +#define GPIO_PIN9_ADDRESS 0x0000004c +#define GPIO_PIN9_OFFSET 0x0000004c +#define GPIO_PIN9_CONFIG_MSB 12 +#define GPIO_PIN9_CONFIG_LSB 11 +#define GPIO_PIN9_CONFIG_MASK 0x00001800 +#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB) +#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define GPIO_PIN9_INT_TYPE_MSB 9 +#define GPIO_PIN9_INT_TYPE_LSB 7 +#define GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB) +#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK) +#define GPIO_PIN9_PAD_DRIVER_MSB 2 +#define GPIO_PIN9_PAD_DRIVER_LSB 2 +#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB) +#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK) +#define GPIO_PIN9_SOURCE_MSB 0 +#define GPIO_PIN9_SOURCE_LSB 0 +#define GPIO_PIN9_SOURCE_MASK 0x00000001 +#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB) +#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK) + +#define GPIO_PIN10_ADDRESS 0x00000050 +#define GPIO_PIN10_OFFSET 0x00000050 +#define GPIO_PIN10_CONFIG_MSB 12 +#define GPIO_PIN10_CONFIG_LSB 11 +#define GPIO_PIN10_CONFIG_MASK 0x00001800 +#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB) +#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define GPIO_PIN10_INT_TYPE_MSB 9 +#define GPIO_PIN10_INT_TYPE_LSB 7 +#define GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB) +#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK) +#define GPIO_PIN10_PAD_DRIVER_MSB 2 +#define GPIO_PIN10_PAD_DRIVER_LSB 2 +#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB) +#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK) +#define GPIO_PIN10_SOURCE_MSB 0 +#define GPIO_PIN10_SOURCE_LSB 0 +#define GPIO_PIN10_SOURCE_MASK 0x00000001 +#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB) +#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK) + +#define GPIO_PIN11_ADDRESS 0x00000054 +#define GPIO_PIN11_OFFSET 0x00000054 +#define GPIO_PIN11_CONFIG_MSB 12 +#define GPIO_PIN11_CONFIG_LSB 11 +#define GPIO_PIN11_CONFIG_MASK 0x00001800 +#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB) +#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define GPIO_PIN11_INT_TYPE_MSB 9 +#define GPIO_PIN11_INT_TYPE_LSB 7 +#define GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB) +#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK) +#define GPIO_PIN11_PAD_DRIVER_MSB 2 +#define GPIO_PIN11_PAD_DRIVER_LSB 2 +#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB) +#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK) +#define GPIO_PIN11_SOURCE_MSB 0 +#define GPIO_PIN11_SOURCE_LSB 0 +#define GPIO_PIN11_SOURCE_MASK 0x00000001 +#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB) +#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK) + +#define GPIO_PIN12_ADDRESS 0x00000058 +#define GPIO_PIN12_OFFSET 0x00000058 +#define GPIO_PIN12_CONFIG_MSB 12 +#define GPIO_PIN12_CONFIG_LSB 11 +#define GPIO_PIN12_CONFIG_MASK 0x00001800 +#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB) +#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define GPIO_PIN12_INT_TYPE_MSB 9 +#define GPIO_PIN12_INT_TYPE_LSB 7 +#define GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB) +#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK) +#define GPIO_PIN12_PAD_DRIVER_MSB 2 +#define GPIO_PIN12_PAD_DRIVER_LSB 2 +#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB) +#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK) +#define GPIO_PIN12_SOURCE_MSB 0 +#define GPIO_PIN12_SOURCE_LSB 0 +#define GPIO_PIN12_SOURCE_MASK 0x00000001 +#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB) +#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK) + +#define GPIO_PIN13_ADDRESS 0x0000005c +#define GPIO_PIN13_OFFSET 0x0000005c +#define GPIO_PIN13_CONFIG_MSB 12 +#define GPIO_PIN13_CONFIG_LSB 11 +#define GPIO_PIN13_CONFIG_MASK 0x00001800 +#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB) +#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define GPIO_PIN13_INT_TYPE_MSB 9 +#define GPIO_PIN13_INT_TYPE_LSB 7 +#define GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB) +#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK) +#define GPIO_PIN13_PAD_DRIVER_MSB 2 +#define GPIO_PIN13_PAD_DRIVER_LSB 2 +#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB) +#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK) +#define GPIO_PIN13_SOURCE_MSB 0 +#define GPIO_PIN13_SOURCE_LSB 0 +#define GPIO_PIN13_SOURCE_MASK 0x00000001 +#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB) +#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK) + +#define GPIO_PIN14_ADDRESS 0x00000060 +#define GPIO_PIN14_OFFSET 0x00000060 +#define GPIO_PIN14_CONFIG_MSB 12 +#define GPIO_PIN14_CONFIG_LSB 11 +#define GPIO_PIN14_CONFIG_MASK 0x00001800 +#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB) +#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define GPIO_PIN14_INT_TYPE_MSB 9 +#define GPIO_PIN14_INT_TYPE_LSB 7 +#define GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB) +#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK) +#define GPIO_PIN14_PAD_DRIVER_MSB 2 +#define GPIO_PIN14_PAD_DRIVER_LSB 2 +#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB) +#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK) +#define GPIO_PIN14_SOURCE_MSB 0 +#define GPIO_PIN14_SOURCE_LSB 0 +#define GPIO_PIN14_SOURCE_MASK 0x00000001 +#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB) +#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK) + +#define GPIO_PIN15_ADDRESS 0x00000064 +#define GPIO_PIN15_OFFSET 0x00000064 +#define GPIO_PIN15_CONFIG_MSB 12 +#define GPIO_PIN15_CONFIG_LSB 11 +#define GPIO_PIN15_CONFIG_MASK 0x00001800 +#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB) +#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define GPIO_PIN15_INT_TYPE_MSB 9 +#define GPIO_PIN15_INT_TYPE_LSB 7 +#define GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB) +#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK) +#define GPIO_PIN15_PAD_DRIVER_MSB 2 +#define GPIO_PIN15_PAD_DRIVER_LSB 2 +#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB) +#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK) +#define GPIO_PIN15_SOURCE_MSB 0 +#define GPIO_PIN15_SOURCE_LSB 0 +#define GPIO_PIN15_SOURCE_MASK 0x00000001 +#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB) +#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK) + +#define GPIO_PIN16_ADDRESS 0x00000068 +#define GPIO_PIN16_OFFSET 0x00000068 +#define GPIO_PIN16_CONFIG_MSB 12 +#define GPIO_PIN16_CONFIG_LSB 11 +#define GPIO_PIN16_CONFIG_MASK 0x00001800 +#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB) +#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define GPIO_PIN16_INT_TYPE_MSB 9 +#define GPIO_PIN16_INT_TYPE_LSB 7 +#define GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB) +#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK) +#define GPIO_PIN16_PAD_DRIVER_MSB 2 +#define GPIO_PIN16_PAD_DRIVER_LSB 2 +#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB) +#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK) +#define GPIO_PIN16_SOURCE_MSB 0 +#define GPIO_PIN16_SOURCE_LSB 0 +#define GPIO_PIN16_SOURCE_MASK 0x00000001 +#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB) +#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK) + +#define GPIO_PIN17_ADDRESS 0x0000006c +#define GPIO_PIN17_OFFSET 0x0000006c +#define GPIO_PIN17_CONFIG_MSB 12 +#define GPIO_PIN17_CONFIG_LSB 11 +#define GPIO_PIN17_CONFIG_MASK 0x00001800 +#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB) +#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define GPIO_PIN17_INT_TYPE_MSB 9 +#define GPIO_PIN17_INT_TYPE_LSB 7 +#define GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB) +#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK) +#define GPIO_PIN17_PAD_DRIVER_MSB 2 +#define GPIO_PIN17_PAD_DRIVER_LSB 2 +#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB) +#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK) +#define GPIO_PIN17_SOURCE_MSB 0 +#define GPIO_PIN17_SOURCE_LSB 0 +#define GPIO_PIN17_SOURCE_MASK 0x00000001 +#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB) +#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK) + +#define SDIO_PIN_ADDRESS 0x00000070 +#define SDIO_PIN_OFFSET 0x00000070 +#define SDIO_PIN_PAD_PULL_MSB 3 +#define SDIO_PIN_PAD_PULL_LSB 2 +#define SDIO_PIN_PAD_PULL_MASK 0x0000000c +#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB) +#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK) +#define SDIO_PIN_PAD_STRENGTH_MSB 1 +#define SDIO_PIN_PAD_STRENGTH_LSB 0 +#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB) +#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK) + +#define CLK_REQ_PIN_ADDRESS 0x00000074 +#define CLK_REQ_PIN_OFFSET 0x00000074 +#define CLK_REQ_PIN_ATE_OE_L_MSB 4 +#define CLK_REQ_PIN_ATE_OE_L_LSB 4 +#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010 +#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB) +#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK) +#define CLK_REQ_PIN_PAD_PULL_MSB 3 +#define CLK_REQ_PIN_PAD_PULL_LSB 2 +#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c +#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB) +#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK) +#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1 +#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0 +#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003 +#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB) +#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK) + +#define SIGMA_DELTA_ADDRESS 0x00000078 +#define SIGMA_DELTA_OFFSET 0x00000078 +#define SIGMA_DELTA_ENABLE_MSB 16 +#define SIGMA_DELTA_ENABLE_LSB 16 +#define SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB) +#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK) +#define SIGMA_DELTA_PRESCALAR_MSB 15 +#define SIGMA_DELTA_PRESCALAR_LSB 8 +#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB) +#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK) +#define SIGMA_DELTA_TARGET_MSB 7 +#define SIGMA_DELTA_TARGET_LSB 0 +#define SIGMA_DELTA_TARGET_MASK 0x000000ff +#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB) +#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK) + +#define DEBUG_CONTROL_ADDRESS 0x0000007c +#define DEBUG_CONTROL_OFFSET 0x0000007c +#define DEBUG_CONTROL_OBS_OE_L_MSB 1 +#define DEBUG_CONTROL_OBS_OE_L_LSB 1 +#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002 +#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB) +#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK) +#define DEBUG_CONTROL_ENABLE_MSB 0 +#define DEBUG_CONTROL_ENABLE_LSB 0 +#define DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB) +#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK) + +#define DEBUG_INPUT_SEL_ADDRESS 0x00000080 +#define DEBUG_INPUT_SEL_OFFSET 0x00000080 +#define DEBUG_INPUT_SEL_SRC_MSB 3 +#define DEBUG_INPUT_SEL_SRC_LSB 0 +#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB) +#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK) + +#define DEBUG_OUT_ADDRESS 0x00000084 +#define DEBUG_OUT_OFFSET 0x00000084 +#define DEBUG_OUT_DATA_MSB 17 +#define DEBUG_OUT_DATA_LSB 0 +#define DEBUG_OUT_DATA_MASK 0x0003ffff +#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB) +#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK) + +#define LA_CONTROL_ADDRESS 0x00000088 +#define LA_CONTROL_OFFSET 0x00000088 +#define LA_CONTROL_RUN_MSB 1 +#define LA_CONTROL_RUN_LSB 1 +#define LA_CONTROL_RUN_MASK 0x00000002 +#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB) +#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK) +#define LA_CONTROL_TRIGGERED_MSB 0 +#define LA_CONTROL_TRIGGERED_LSB 0 +#define LA_CONTROL_TRIGGERED_MASK 0x00000001 +#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB) +#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK) + +#define LA_CLOCK_ADDRESS 0x0000008c +#define LA_CLOCK_OFFSET 0x0000008c +#define LA_CLOCK_DIV_MSB 7 +#define LA_CLOCK_DIV_LSB 0 +#define LA_CLOCK_DIV_MASK 0x000000ff +#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB) +#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK) + +#define LA_STATUS_ADDRESS 0x00000090 +#define LA_STATUS_OFFSET 0x00000090 +#define LA_STATUS_INTERRUPT_MSB 0 +#define LA_STATUS_INTERRUPT_LSB 0 +#define LA_STATUS_INTERRUPT_MASK 0x00000001 +#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB) +#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK) + +#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094 +#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094 +#define LA_TRIGGER_SAMPLE_COUNT_MSB 15 +#define LA_TRIGGER_SAMPLE_COUNT_LSB 0 +#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff +#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB) +#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK) + +#define LA_TRIGGER_POSITION_ADDRESS 0x00000098 +#define LA_TRIGGER_POSITION_OFFSET 0x00000098 +#define LA_TRIGGER_POSITION_VALUE_MSB 15 +#define LA_TRIGGER_POSITION_VALUE_LSB 0 +#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff +#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB) +#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK) + +#define LA_PRE_TRIGGER_ADDRESS 0x0000009c +#define LA_PRE_TRIGGER_OFFSET 0x0000009c +#define LA_PRE_TRIGGER_COUNT_MSB 15 +#define LA_PRE_TRIGGER_COUNT_LSB 0 +#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB) +#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK) + +#define LA_POST_TRIGGER_ADDRESS 0x000000a0 +#define LA_POST_TRIGGER_OFFSET 0x000000a0 +#define LA_POST_TRIGGER_COUNT_MSB 15 +#define LA_POST_TRIGGER_COUNT_LSB 0 +#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB) +#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK) + +#define LA_FILTER_CONTROL_ADDRESS 0x000000a4 +#define LA_FILTER_CONTROL_OFFSET 0x000000a4 +#define LA_FILTER_CONTROL_DELTA_MSB 0 +#define LA_FILTER_CONTROL_DELTA_LSB 0 +#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001 +#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB) +#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK) + +#define LA_FILTER_DATA_ADDRESS 0x000000a8 +#define LA_FILTER_DATA_OFFSET 0x000000a8 +#define LA_FILTER_DATA_MATCH_MSB 17 +#define LA_FILTER_DATA_MATCH_LSB 0 +#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff +#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB) +#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK) + +#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac +#define LA_FILTER_WILDCARD_OFFSET 0x000000ac +#define LA_FILTER_WILDCARD_MATCH_MSB 17 +#define LA_FILTER_WILDCARD_MATCH_LSB 0 +#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB) +#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0 +#define LA_TRIGGERA_DATA_OFFSET 0x000000b0 +#define LA_TRIGGERA_DATA_MATCH_MSB 17 +#define LA_TRIGGERA_DATA_MATCH_LSB 0 +#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB) +#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK) + +#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4 +#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4 +#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB) +#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8 +#define LA_TRIGGERB_DATA_OFFSET 0x000000b8 +#define LA_TRIGGERB_DATA_MATCH_MSB 17 +#define LA_TRIGGERB_DATA_MATCH_LSB 0 +#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB) +#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK) + +#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc +#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc +#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB) +#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK) + +#define LA_TRIGGER_ADDRESS 0x000000c0 +#define LA_TRIGGER_OFFSET 0x000000c0 +#define LA_TRIGGER_EVENT_MSB 2 +#define LA_TRIGGER_EVENT_LSB 0 +#define LA_TRIGGER_EVENT_MASK 0x00000007 +#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB) +#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK) + +#define LA_FIFO_ADDRESS 0x000000c4 +#define LA_FIFO_OFFSET 0x000000c4 +#define LA_FIFO_FULL_MSB 1 +#define LA_FIFO_FULL_LSB 1 +#define LA_FIFO_FULL_MASK 0x00000002 +#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB) +#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK) +#define LA_FIFO_EMPTY_MSB 0 +#define LA_FIFO_EMPTY_LSB 0 +#define LA_FIFO_EMPTY_MASK 0x00000001 +#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB) +#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK) + +#define LA_ADDRESS 0x000000c8 +#define LA_OFFSET 0x000000c8 +#define LA_DATA_MSB 17 +#define LA_DATA_LSB 0 +#define LA_DATA_MASK 0x0003ffff +#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB) +#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK) + +#define ANT_PIN_ADDRESS 0x000000d0 +#define ANT_PIN_OFFSET 0x000000d0 +#define ANT_PIN_PAD_PULL_MSB 3 +#define ANT_PIN_PAD_PULL_LSB 2 +#define ANT_PIN_PAD_PULL_MASK 0x0000000c +#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB) +#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK) +#define ANT_PIN_PAD_STRENGTH_MSB 1 +#define ANT_PIN_PAD_STRENGTH_LSB 0 +#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB) +#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK) + +#define ANTD_PIN_ADDRESS 0x000000d4 +#define ANTD_PIN_OFFSET 0x000000d4 +#define ANTD_PIN_PAD_PULL_MSB 1 +#define ANTD_PIN_PAD_PULL_LSB 0 +#define ANTD_PIN_PAD_PULL_MASK 0x00000003 +#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB) +#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK) + +#define GPIO_PIN_ADDRESS 0x000000d8 +#define GPIO_PIN_OFFSET 0x000000d8 +#define GPIO_PIN_PAD_PULL_MSB 3 +#define GPIO_PIN_PAD_PULL_LSB 2 +#define GPIO_PIN_PAD_PULL_MASK 0x0000000c +#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB) +#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK) +#define GPIO_PIN_PAD_STRENGTH_MSB 1 +#define GPIO_PIN_PAD_STRENGTH_LSB 0 +#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB) +#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK) + +#define GPIO_H_PIN_ADDRESS 0x000000dc +#define GPIO_H_PIN_OFFSET 0x000000dc +#define GPIO_H_PIN_PAD_PULL_MSB 1 +#define GPIO_H_PIN_PAD_PULL_LSB 0 +#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003 +#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB) +#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK) + +#define BT_PIN_ADDRESS 0x000000e0 +#define BT_PIN_OFFSET 0x000000e0 +#define BT_PIN_PAD_PULL_MSB 3 +#define BT_PIN_PAD_PULL_LSB 2 +#define BT_PIN_PAD_PULL_MASK 0x0000000c +#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB) +#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK) +#define BT_PIN_PAD_STRENGTH_MSB 1 +#define BT_PIN_PAD_STRENGTH_LSB 0 +#define BT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB) +#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK) + +#define BT_WLAN_PIN_ADDRESS 0x000000e4 +#define BT_WLAN_PIN_OFFSET 0x000000e4 +#define BT_WLAN_PIN_PAD_PULL_MSB 1 +#define BT_WLAN_PIN_PAD_PULL_LSB 0 +#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003 +#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB) +#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK) + +#define SI_UART_PIN_ADDRESS 0x000000e8 +#define SI_UART_PIN_OFFSET 0x000000e8 +#define SI_UART_PIN_PAD_PULL_MSB 3 +#define SI_UART_PIN_PAD_PULL_LSB 2 +#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c +#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB) +#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK) +#define SI_UART_PIN_PAD_STRENGTH_MSB 1 +#define SI_UART_PIN_PAD_STRENGTH_LSB 0 +#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB) +#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK) + +#define CLK32K_PIN_ADDRESS 0x000000ec +#define CLK32K_PIN_OFFSET 0x000000ec +#define CLK32K_PIN_PAD_PULL_MSB 1 +#define CLK32K_PIN_PAD_PULL_LSB 0 +#define CLK32K_PIN_PAD_PULL_MASK 0x00000003 +#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB) +#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK) + +#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0 +#define RESET_TUPLE_STATUS_OFFSET 0x000000f0 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct gpio_reg_reg_s { + volatile unsigned int gpio_out; + volatile unsigned int gpio_out_w1ts; + volatile unsigned int gpio_out_w1tc; + volatile unsigned int gpio_enable; + volatile unsigned int gpio_enable_w1ts; + volatile unsigned int gpio_enable_w1tc; + volatile unsigned int gpio_in; + volatile unsigned int gpio_status; + volatile unsigned int gpio_status_w1ts; + volatile unsigned int gpio_status_w1tc; + volatile unsigned int gpio_pin0; + volatile unsigned int gpio_pin1; + volatile unsigned int gpio_pin2; + volatile unsigned int gpio_pin3; + volatile unsigned int gpio_pin4; + volatile unsigned int gpio_pin5; + volatile unsigned int gpio_pin6; + volatile unsigned int gpio_pin7; + volatile unsigned int gpio_pin8; + volatile unsigned int gpio_pin9; + volatile unsigned int gpio_pin10; + volatile unsigned int gpio_pin11; + volatile unsigned int gpio_pin12; + volatile unsigned int gpio_pin13; + volatile unsigned int gpio_pin14; + volatile unsigned int gpio_pin15; + volatile unsigned int gpio_pin16; + volatile unsigned int gpio_pin17; + volatile unsigned int sdio_pin; + volatile unsigned int clk_req_pin; + volatile unsigned int sigma_delta; + volatile unsigned int debug_control; + volatile unsigned int debug_input_sel; + volatile unsigned int debug_out; + volatile unsigned int la_control; + volatile unsigned int la_clock; + volatile unsigned int la_status; + volatile unsigned int la_trigger_sample; + volatile unsigned int la_trigger_position; + volatile unsigned int la_pre_trigger; + volatile unsigned int la_post_trigger; + volatile unsigned int la_filter_control; + volatile unsigned int la_filter_data; + volatile unsigned int la_filter_wildcard; + volatile unsigned int la_triggera_data; + volatile unsigned int la_triggera_wildcard; + volatile unsigned int la_triggerb_data; + volatile unsigned int la_triggerb_wildcard; + volatile unsigned int la_trigger; + volatile unsigned int la_fifo; + volatile unsigned int la[2]; + volatile unsigned int ant_pin; + volatile unsigned int antd_pin; + volatile unsigned int gpio_pin; + volatile unsigned int gpio_h_pin; + volatile unsigned int bt_pin; + volatile unsigned int bt_wlan_pin; + volatile unsigned int si_uart_pin; + volatile unsigned int clk32k_pin; + volatile unsigned int reset_tuple_status; +} gpio_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/mbox_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/mbox_host_reg.h new file mode 100644 index 000000000000..f836ae47a303 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/mbox_host_reg.h @@ -0,0 +1,386 @@ +#ifndef _MBOX_HOST_REG_REG_H_ +#define _MBOX_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_DRAGON_INT_MSB 5 +#define HOST_INT_STATUS_DRAGON_INT_LSB 5 +#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020 +#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB) +#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB) +#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define SPI_CONFIG_ADDRESS 0x00000480 +#define SPI_CONFIG_OFFSET 0x00000480 +#define SPI_CONFIG_SPI_RESET_MSB 4 +#define SPI_CONFIG_SPI_RESET_LSB 4 +#define SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB) +#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK) +#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define SPI_CONFIG_TEST_MODE_MSB 2 +#define SPI_CONFIG_TEST_MODE_LSB 2 +#define SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB) +#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK) +#define SPI_CONFIG_DATA_SIZE_MSB 1 +#define SPI_CONFIG_DATA_SIZE_LSB 0 +#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB) +#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK) + +#define SPI_STATUS_ADDRESS 0x00000481 +#define SPI_STATUS_OFFSET 0x00000481 +#define SPI_STATUS_ADDR_ERR_MSB 3 +#define SPI_STATUS_ADDR_ERR_LSB 3 +#define SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB) +#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK) +#define SPI_STATUS_RD_ERR_MSB 2 +#define SPI_STATUS_RD_ERR_LSB 2 +#define SPI_STATUS_RD_ERR_MASK 0x00000004 +#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB) +#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK) +#define SPI_STATUS_WR_ERR_MSB 1 +#define SPI_STATUS_WR_ERR_LSB 1 +#define SPI_STATUS_WR_ERR_MASK 0x00000002 +#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB) +#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK) +#define SPI_STATUS_READY_MSB 0 +#define SPI_STATUS_READY_LSB 0 +#define SPI_STATUS_READY_MASK 0x00000001 +#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB) +#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + unsigned char pad1[2]; /* pad to 0x408 */ + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad2[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad3[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad4[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad5[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad6[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char spi_config; + volatile unsigned char spi_status; + volatile unsigned char non_assoc_sleep_en; + unsigned char pad7[381]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_HOST_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/mbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/mbox_reg.h new file mode 100644 index 000000000000..4e07d2286107 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/mbox_reg.h @@ -0,0 +1,481 @@ +#ifndef _MBOX_REG_REG_H_ +#define _MBOX_REG_REG_H_ + +#define MBOX_FIFO_ADDRESS 0x00000000 +#define MBOX_FIFO_OFFSET 0x00000000 +#define MBOX_FIFO_DATA_MSB 19 +#define MBOX_FIFO_DATA_LSB 0 +#define MBOX_FIFO_DATA_MASK 0x000fffff +#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB) +#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK) + +#define MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK) +#define MBOX_FIFO_STATUS_FULL_MSB 15 +#define MBOX_FIFO_STATUS_FULL_LSB 12 +#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB) +#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK) + +#define MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define MBOX_DMA_POLICY_OFFSET 0x00000014 +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX_INT_STATUS_ADDRESS 0x00000058 +#define MBOX_INT_STATUS_OFFSET 0x00000058 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define MBOX_INT_STATUS_HOST_MSB 7 +#define MBOX_INT_STATUS_HOST_LSB 0 +#define MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB) +#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK) + +#define MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define MBOX_INT_ENABLE_OFFSET 0x0000005c +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define MBOX_INT_ENABLE_HOST_MSB 7 +#define MBOX_INT_ENABLE_HOST_LSB 0 +#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB) +#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK) + +#define INT_HOST_ADDRESS 0x00000060 +#define INT_HOST_OFFSET 0x00000060 +#define INT_HOST_VECTOR_MSB 7 +#define INT_HOST_VECTOR_LSB 0 +#define INT_HOST_VECTOR_MASK 0x000000ff +#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB) +#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK) + +#define LOCAL_COUNT_ADDRESS 0x00000080 +#define LOCAL_COUNT_OFFSET 0x00000080 +#define LOCAL_COUNT_VALUE_MSB 7 +#define LOCAL_COUNT_VALUE_LSB 0 +#define LOCAL_COUNT_VALUE_MASK 0x000000ff +#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB) +#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK) + +#define COUNT_INC_ADDRESS 0x000000a0 +#define COUNT_INC_OFFSET 0x000000a0 +#define COUNT_INC_VALUE_MSB 7 +#define COUNT_INC_VALUE_LSB 0 +#define COUNT_INC_VALUE_MASK 0x000000ff +#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB) +#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK) + +#define LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define LOCAL_SCRATCH_OFFSET 0x000000c0 +#define LOCAL_SCRATCH_VALUE_MSB 7 +#define LOCAL_SCRATCH_VALUE_LSB 0 +#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB) +#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK) + +#define USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define USE_LOCAL_BUS_OFFSET 0x000000e0 +#define USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK) + +#define SDIO_CONFIG_ADDRESS 0x000000e4 +#define SDIO_CONFIG_OFFSET 0x000000e4 +#define SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK) + +#define MBOX_DEBUG_ADDRESS 0x000000e8 +#define MBOX_DEBUG_OFFSET 0x000000e8 +#define MBOX_DEBUG_SEL_MSB 2 +#define MBOX_DEBUG_SEL_LSB 0 +#define MBOX_DEBUG_SEL_MASK 0x00000007 +#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB) +#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK) + +#define MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define MBOX_FIFO_RESET_OFFSET 0x000000ec +#define MBOX_FIFO_RESET_INIT_MSB 0 +#define MBOX_FIFO_RESET_INIT_LSB 0 +#define MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB) +#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK) + +#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define MBOX_TXFIFO_POP_DATA_MSB 0 +#define MBOX_TXFIFO_POP_DATA_LSB 0 +#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB) +#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK) + +#define MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define MBOX_RXFIFO_POP_DATA_MSB 0 +#define MBOX_RXFIFO_POP_DATA_LSB 0 +#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB) +#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK) + +#define SDIO_DEBUG_ADDRESS 0x00000110 +#define SDIO_DEBUG_OFFSET 0x00000110 +#define SDIO_DEBUG_SEL_MSB 3 +#define SDIO_DEBUG_SEL_LSB 0 +#define SDIO_DEBUG_SEL_MASK 0x0000000f +#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB) +#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK) + +#define HOST_IF_WINDOW_ADDRESS 0x00002000 +#define HOST_IF_WINDOW_OFFSET 0x00002000 +#define HOST_IF_WINDOW_DATA_MSB 7 +#define HOST_IF_WINDOW_DATA_LSB 0 +#define HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB) +#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_reg_reg_s { + volatile unsigned int mbox_fifo[4]; + volatile unsigned int mbox_fifo_status; + volatile unsigned int mbox_dma_policy; + volatile unsigned int mbox0_dma_rx_descriptor_base; + volatile unsigned int mbox0_dma_rx_control; + volatile unsigned int mbox0_dma_tx_descriptor_base; + volatile unsigned int mbox0_dma_tx_control; + volatile unsigned int mbox1_dma_rx_descriptor_base; + volatile unsigned int mbox1_dma_rx_control; + volatile unsigned int mbox1_dma_tx_descriptor_base; + volatile unsigned int mbox1_dma_tx_control; + volatile unsigned int mbox2_dma_rx_descriptor_base; + volatile unsigned int mbox2_dma_rx_control; + volatile unsigned int mbox2_dma_tx_descriptor_base; + volatile unsigned int mbox2_dma_tx_control; + volatile unsigned int mbox3_dma_rx_descriptor_base; + volatile unsigned int mbox3_dma_rx_control; + volatile unsigned int mbox3_dma_tx_descriptor_base; + volatile unsigned int mbox3_dma_tx_control; + volatile unsigned int mbox_int_status; + volatile unsigned int mbox_int_enable; + volatile unsigned int int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int local_count[8]; + volatile unsigned int count_inc[8]; + volatile unsigned int local_scratch[8]; + volatile unsigned int use_local_bus; + volatile unsigned int sdio_config; + volatile unsigned int mbox_debug; + volatile unsigned int mbox_fifo_reset; + volatile unsigned int mbox_txfifo_pop[4]; + volatile unsigned int mbox_rxfifo_pop[4]; + volatile unsigned int sdio_debug; + unsigned char pad1[7916]; /* pad to 0x2000 */ + volatile unsigned int host_if_window[2048]; +} mbox_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/rtc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/rtc_reg.h new file mode 100644 index 000000000000..8b3980afb643 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/rtc_reg.h @@ -0,0 +1,1163 @@ +#ifndef _RTC_REG_REG_H_ +#define _RTC_REG_REG_H_ + +#define RESET_CONTROL_ADDRESS 0x00000000 +#define RESET_CONTROL_OFFSET 0x00000000 +#define RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define RESET_CONTROL_RST_OUT_MSB 9 +#define RESET_CONTROL_RST_OUT_LSB 9 +#define RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB) +#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK) +#define RESET_CONTROL_COLD_RST_MSB 8 +#define RESET_CONTROL_COLD_RST_LSB 8 +#define RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB) +#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK) +#define RESET_CONTROL_WARM_RST_MSB 7 +#define RESET_CONTROL_WARM_RST_LSB 7 +#define RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB) +#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK) +#define RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK) +#define RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK) +#define RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK) +#define RESET_CONTROL_MBOX_RST_MSB 2 +#define RESET_CONTROL_MBOX_RST_LSB 2 +#define RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB) +#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK) +#define RESET_CONTROL_UART_RST_MSB 1 +#define RESET_CONTROL_UART_RST_LSB 1 +#define RESET_CONTROL_UART_RST_MASK 0x00000002 +#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB) +#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK) +#define RESET_CONTROL_SI0_RST_MSB 0 +#define RESET_CONTROL_SI0_RST_LSB 0 +#define RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB) +#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK) + +#define XTAL_CONTROL_ADDRESS 0x00000004 +#define XTAL_CONTROL_OFFSET 0x00000004 +#define XTAL_CONTROL_TCXO_MSB 0 +#define XTAL_CONTROL_TCXO_LSB 0 +#define XTAL_CONTROL_TCXO_MASK 0x00000001 +#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB) +#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK) + +#define TCXO_DETECT_ADDRESS 0x00000008 +#define TCXO_DETECT_OFFSET 0x00000008 +#define TCXO_DETECT_PRESENT_MSB 0 +#define TCXO_DETECT_PRESENT_LSB 0 +#define TCXO_DETECT_PRESENT_MASK 0x00000001 +#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB) +#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK) + +#define XTAL_TEST_ADDRESS 0x0000000c +#define XTAL_TEST_OFFSET 0x0000000c +#define XTAL_TEST_NOTCXODET_MSB 0 +#define XTAL_TEST_NOTCXODET_LSB 0 +#define XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB) +#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK) + +#define QUADRATURE_ADDRESS 0x00000010 +#define QUADRATURE_OFFSET 0x00000010 +#define QUADRATURE_ADC_MSB 5 +#define QUADRATURE_ADC_LSB 4 +#define QUADRATURE_ADC_MASK 0x00000030 +#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB) +#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK) +#define QUADRATURE_SEL_MSB 2 +#define QUADRATURE_SEL_LSB 2 +#define QUADRATURE_SEL_MASK 0x00000004 +#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB) +#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK) +#define QUADRATURE_DAC_MSB 1 +#define QUADRATURE_DAC_LSB 0 +#define QUADRATURE_DAC_MASK 0x00000003 +#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB) +#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK) + +#define PLL_CONTROL_ADDRESS 0x00000014 +#define PLL_CONTROL_OFFSET 0x00000014 +#define PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK) +#define PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK) +#define PLL_CONTROL_NOPWD_MSB 18 +#define PLL_CONTROL_NOPWD_LSB 18 +#define PLL_CONTROL_NOPWD_MASK 0x00040000 +#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB) +#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK) +#define PLL_CONTROL_UPDATING_MSB 17 +#define PLL_CONTROL_UPDATING_LSB 17 +#define PLL_CONTROL_UPDATING_MASK 0x00020000 +#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB) +#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK) +#define PLL_CONTROL_BYPASS_MSB 16 +#define PLL_CONTROL_BYPASS_LSB 16 +#define PLL_CONTROL_BYPASS_MASK 0x00010000 +#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB) +#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK) +#define PLL_CONTROL_REFDIV_MSB 15 +#define PLL_CONTROL_REFDIV_LSB 12 +#define PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB) +#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK) +#define PLL_CONTROL_DIV_MSB 9 +#define PLL_CONTROL_DIV_LSB 0 +#define PLL_CONTROL_DIV_MASK 0x000003ff +#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB) +#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK) + +#define PLL_SETTLE_ADDRESS 0x00000018 +#define PLL_SETTLE_OFFSET 0x00000018 +#define PLL_SETTLE_TIME_MSB 11 +#define PLL_SETTLE_TIME_LSB 0 +#define PLL_SETTLE_TIME_MASK 0x00000fff +#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB) +#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK) + +#define XTAL_SETTLE_ADDRESS 0x0000001c +#define XTAL_SETTLE_OFFSET 0x0000001c +#define XTAL_SETTLE_TIME_MSB 7 +#define XTAL_SETTLE_TIME_LSB 0 +#define XTAL_SETTLE_TIME_MASK 0x000000ff +#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB) +#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK) + +#define CPU_CLOCK_ADDRESS 0x00000020 +#define CPU_CLOCK_OFFSET 0x00000020 +#define CPU_CLOCK_STANDARD_MSB 1 +#define CPU_CLOCK_STANDARD_LSB 0 +#define CPU_CLOCK_STANDARD_MASK 0x00000003 +#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB) +#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) + +#define CLOCK_OUT_ADDRESS 0x00000024 +#define CLOCK_OUT_OFFSET 0x00000024 +#define CLOCK_OUT_SELECT_MSB 3 +#define CLOCK_OUT_SELECT_LSB 0 +#define CLOCK_OUT_SELECT_MASK 0x0000000f +#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB) +#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK) + +#define CLOCK_CONTROL_ADDRESS 0x00000028 +#define CLOCK_CONTROL_OFFSET 0x00000028 +#define CLOCK_CONTROL_LF_CLK32_MSB 2 +#define CLOCK_CONTROL_LF_CLK32_LSB 2 +#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB) +#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK) +#define CLOCK_CONTROL_UART_CLK_MSB 1 +#define CLOCK_CONTROL_UART_CLK_LSB 1 +#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002 +#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB) +#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK) +#define CLOCK_CONTROL_SI0_CLK_MSB 0 +#define CLOCK_CONTROL_SI0_CLK_LSB 0 +#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB) +#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK) + +#define BIAS_OVERRIDE_ADDRESS 0x0000002c +#define BIAS_OVERRIDE_OFFSET 0x0000002c +#define BIAS_OVERRIDE_ON_MSB 0 +#define BIAS_OVERRIDE_ON_LSB 0 +#define BIAS_OVERRIDE_ON_MASK 0x00000001 +#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB) +#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK) + +#define WDT_CONTROL_ADDRESS 0x00000030 +#define WDT_CONTROL_OFFSET 0x00000030 +#define WDT_CONTROL_ACTION_MSB 2 +#define WDT_CONTROL_ACTION_LSB 0 +#define WDT_CONTROL_ACTION_MASK 0x00000007 +#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB) +#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK) + +#define WDT_STATUS_ADDRESS 0x00000034 +#define WDT_STATUS_OFFSET 0x00000034 +#define WDT_STATUS_INTERRUPT_MSB 0 +#define WDT_STATUS_INTERRUPT_LSB 0 +#define WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB) +#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK) + +#define WDT_ADDRESS 0x00000038 +#define WDT_OFFSET 0x00000038 +#define WDT_TARGET_MSB 21 +#define WDT_TARGET_LSB 0 +#define WDT_TARGET_MASK 0x003fffff +#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB) +#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK) + +#define WDT_COUNT_ADDRESS 0x0000003c +#define WDT_COUNT_OFFSET 0x0000003c +#define WDT_COUNT_VALUE_MSB 21 +#define WDT_COUNT_VALUE_LSB 0 +#define WDT_COUNT_VALUE_MASK 0x003fffff +#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB) +#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK) + +#define WDT_RESET_ADDRESS 0x00000040 +#define WDT_RESET_OFFSET 0x00000040 +#define WDT_RESET_VALUE_MSB 0 +#define WDT_RESET_VALUE_LSB 0 +#define WDT_RESET_VALUE_MASK 0x00000001 +#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB) +#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK) + +#define INT_STATUS_ADDRESS 0x00000044 +#define INT_STATUS_OFFSET 0x00000044 +#define INT_STATUS_RTC_POWER_MSB 14 +#define INT_STATUS_RTC_POWER_LSB 14 +#define INT_STATUS_RTC_POWER_MASK 0x00004000 +#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB) +#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK) +#define INT_STATUS_MAC_MSB 13 +#define INT_STATUS_MAC_LSB 13 +#define INT_STATUS_MAC_MASK 0x00002000 +#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB) +#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK) +#define INT_STATUS_MAILBOX_MSB 12 +#define INT_STATUS_MAILBOX_LSB 12 +#define INT_STATUS_MAILBOX_MASK 0x00001000 +#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB) +#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK) +#define INT_STATUS_RTC_ALARM_MSB 11 +#define INT_STATUS_RTC_ALARM_LSB 11 +#define INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB) +#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK) +#define INT_STATUS_HF_TIMER_MSB 10 +#define INT_STATUS_HF_TIMER_LSB 10 +#define INT_STATUS_HF_TIMER_MASK 0x00000400 +#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB) +#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK) +#define INT_STATUS_LF_TIMER3_MSB 9 +#define INT_STATUS_LF_TIMER3_LSB 9 +#define INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB) +#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK) +#define INT_STATUS_LF_TIMER2_MSB 8 +#define INT_STATUS_LF_TIMER2_LSB 8 +#define INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB) +#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK) +#define INT_STATUS_LF_TIMER1_MSB 7 +#define INT_STATUS_LF_TIMER1_LSB 7 +#define INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB) +#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK) +#define INT_STATUS_LF_TIMER0_MSB 6 +#define INT_STATUS_LF_TIMER0_LSB 6 +#define INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB) +#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK) +#define INT_STATUS_KEYPAD_MSB 5 +#define INT_STATUS_KEYPAD_LSB 5 +#define INT_STATUS_KEYPAD_MASK 0x00000020 +#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB) +#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK) +#define INT_STATUS_SI_MSB 4 +#define INT_STATUS_SI_LSB 4 +#define INT_STATUS_SI_MASK 0x00000010 +#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB) +#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK) +#define INT_STATUS_GPIO_MSB 3 +#define INT_STATUS_GPIO_LSB 3 +#define INT_STATUS_GPIO_MASK 0x00000008 +#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB) +#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK) +#define INT_STATUS_UART_MSB 2 +#define INT_STATUS_UART_LSB 2 +#define INT_STATUS_UART_MASK 0x00000004 +#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB) +#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK) +#define INT_STATUS_ERROR_MSB 1 +#define INT_STATUS_ERROR_LSB 1 +#define INT_STATUS_ERROR_MASK 0x00000002 +#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB) +#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK) +#define INT_STATUS_WDT_INT_MSB 0 +#define INT_STATUS_WDT_INT_LSB 0 +#define INT_STATUS_WDT_INT_MASK 0x00000001 +#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB) +#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK) + +#define LF_TIMER0_ADDRESS 0x00000048 +#define LF_TIMER0_OFFSET 0x00000048 +#define LF_TIMER0_TARGET_MSB 31 +#define LF_TIMER0_TARGET_LSB 0 +#define LF_TIMER0_TARGET_MASK 0xffffffff +#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB) +#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK) + +#define LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define LF_TIMER_COUNT0_OFFSET 0x0000004c +#define LF_TIMER_COUNT0_VALUE_MSB 31 +#define LF_TIMER_COUNT0_VALUE_LSB 0 +#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB) +#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK) + +#define LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL0_RESET_MSB 0 +#define LF_TIMER_CONTROL0_RESET_LSB 0 +#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB) +#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK) + +#define LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define LF_TIMER_STATUS0_OFFSET 0x00000054 +#define LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define LF_TIMER1_ADDRESS 0x00000058 +#define LF_TIMER1_OFFSET 0x00000058 +#define LF_TIMER1_TARGET_MSB 31 +#define LF_TIMER1_TARGET_LSB 0 +#define LF_TIMER1_TARGET_MASK 0xffffffff +#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB) +#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK) + +#define LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define LF_TIMER_COUNT1_OFFSET 0x0000005c +#define LF_TIMER_COUNT1_VALUE_MSB 31 +#define LF_TIMER_COUNT1_VALUE_LSB 0 +#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB) +#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK) + +#define LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL1_RESET_MSB 0 +#define LF_TIMER_CONTROL1_RESET_LSB 0 +#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB) +#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK) + +#define LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define LF_TIMER_STATUS1_OFFSET 0x00000064 +#define LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define LF_TIMER2_ADDRESS 0x00000068 +#define LF_TIMER2_OFFSET 0x00000068 +#define LF_TIMER2_TARGET_MSB 31 +#define LF_TIMER2_TARGET_LSB 0 +#define LF_TIMER2_TARGET_MASK 0xffffffff +#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB) +#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK) + +#define LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define LF_TIMER_COUNT2_OFFSET 0x0000006c +#define LF_TIMER_COUNT2_VALUE_MSB 31 +#define LF_TIMER_COUNT2_VALUE_LSB 0 +#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB) +#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK) + +#define LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL2_RESET_MSB 0 +#define LF_TIMER_CONTROL2_RESET_LSB 0 +#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB) +#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK) + +#define LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define LF_TIMER_STATUS2_OFFSET 0x00000074 +#define LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define LF_TIMER3_ADDRESS 0x00000078 +#define LF_TIMER3_OFFSET 0x00000078 +#define LF_TIMER3_TARGET_MSB 31 +#define LF_TIMER3_TARGET_LSB 0 +#define LF_TIMER3_TARGET_MASK 0xffffffff +#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB) +#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK) + +#define LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define LF_TIMER_COUNT3_OFFSET 0x0000007c +#define LF_TIMER_COUNT3_VALUE_MSB 31 +#define LF_TIMER_COUNT3_VALUE_LSB 0 +#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB) +#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK) + +#define LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL3_RESET_MSB 0 +#define LF_TIMER_CONTROL3_RESET_LSB 0 +#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB) +#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK) + +#define LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define LF_TIMER_STATUS3_OFFSET 0x00000084 +#define LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define HF_TIMER_ADDRESS 0x00000088 +#define HF_TIMER_OFFSET 0x00000088 +#define HF_TIMER_TARGET_MSB 31 +#define HF_TIMER_TARGET_LSB 12 +#define HF_TIMER_TARGET_MASK 0xfffff000 +#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB) +#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK) + +#define HF_TIMER_COUNT_ADDRESS 0x0000008c +#define HF_TIMER_COUNT_OFFSET 0x0000008c +#define HF_TIMER_COUNT_VALUE_MSB 31 +#define HF_TIMER_COUNT_VALUE_LSB 12 +#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB) +#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK) + +#define HF_LF_COUNT_ADDRESS 0x00000090 +#define HF_LF_COUNT_OFFSET 0x00000090 +#define HF_LF_COUNT_VALUE_MSB 31 +#define HF_LF_COUNT_VALUE_LSB 0 +#define HF_LF_COUNT_VALUE_MASK 0xffffffff +#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB) +#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK) + +#define HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define HF_TIMER_CONTROL_OFFSET 0x00000094 +#define HF_TIMER_CONTROL_ENABLE_MSB 3 +#define HF_TIMER_CONTROL_ENABLE_LSB 3 +#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB) +#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK) +#define HF_TIMER_CONTROL_ON_MSB 2 +#define HF_TIMER_CONTROL_ON_LSB 2 +#define HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB) +#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define HF_TIMER_CONTROL_RESET_MSB 0 +#define HF_TIMER_CONTROL_RESET_LSB 0 +#define HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB) +#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK) + +#define HF_TIMER_STATUS_ADDRESS 0x00000098 +#define HF_TIMER_STATUS_OFFSET 0x00000098 +#define HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK) + +#define RTC_CONTROL_ADDRESS 0x0000009c +#define RTC_CONTROL_OFFSET 0x0000009c +#define RTC_CONTROL_ENABLE_MSB 2 +#define RTC_CONTROL_ENABLE_LSB 2 +#define RTC_CONTROL_ENABLE_MASK 0x00000004 +#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB) +#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK) +#define RTC_CONTROL_LOAD_RTC_MSB 1 +#define RTC_CONTROL_LOAD_RTC_LSB 1 +#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB) +#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK) +#define RTC_CONTROL_LOAD_ALARM_MSB 0 +#define RTC_CONTROL_LOAD_ALARM_LSB 0 +#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB) +#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK) + +#define RTC_TIME_ADDRESS 0x000000a0 +#define RTC_TIME_OFFSET 0x000000a0 +#define RTC_TIME_WEEK_DAY_MSB 26 +#define RTC_TIME_WEEK_DAY_LSB 24 +#define RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB) +#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK) +#define RTC_TIME_HOUR_MSB 21 +#define RTC_TIME_HOUR_LSB 16 +#define RTC_TIME_HOUR_MASK 0x003f0000 +#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB) +#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK) +#define RTC_TIME_MINUTE_MSB 14 +#define RTC_TIME_MINUTE_LSB 8 +#define RTC_TIME_MINUTE_MASK 0x00007f00 +#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB) +#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK) +#define RTC_TIME_SECOND_MSB 6 +#define RTC_TIME_SECOND_LSB 0 +#define RTC_TIME_SECOND_MASK 0x0000007f +#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB) +#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK) + +#define RTC_DATE_ADDRESS 0x000000a4 +#define RTC_DATE_OFFSET 0x000000a4 +#define RTC_DATE_YEAR_MSB 23 +#define RTC_DATE_YEAR_LSB 16 +#define RTC_DATE_YEAR_MASK 0x00ff0000 +#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB) +#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK) +#define RTC_DATE_MONTH_MSB 12 +#define RTC_DATE_MONTH_LSB 8 +#define RTC_DATE_MONTH_MASK 0x00001f00 +#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB) +#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK) +#define RTC_DATE_MONTH_DAY_MSB 5 +#define RTC_DATE_MONTH_DAY_LSB 0 +#define RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB) +#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK) + +#define RTC_SET_TIME_ADDRESS 0x000000a8 +#define RTC_SET_TIME_OFFSET 0x000000a8 +#define RTC_SET_TIME_WEEK_DAY_MSB 26 +#define RTC_SET_TIME_WEEK_DAY_LSB 24 +#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB) +#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK) +#define RTC_SET_TIME_HOUR_MSB 21 +#define RTC_SET_TIME_HOUR_LSB 16 +#define RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB) +#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK) +#define RTC_SET_TIME_MINUTE_MSB 14 +#define RTC_SET_TIME_MINUTE_LSB 8 +#define RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB) +#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK) +#define RTC_SET_TIME_SECOND_MSB 6 +#define RTC_SET_TIME_SECOND_LSB 0 +#define RTC_SET_TIME_SECOND_MASK 0x0000007f +#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB) +#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK) + +#define RTC_SET_DATE_ADDRESS 0x000000ac +#define RTC_SET_DATE_OFFSET 0x000000ac +#define RTC_SET_DATE_YEAR_MSB 23 +#define RTC_SET_DATE_YEAR_LSB 16 +#define RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB) +#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK) +#define RTC_SET_DATE_MONTH_MSB 12 +#define RTC_SET_DATE_MONTH_LSB 8 +#define RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB) +#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK) +#define RTC_SET_DATE_MONTH_DAY_MSB 5 +#define RTC_SET_DATE_MONTH_DAY_LSB 0 +#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB) +#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK) + +#define RTC_SET_ALARM_ADDRESS 0x000000b0 +#define RTC_SET_ALARM_OFFSET 0x000000b0 +#define RTC_SET_ALARM_HOUR_MSB 21 +#define RTC_SET_ALARM_HOUR_LSB 16 +#define RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB) +#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK) +#define RTC_SET_ALARM_MINUTE_MSB 14 +#define RTC_SET_ALARM_MINUTE_LSB 8 +#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB) +#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK) +#define RTC_SET_ALARM_SECOND_MSB 6 +#define RTC_SET_ALARM_SECOND_LSB 0 +#define RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB) +#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK) + +#define RTC_CONFIG_ADDRESS 0x000000b4 +#define RTC_CONFIG_OFFSET 0x000000b4 +#define RTC_CONFIG_BCD_MSB 2 +#define RTC_CONFIG_BCD_LSB 2 +#define RTC_CONFIG_BCD_MASK 0x00000004 +#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB) +#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK) +#define RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK) +#define RTC_CONFIG_DSE_MSB 0 +#define RTC_CONFIG_DSE_LSB 0 +#define RTC_CONFIG_DSE_MASK 0x00000001 +#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB) +#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK) + +#define RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define RTC_ALARM_STATUS_ENABLE_MSB 1 +#define RTC_ALARM_STATUS_ENABLE_LSB 1 +#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB) +#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK) +#define RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define UART_WAKEUP_ADDRESS 0x000000bc +#define UART_WAKEUP_OFFSET 0x000000bc +#define UART_WAKEUP_ENABLE_MSB 0 +#define UART_WAKEUP_ENABLE_LSB 0 +#define UART_WAKEUP_ENABLE_MASK 0x00000001 +#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB) +#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK) + +#define RESET_CAUSE_ADDRESS 0x000000c0 +#define RESET_CAUSE_OFFSET 0x000000c0 +#define RESET_CAUSE_LAST_MSB 2 +#define RESET_CAUSE_LAST_LSB 0 +#define RESET_CAUSE_LAST_MASK 0x00000007 +#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB) +#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK) + +#define SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define SYSTEM_SLEEP_OFFSET 0x000000c4 +#define SYSTEM_SLEEP_HOST_IF_MSB 4 +#define SYSTEM_SLEEP_HOST_IF_LSB 4 +#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB) +#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK) +#define SYSTEM_SLEEP_MBOX_MSB 3 +#define SYSTEM_SLEEP_MBOX_LSB 3 +#define SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB) +#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK) +#define SYSTEM_SLEEP_MAC_IF_MSB 2 +#define SYSTEM_SLEEP_MAC_IF_LSB 2 +#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB) +#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK) +#define SYSTEM_SLEEP_LIGHT_MSB 1 +#define SYSTEM_SLEEP_LIGHT_LSB 1 +#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB) +#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK) +#define SYSTEM_SLEEP_DISABLE_MSB 0 +#define SYSTEM_SLEEP_DISABLE_LSB 0 +#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB) +#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) + +#define SDIO_WRAPPER_ADDRESS 0x000000c8 +#define SDIO_WRAPPER_OFFSET 0x000000c8 +#define SDIO_WRAPPER_SLEEP_MSB 3 +#define SDIO_WRAPPER_SLEEP_LSB 3 +#define SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB) +#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK) +#define SDIO_WRAPPER_WAKEUP_MSB 2 +#define SDIO_WRAPPER_WAKEUP_LSB 2 +#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB) +#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK) +#define SDIO_WRAPPER_SOC_ON_MSB 1 +#define SDIO_WRAPPER_SOC_ON_LSB 1 +#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB) +#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK) +#define SDIO_WRAPPER_ON_MSB 0 +#define SDIO_WRAPPER_ON_LSB 0 +#define SDIO_WRAPPER_ON_MASK 0x00000001 +#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB) +#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK) + +#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define KEEP_AWAKE_ADDRESS 0x000000d0 +#define KEEP_AWAKE_OFFSET 0x000000d0 +#define KEEP_AWAKE_COUNT_MSB 7 +#define KEEP_AWAKE_COUNT_LSB 0 +#define KEEP_AWAKE_COUNT_MASK 0x000000ff +#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB) +#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK) + +#define LPO_CAL_TIME_ADDRESS 0x000000d4 +#define LPO_CAL_TIME_OFFSET 0x000000d4 +#define LPO_CAL_TIME_LENGTH_MSB 13 +#define LPO_CAL_TIME_LENGTH_LSB 0 +#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB) +#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK) + +#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define LPO_CAL_ADDRESS 0x000000e0 +#define LPO_CAL_OFFSET 0x000000e0 +#define LPO_CAL_ENABLE_MSB 20 +#define LPO_CAL_ENABLE_LSB 20 +#define LPO_CAL_ENABLE_MASK 0x00100000 +#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB) +#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) +#define LPO_CAL_COUNT_MSB 19 +#define LPO_CAL_COUNT_LSB 0 +#define LPO_CAL_COUNT_MASK 0x000fffff +#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB) +#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK) + +#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define LPO_CAL_TEST_STATUS_READY_MSB 16 +#define LPO_CAL_TEST_STATUS_READY_LSB 16 +#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB) +#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK) +#define LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define CHIP_ID_ADDRESS 0x000000ec +#define CHIP_ID_OFFSET 0x000000ec +#define CHIP_ID_DEVICE_ID_MSB 31 +#define CHIP_ID_DEVICE_ID_LSB 16 +#define CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB) +#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK) +#define CHIP_ID_CONFIG_ID_MSB 15 +#define CHIP_ID_CONFIG_ID_LSB 4 +#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB) +#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK) +#define CHIP_ID_VERSION_ID_MSB 3 +#define CHIP_ID_VERSION_ID_LSB 0 +#define CHIP_ID_VERSION_ID_MASK 0x0000000f +#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB) +#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK) + +#define DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define DERIVED_RTC_CLK_FORCE_MSB 17 +#define DERIVED_RTC_CLK_FORCE_LSB 16 +#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB) +#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK) +#define DERIVED_RTC_CLK_PERIOD_MSB 15 +#define DERIVED_RTC_CLK_PERIOD_LSB 1 +#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB) +#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c +#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) + +#define POWER_REG_ADDRESS 0x00000110 +#define POWER_REG_OFFSET 0x00000110 +#define POWER_REG_VLVL_MSB 11 +#define POWER_REG_VLVL_LSB 8 +#define POWER_REG_VLVL_MASK 0x00000f00 +#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB) +#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK) +#define POWER_REG_CPU_INT_ENABLE_MSB 7 +#define POWER_REG_CPU_INT_ENABLE_LSB 7 +#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB) +#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK) +#define POWER_REG_WLAN_ISO_DIS_MSB 6 +#define POWER_REG_WLAN_ISO_DIS_LSB 6 +#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB) +#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK) +#define POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK) +#define POWER_REG_RADIO_PWD_EN_MSB 4 +#define POWER_REG_RADIO_PWD_EN_LSB 4 +#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB) +#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK) +#define POWER_REG_SOC_SCALE_EN_MSB 3 +#define POWER_REG_SOC_SCALE_EN_LSB 3 +#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008 +#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB) +#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK) +#define POWER_REG_WLAN_SCALE_EN_MSB 2 +#define POWER_REG_WLAN_SCALE_EN_LSB 2 +#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004 +#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB) +#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK) +#define POWER_REG_WLAN_PWD_EN_MSB 1 +#define POWER_REG_WLAN_PWD_EN_LSB 1 +#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB) +#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK) +#define POWER_REG_POWER_EN_MSB 0 +#define POWER_REG_POWER_EN_LSB 0 +#define POWER_REG_POWER_EN_MASK 0x00000001 +#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB) +#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK) + +#define CORE_CLK_CTRL_ADDRESS 0x00000114 +#define CORE_CLK_CTRL_OFFSET 0x00000114 +#define CORE_CLK_CTRL_DIV_MSB 2 +#define CORE_CLK_CTRL_DIV_LSB 0 +#define CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB) +#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK) + +#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120 +#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120 +#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7 +#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0 +#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB) +#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) + +#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140 +#define SDIO_SETUP_CONFIG_OFFSET 0x00000140 +#define SDIO_SETUP_CONFIG_ENABLE_MSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_LSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB) +#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK) +#define SDIO_SETUP_CONFIG_CLEAR_MSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_LSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB) +#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CONFIG_ADDRESS 0x00000144 +#define CPU_SETUP_CONFIG_OFFSET 0x00000144 +#define CPU_SETUP_CONFIG_ENABLE_MSB 1 +#define CPU_SETUP_CONFIG_ENABLE_LSB 1 +#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB) +#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK) +#define CPU_SETUP_CONFIG_CLEAR_MSB 0 +#define CPU_SETUP_CONFIG_CLEAR_LSB 0 +#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB) +#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160 +#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160 +#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7 +#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0 +#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB) +#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK) + +#define BB_SETUP_CONFIG_ADDRESS 0x00000180 +#define BB_SETUP_CONFIG_OFFSET 0x00000180 +#define BB_SETUP_CONFIG_ENABLE_MSB 1 +#define BB_SETUP_CONFIG_ENABLE_LSB 1 +#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB) +#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK) +#define BB_SETUP_CONFIG_CLEAR_MSB 0 +#define BB_SETUP_CONFIG_CLEAR_LSB 0 +#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB) +#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK) + +#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0 +#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0 +#define BB_SETUP_CIRCUIT_VECTOR_MSB 7 +#define BB_SETUP_CIRCUIT_VECTOR_LSB 0 +#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB) +#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK) + +#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0 +#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rtc_reg_reg_s { + volatile unsigned int reset_control; + volatile unsigned int xtal_control; + volatile unsigned int tcxo_detect; + volatile unsigned int xtal_test; + volatile unsigned int quadrature; + volatile unsigned int pll_control; + volatile unsigned int pll_settle; + volatile unsigned int xtal_settle; + volatile unsigned int cpu_clock; + volatile unsigned int clock_out; + volatile unsigned int clock_control; + volatile unsigned int bias_override; + volatile unsigned int wdt_control; + volatile unsigned int wdt_status; + volatile unsigned int wdt; + volatile unsigned int wdt_count; + volatile unsigned int wdt_reset; + volatile unsigned int int_status; + volatile unsigned int lf_timer0; + volatile unsigned int lf_timer_count0; + volatile unsigned int lf_timer_control0; + volatile unsigned int lf_timer_status0; + volatile unsigned int lf_timer1; + volatile unsigned int lf_timer_count1; + volatile unsigned int lf_timer_control1; + volatile unsigned int lf_timer_status1; + volatile unsigned int lf_timer2; + volatile unsigned int lf_timer_count2; + volatile unsigned int lf_timer_control2; + volatile unsigned int lf_timer_status2; + volatile unsigned int lf_timer3; + volatile unsigned int lf_timer_count3; + volatile unsigned int lf_timer_control3; + volatile unsigned int lf_timer_status3; + volatile unsigned int hf_timer; + volatile unsigned int hf_timer_count; + volatile unsigned int hf_lf_count; + volatile unsigned int hf_timer_control; + volatile unsigned int hf_timer_status; + volatile unsigned int rtc_control; + volatile unsigned int rtc_time; + volatile unsigned int rtc_date; + volatile unsigned int rtc_set_time; + volatile unsigned int rtc_set_date; + volatile unsigned int rtc_set_alarm; + volatile unsigned int rtc_config; + volatile unsigned int rtc_alarm_status; + volatile unsigned int uart_wakeup; + volatile unsigned int reset_cause; + volatile unsigned int system_sleep; + volatile unsigned int sdio_wrapper; + volatile unsigned int mac_sleep_control; + volatile unsigned int keep_awake; + volatile unsigned int lpo_cal_time; + volatile unsigned int lpo_init_dividend_int; + volatile unsigned int lpo_init_dividend_fraction; + volatile unsigned int lpo_cal; + volatile unsigned int lpo_cal_test_control; + volatile unsigned int lpo_cal_test_status; + volatile unsigned int chip_id; + volatile unsigned int derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int mac_pcu_slp_beacon; + volatile unsigned int power_reg; + volatile unsigned int core_clk_ctrl; + unsigned char pad0[8]; /* pad to 0x120 */ + volatile unsigned int sdio_setup_circuit[8]; + volatile unsigned int sdio_setup_config; + volatile unsigned int cpu_setup_config; + unsigned char pad1[24]; /* pad to 0x160 */ + volatile unsigned int cpu_setup_circuit[8]; + volatile unsigned int bb_setup_config; + unsigned char pad2[28]; /* pad to 0x1a0 */ + volatile unsigned int bb_setup_circuit[8]; + volatile unsigned int gpio_wakeup_control; +} rtc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/si_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/si_reg.h new file mode 100644 index 000000000000..16fb99cfd0b8 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/si_reg.h @@ -0,0 +1,186 @@ +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s { + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/uart_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/uart_reg.h new file mode 100644 index 000000000000..5db321b72b2c --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/uart_reg.h @@ -0,0 +1,327 @@ +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define RBR_ADDRESS 0x00000000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00000000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00000000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00000004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00000004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00000008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00000008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0000000c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00000010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00000014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00000018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + +#define SCR_ADDRESS 0x0000001c +#define SCR_OFFSET 0x0000001c +#define SCR_SCR_MSB 7 +#define SCR_SCR_LSB 0 +#define SCR_SCR_MASK 0x000000ff +#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB) +#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK) + +#define SRBR_ADDRESS 0x00000020 +#define SRBR_OFFSET 0x00000020 +#define SRBR_SRBR_MSB 7 +#define SRBR_SRBR_LSB 0 +#define SRBR_SRBR_MASK 0x000000ff +#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB) +#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK) + +#define SIIR_ADDRESS 0x00000028 +#define SIIR_OFFSET 0x00000028 +#define SIIR_SIIR_MSB 7 +#define SIIR_SIIR_LSB 0 +#define SIIR_SIIR_MASK 0x000000ff +#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB) +#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK) + +#define MWR_ADDRESS 0x0000002c +#define MWR_OFFSET 0x0000002c +#define MWR_MWR_MSB 31 +#define MWR_MWR_LSB 0 +#define MWR_MWR_MASK 0xffffffff +#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB) +#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK) + +#define SLSR_ADDRESS 0x00000034 +#define SLSR_OFFSET 0x00000034 +#define SLSR_SLSR_MSB 7 +#define SLSR_SLSR_LSB 0 +#define SLSR_SLSR_MASK 0x000000ff +#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB) +#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK) + +#define SMSR_ADDRESS 0x00000038 +#define SMSR_OFFSET 0x00000038 +#define SMSR_SMSR_MSB 7 +#define SMSR_SMSR_LSB 0 +#define SMSR_SMSR_MASK 0x000000ff +#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB) +#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK) + +#define MRR_ADDRESS 0x0000003c +#define MRR_OFFSET 0x0000003c +#define MRR_MRR_MSB 31 +#define MRR_MRR_LSB 0 +#define MRR_MRR_MASK 0xffffffff +#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB) +#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s { + volatile unsigned int rbr; + volatile unsigned int dlh; + volatile unsigned int iir; + volatile unsigned int lcr; + volatile unsigned int mcr; + volatile unsigned int lsr; + volatile unsigned int msr; + volatile unsigned int scr; + volatile unsigned int srbr; + unsigned char pad0[4]; /* pad to 0x28 */ + volatile unsigned int siir; + volatile unsigned int mwr; + unsigned char pad1[4]; /* pad to 0x34 */ + volatile unsigned int slsr; + volatile unsigned int smsr; + volatile unsigned int mrr; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw.0/vmc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw.0/vmc_reg.h new file mode 100644 index 000000000000..932ec510d26b --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw.0/vmc_reg.h @@ -0,0 +1,76 @@ +#ifndef _VMC_REG_REG_H_ +#define _VMC_REG_REG_H_ + +#define MC_TCAM_VALID_ADDRESS 0x00000000 +#define MC_TCAM_VALID_OFFSET 0x00000000 +#define MC_TCAM_VALID_BIT_MSB 0 +#define MC_TCAM_VALID_BIT_LSB 0 +#define MC_TCAM_VALID_BIT_MASK 0x00000001 +#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB) +#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK) + +#define MC_TCAM_MASK_ADDRESS 0x00000080 +#define MC_TCAM_MASK_OFFSET 0x00000080 +#define MC_TCAM_MASK_SIZE_MSB 2 +#define MC_TCAM_MASK_SIZE_LSB 0 +#define MC_TCAM_MASK_SIZE_MASK 0x00000007 +#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB) +#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK) + +#define MC_TCAM_COMPARE_ADDRESS 0x00000100 +#define MC_TCAM_COMPARE_OFFSET 0x00000100 +#define MC_TCAM_COMPARE_KEY_MSB 21 +#define MC_TCAM_COMPARE_KEY_LSB 5 +#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0 +#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB) +#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK) + +#define MC_TCAM_TARGET_ADDRESS 0x00000180 +#define MC_TCAM_TARGET_OFFSET 0x00000180 +#define MC_TCAM_TARGET_ADDR_MSB 21 +#define MC_TCAM_TARGET_ADDR_LSB 5 +#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0 +#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB) +#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK) + +#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200 +#define ADDR_ERROR_CONTROL_OFFSET 0x00000200 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define ADDR_ERROR_STATUS_ADDRESS 0x00000204 +#define ADDR_ERROR_STATUS_OFFSET 0x00000204 +#define ADDR_ERROR_STATUS_WRITE_MSB 25 +#define ADDR_ERROR_STATUS_WRITE_LSB 25 +#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB) +#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK) +#define ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB) +#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct vmc_reg_reg_s { + volatile unsigned int mc_tcam_valid[32]; + volatile unsigned int mc_tcam_mask[32]; + volatile unsigned int mc_tcam_compare[32]; + volatile unsigned int mc_tcam_target[32]; + volatile unsigned int addr_error_control; + volatile unsigned int addr_error_status; +} vmc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw new file mode 120000 index 000000000000..8fae5c67cfcd --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw @@ -0,0 +1 @@ +../hw.0
\ No newline at end of file diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h new file mode 100644 index 000000000000..5970fa94d4d2 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h @@ -0,0 +1,3291 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + +/* Copyright (C) 2009 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ + + +#ifndef _ANALOG_INTF_ARES_REG_REG_H_ +#define _ANALOG_INTF_ARES_REG_REG_H_ + + +/* macros for RXRF_BIAS1 */ +#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_BIAS2 */ +#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MSB 10 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_LSB 8 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MASK 0x00000700 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MSB 13 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_LSB 11 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MASK 0x00003800 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MSB 16 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_LSB 14 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MASK 0x0001c000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MSB 19 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_LSB 17 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MASK 0x000e0000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MSB 22 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_LSB 20 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MASK 0x00700000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MSB 25 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_LSB 23 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MASK 0x03800000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXRF_GAINSTAGES */ +#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_AGC */ +#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c +#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c +#define PHY_ANALOG_RXRF_AGC_SPARE_MSB 5 +#define PHY_ANALOG_RXRF_AGC_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_AGC_SPARE_MASK 0x0000003f +#define PHY_ANALOG_RXRF_AGC_SPARE_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_RXRF_AGC_SPARE_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF1 */ +#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040 +#define PHY_ANALOG_TXRF1_OFFSET 0x00000040 +#define PHY_ANALOG_TXRF1_DCAS2G_MSB 2 +#define PHY_ANALOG_TXRF1_DCAS2G_LSB 0 +#define PHY_ANALOG_TXRF1_DCAS2G_MASK 0x00000007 +#define PHY_ANALOG_TXRF1_DCAS2G_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF1_DCAS2G_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MSB 5 +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_LSB 3 +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MASK 0x00000038 +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_TXRF1_OB2G_QAM_MSB 8 +#define PHY_ANALOG_TXRF1_OB2G_QAM_LSB 6 +#define PHY_ANALOG_TXRF1_OB2G_QAM_MASK 0x000001c0 +#define PHY_ANALOG_TXRF1_OB2G_QAM_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_TXRF1_OB2G_QAM_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_TXRF1_OB2G_PSK_MSB 11 +#define PHY_ANALOG_TXRF1_OB2G_PSK_LSB 9 +#define PHY_ANALOG_TXRF1_OB2G_PSK_MASK 0x00000e00 +#define PHY_ANALOG_TXRF1_OB2G_PSK_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_TXRF1_OB2G_PSK_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_TXRF1_OB2G_CCK_MSB 14 +#define PHY_ANALOG_TXRF1_OB2G_CCK_LSB 12 +#define PHY_ANALOG_TXRF1_OB2G_CCK_MASK 0x00007000 +#define PHY_ANALOG_TXRF1_OB2G_CCK_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF1_OB2G_CCK_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF1_DB2G_MSB 17 +#define PHY_ANALOG_TXRF1_DB2G_LSB 15 +#define PHY_ANALOG_TXRF1_DB2G_MASK 0x00038000 +#define PHY_ANALOG_TXRF1_DB2G_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_TXRF1_DB2G_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 18 +#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 18 +#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00040000 +#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_TXRF1_PDDR2G_MSB 19 +#define PHY_ANALOG_TXRF1_PDDR2G_LSB 19 +#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00080000 +#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 20 +#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 20 +#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00100000 +#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF1_PDLO2G_MSB 21 +#define PHY_ANALOG_TXRF1_PDLO2G_LSB 21 +#define PHY_ANALOG_TXRF1_PDLO2G_MASK 0x00200000 +#define PHY_ANALOG_TXRF1_PDLO2G_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF1_PDLO2G_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30 +#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24 +#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000 +#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF2 */ +#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044 +#define PHY_ANALOG_TXRF2_OFFSET 0x00000044 +#define PHY_ANALOG_TXRF2_SPARE2_MSB 0 +#define PHY_ANALOG_TXRF2_SPARE2_LSB 0 +#define PHY_ANALOG_TXRF2_SPARE2_MASK 0x00000001 +#define PHY_ANALOG_TXRF2_SPARE2_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF2_SPARE2_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF2_D3B5G_MSB 3 +#define PHY_ANALOG_TXRF2_D3B5G_LSB 1 +#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x0000000e +#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_TXRF2_D4B5G_MSB 6 +#define PHY_ANALOG_TXRF2_D4B5G_LSB 4 +#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000070 +#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 10 +#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 7 +#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x00000780 +#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x00000780) >> 7) +#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 7) & 0x00000780) +#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 11 +#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 11 +#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x00000800 +#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TXRF2_PDLOBUF5G_MSB 12 +#define PHY_ANALOG_TXRF2_PDLOBUF5G_LSB 12 +#define PHY_ANALOG_TXRF2_PDLOBUF5G_MASK 0x00001000 +#define PHY_ANALOG_TXRF2_PDLOBUF5G_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_TXRF2_PDLOBUF5G_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_TXRF2_PDLODIV5G_MSB 13 +#define PHY_ANALOG_TXRF2_PDLODIV5G_LSB 13 +#define PHY_ANALOG_TXRF2_PDLODIV5G_MASK 0x00002000 +#define PHY_ANALOG_TXRF2_PDLODIV5G_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF2_PDLODIV5G_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MSB 14 +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_LSB 14 +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MASK 0x00004000 +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MSB 15 +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_LSB 15 +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MASK 0x00008000 +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_TXRF2_PADRV2GN5G_MSB 19 +#define PHY_ANALOG_TXRF2_PADRV2GN5G_LSB 16 +#define PHY_ANALOG_TXRF2_PADRV2GN5G_MASK 0x000f0000 +#define PHY_ANALOG_TXRF2_PADRV2GN5G_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TXRF2_PADRV2GN5G_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TXRF2_PADRV3GN5G_MSB 23 +#define PHY_ANALOG_TXRF2_PADRV3GN5G_LSB 20 +#define PHY_ANALOG_TXRF2_PADRV3GN5G_MASK 0x00f00000 +#define PHY_ANALOG_TXRF2_PADRV3GN5G_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_ANALOG_TXRF2_PADRV3GN5G_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_ANALOG_TXRF2_PADRV4GN5G_MSB 27 +#define PHY_ANALOG_TXRF2_PADRV4GN5G_LSB 24 +#define PHY_ANALOG_TXRF2_PADRV4GN5G_MASK 0x0f000000 +#define PHY_ANALOG_TXRF2_PADRV4GN5G_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_ANALOG_TXRF2_PADRV4GN5G_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MSB 28 +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_LSB 28 +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MASK 0x10000000 +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TXRF2_OCAS2G_MSB 31 +#define PHY_ANALOG_TXRF2_OCAS2G_LSB 29 +#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF3 */ +#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048 +#define PHY_ANALOG_TXRF3_OFFSET 0x00000048 +#define PHY_ANALOG_TXRF3_SPARE3_MSB 22 +#define PHY_ANALOG_TXRF3_SPARE3_LSB 0 +#define PHY_ANALOG_TXRF3_SPARE3_MASK 0x007fffff +#define PHY_ANALOG_TXRF3_SPARE3_GET(x) (((x) & 0x007fffff) >> 0) +#define PHY_ANALOG_TXRF3_SPARE3_SET(x) (((x) << 0) & 0x007fffff) +#define PHY_ANALOG_TXRF3_CAS5G_MSB 25 +#define PHY_ANALOG_TXRF3_CAS5G_LSB 23 +#define PHY_ANALOG_TXRF3_CAS5G_MASK 0x03800000 +#define PHY_ANALOG_TXRF3_CAS5G_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF3_CAS5G_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF3_OB5G_MSB 28 +#define PHY_ANALOG_TXRF3_OB5G_LSB 26 +#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF3_D2B5G_MSB 31 +#define PHY_ANALOG_TXRF3_D2B5G_LSB 29 +#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF4 */ +#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c +#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 2 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 0 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x00000007 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 5 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 3 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x00000038 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 8 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 6 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x000001c0 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 11 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 9 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x00000e00 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 14 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 12 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x00007000 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 17 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 15 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0x00038000 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_TXRF4_FILTR2G_MSB 19 +#define PHY_ANALOG_TXRF4_FILTR2G_LSB 18 +#define PHY_ANALOG_TXRF4_FILTR2G_MASK 0x000c0000 +#define PHY_ANALOG_TXRF4_FILTR2G_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_TXRF4_FILTR2G_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_TXRF4_PWDFB2_2G_MSB 20 +#define PHY_ANALOG_TXRF4_PWDFB2_2G_LSB 20 +#define PHY_ANALOG_TXRF4_PWDFB2_2G_MASK 0x00100000 +#define PHY_ANALOG_TXRF4_PWDFB2_2G_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF4_PWDFB2_2G_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF4_PWDFB1_2G_MSB 21 +#define PHY_ANALOG_TXRF4_PWDFB1_2G_LSB 21 +#define PHY_ANALOG_TXRF4_PWDFB1_2G_MASK 0x00200000 +#define PHY_ANALOG_TXRF4_PWDFB1_2G_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF4_PWDFB1_2G_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF4_PDFB2G_MSB 22 +#define PHY_ANALOG_TXRF4_PDFB2G_LSB 22 +#define PHY_ANALOG_TXRF4_PDFB2G_MASK 0x00400000 +#define PHY_ANALOG_TXRF4_PDFB2G_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF4_PDFB2G_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF4_RDIV5G_MSB 24 +#define PHY_ANALOG_TXRF4_RDIV5G_LSB 23 +#define PHY_ANALOG_TXRF4_RDIV5G_MASK 0x01800000 +#define PHY_ANALOG_TXRF4_RDIV5G_GET(x) (((x) & 0x01800000) >> 23) +#define PHY_ANALOG_TXRF4_RDIV5G_SET(x) (((x) << 23) & 0x01800000) +#define PHY_ANALOG_TXRF4_CAPDIV5G_MSB 27 +#define PHY_ANALOG_TXRF4_CAPDIV5G_LSB 25 +#define PHY_ANALOG_TXRF4_CAPDIV5G_MASK 0x0e000000 +#define PHY_ANALOG_TXRF4_CAPDIV5G_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_TXRF4_CAPDIV5G_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_TXRF4_PDPREDIST5G_MSB 28 +#define PHY_ANALOG_TXRF4_PDPREDIST5G_LSB 28 +#define PHY_ANALOG_TXRF4_PDPREDIST5G_MASK 0x10000000 +#define PHY_ANALOG_TXRF4_PDPREDIST5G_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TXRF4_PDPREDIST5G_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TXRF4_RDIV2G_MSB 30 +#define PHY_ANALOG_TXRF4_RDIV2G_LSB 29 +#define PHY_ANALOG_TXRF4_RDIV2G_MASK 0x60000000 +#define PHY_ANALOG_TXRF4_RDIV2G_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_ANALOG_TXRF4_RDIV2G_SET(x) (((x) << 29) & 0x60000000) +#define PHY_ANALOG_TXRF4_PDPREDIST2G_MSB 31 +#define PHY_ANALOG_TXRF4_PDPREDIST2G_LSB 31 +#define PHY_ANALOG_TXRF4_PDPREDIST2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF4_PDPREDIST2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF4_PDPREDIST2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF5 */ +#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050 +#define PHY_ANALOG_TXRF5_OFFSET 0x00000050 +#define PHY_ANALOG_TXRF5_FBHI2G_MSB 0 +#define PHY_ANALOG_TXRF5_FBHI2G_LSB 0 +#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000001 +#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF5_FBLO2G_MSB 1 +#define PHY_ANALOG_TXRF5_FBLO2G_LSB 1 +#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000002 +#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF5_REFHI2G_MSB 4 +#define PHY_ANALOG_TXRF5_REFHI2G_LSB 2 +#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0000001c +#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF5_REFLO2G_MSB 7 +#define PHY_ANALOG_TXRF5_REFLO2G_LSB 5 +#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000000e0 +#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 9 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 8 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00000300 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 11 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 10 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x00000c00 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x00000c00) >> 10) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 10) & 0x00000c00) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 13 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 12 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x00003000 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 15 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 14 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x0000c000 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 17 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 16 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0x00030000 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MSB 19 +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_LSB 18 +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MASK 0x000c0000 +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MSB 22 +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_LSB 20 +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MASK 0x00700000 +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MSB 25 +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_LSB 23 +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MASK 0x03800000 +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MSB 28 +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_LSB 26 +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MASK 0x1c000000 +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF5_COMP2G_QAM_MSB 31 +#define PHY_ANALOG_TXRF5_COMP2G_QAM_LSB 29 +#define PHY_ANALOG_TXRF5_COMP2G_QAM_MASK 0xe0000000 +#define PHY_ANALOG_TXRF5_COMP2G_QAM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF5_COMP2G_QAM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF6 */ +#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054 +#define PHY_ANALOG_TXRF6_OFFSET 0x00000054 +#define PHY_ANALOG_TXRF6_SPARE6_MSB 0 +#define PHY_ANALOG_TXRF6_SPARE6_LSB 0 +#define PHY_ANALOG_TXRF6_SPARE6_MASK 0x00000001 +#define PHY_ANALOG_TXRF6_SPARE6_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF6_SPARE6_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF6_PAL_LOCKED_MSB 1 +#define PHY_ANALOG_TXRF6_PAL_LOCKED_LSB 1 +#define PHY_ANALOG_TXRF6_PAL_LOCKED_MASK 0x00000002 +#define PHY_ANALOG_TXRF6_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MSB 7 +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_LSB 2 +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MASK 0x000000fc +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 10 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 8 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00000700 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 11 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 11 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00000800 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 15 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 12 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x0000f000 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 18 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 16 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x00070000 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 21 +#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 19 +#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x00380000 +#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 22 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 22 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x00400000 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF6_ENPACAL2G_MSB 23 +#define PHY_ANALOG_TXRF6_ENPACAL2G_LSB 23 +#define PHY_ANALOG_TXRF6_ENPACAL2G_MASK 0x00800000 +#define PHY_ANALOG_TXRF6_ENPACAL2G_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TXRF6_ENPACAL2G_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TXRF6_OFFSET2G_MSB 30 +#define PHY_ANALOG_TXRF6_OFFSET2G_LSB 24 +#define PHY_ANALOG_TXRF6_OFFSET2G_MASK 0x7f000000 +#define PHY_ANALOG_TXRF6_OFFSET2G_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TXRF6_OFFSET2G_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MSB 31 +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_LSB 31 +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF7 */ +#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058 +#define PHY_ANALOG_TXRF7_OFFSET 0x00000058 +#define PHY_ANALOG_TXRF7_SPARE7_MSB 1 +#define PHY_ANALOG_TXRF7_SPARE7_LSB 0 +#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003 +#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF8 */ +#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c +#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c +#define PHY_ANALOG_TXRF8_SPARE8_MSB 1 +#define PHY_ANALOG_TXRF8_SPARE8_LSB 0 +#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003 +#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF9 */ +#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060 +#define PHY_ANALOG_TXRF9_OFFSET 0x00000060 +#define PHY_ANALOG_TXRF9_SPARE9_MSB 1 +#define PHY_ANALOG_TXRF9_SPARE9_LSB 0 +#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003 +#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF10 */ +#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064 +#define PHY_ANALOG_TXRF10_OFFSET 0x00000064 +#define PHY_ANALOG_TXRF10_SPARE10_MSB 12 +#define PHY_ANALOG_TXRF10_SPARE10_LSB 0 +#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00001fff +#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00001fff) >> 0) +#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00001fff) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 13 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 13 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00002000 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 16 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 14 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x0001c000 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 19 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 17 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x000e0000 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 26 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 20 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x07f00000 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x07f00000) >> 20) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 20) & 0x07f00000) +#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 29 +#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 27 +#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x38000000 +#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x38000000) >> 27) +#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 27) & 0x38000000) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 30 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 30 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x40000000 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 31 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 31 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x80000000 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF11 */ +#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068 +#define PHY_ANALOG_TXRF11_OFFSET 0x00000068 +#define PHY_ANALOG_TXRF11_SPARE11_MSB 1 +#define PHY_ANALOG_TXRF11_SPARE11_LSB 0 +#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003 +#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MSB 4 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_LSB 2 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MASK 0x0000001c +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 7 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 5 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x000000e0 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 10 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 8 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x00000700 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 13 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 11 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00003800 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 16 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 14 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 19 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 17 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x000e0000 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF12 */ +#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c +#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c +#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7 +#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0 +#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff +#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 15 +#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8 +#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x0000ff00 +#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 19 +#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 16 +#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x000f0000 +#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 22 +#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 20 +#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x00700000 +#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 25 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 23 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x03800000 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 28 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 26 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x1c000000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 31 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 29 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0xe0000000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH1 */ +#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080 +#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15 +#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13 +#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000 +#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000 +#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000 +#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH2 */ +#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084 +#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f +#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MSB 15 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_LSB 12 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MASK 0x0000f000 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_SYNTH2_CPLOWLK_MSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_LSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_MASK 0x00010000 +#define PHY_ANALOG_SYNTH2_CPLOWLK_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH2_CPLOWLK_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH2_CPBIAS_MSB 19 +#define PHY_ANALOG_SYNTH2_CPBIAS_LSB 18 +#define PHY_ANALOG_SYNTH2_CPBIAS_MASK 0x000c0000 +#define PHY_ANALOG_SYNTH2_CPBIAS_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_SYNTH2_CPBIAS_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH3 */ +#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088 +#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH4 */ +#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c +#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH4_SDM_DITHER_MSB 7 +#define PHY_ANALOG_SYNTH4_SDM_DITHER_LSB 6 +#define PHY_ANALOG_SYNTH4_SDM_DITHER_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH4_SDM_DITHER_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH4_SDM_DITHER_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100 +#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12 +#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11 +#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800 +#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH5 */ +#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090 +#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1 +#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003 +#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000) +#define PHY_ANALOG_SYNTH5_SPARE5A_MSB 31 +#define PHY_ANALOG_SYNTH5_SPARE5A_LSB 30 +#define PHY_ANALOG_SYNTH5_SPARE5A_MASK 0xc0000000 +#define PHY_ANALOG_SYNTH5_SPARE5A_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_SYNTH5_SPARE5A_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for SYNTH6 */ +#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094 +#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8 +#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2 +#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc +#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2) +#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200 +#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400 +#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000 +#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000 +#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000 +#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000 +#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for SYNTH7 */ +#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098 +#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18 +#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2 +#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc +#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2) +#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc) +#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27 +#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19 +#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000 +#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19) +#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000) +#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000 +#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH8 */ +#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c +#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31 +#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27 +#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH9 */ +#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0 +#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31 +#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27 +#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH10 */ +#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4 +#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4 +#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 0 +#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0 +#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000001 +#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 3 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 1 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000000e +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MSB 4 +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_LSB 4 +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MASK 0x00000010 +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH11 */ +#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8 +#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8 +#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4 +#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0 +#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f +#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7 +#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6 +#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH12 */ +#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac +#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac +#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 17 +#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0 +#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x0003ffff +#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x0003ffff) +#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000 +#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22 +#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19 +#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000 +#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26 +#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23 +#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000 +#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30 +#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27 +#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000 +#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BIAS1 */ +#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0 +#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0 +#define PHY_ANALOG_BIAS1_SPARE1_MSB 6 +#define PHY_ANALOG_BIAS1_SPARE1_LSB 0 +#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f +#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31 +#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25 +#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000 +#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25) +#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000) + +/* macros for BIAS2 */ +#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4 +#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4 +#define PHY_ANALOG_BIAS2_SPARE2_MSB 4 +#define PHY_ANALOG_BIAS2_SPARE2_LSB 0 +#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f +#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MSB 7 +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_LSB 5 +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MASK 0x000000e0 +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MSB 19 +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_LSB 17 +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MASK 0x000e0000 +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS3 */ +#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8 +#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8 +#define PHY_ANALOG_BIAS3_SPARE3_MSB 1 +#define PHY_ANALOG_BIAS3_SPARE3_LSB 0 +#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003 +#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MSB 4 +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_LSB 2 +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MASK 0x0000001c +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MSB 13 +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_LSB 11 +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MASK 0x00003800 +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS4 */ +#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc +#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc +#define PHY_ANALOG_BIAS4_SPARE4_MSB 13 +#define PHY_ANALOG_BIAS4_SPARE4_LSB 0 +#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x00003fff +#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MSB 22 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_LSB 20 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MASK 0x00700000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX1 */ +#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100 +#define PHY_ANALOG_RXTX1_OFFSET 0x00000100 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002 +#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c +#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18 +#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15 +#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000 +#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30 +#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27 +#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000 +#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000 +#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXTX2 */ +#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104 +#define PHY_ANALOG_RXTX2_OFFSET 0x00000104 +#define PHY_ANALOG_RXTX2_BMODE_MSB 0 +#define PHY_ANALOG_RXTX2_BMODE_LSB 0 +#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001 +#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002 +#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004 +#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX2_BW_ST_MSB 5 +#define PHY_ANALOG_RXTX2_BW_ST_LSB 4 +#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030 +#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX2_TXON_MSB 7 +#define PHY_ANALOG_RXTX2_TXON_LSB 7 +#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080 +#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX2_PAON_MSB 9 +#define PHY_ANALOG_RXTX2_PAON_LSB 9 +#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200 +#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX2_RXON_MSB 11 +#define PHY_ANALOG_RXTX2_RXON_LSB 11 +#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800 +#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000 +#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RXTX2_AGCON_MSB 13 +#define PHY_ANALOG_RXTX2_AGCON_LSB 13 +#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000 +#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000 +#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX2_TXMOD_MSB 17 +#define PHY_ANALOG_RXTX2_TXMOD_LSB 15 +#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000 +#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25 +#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24 +#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000 +#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28 +#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26 +#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000 +#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31 +#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29 +#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000 +#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX3 */ +#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108 +#define PHY_ANALOG_RXTX3_OFFSET 0x00000108 +#define PHY_ANALOG_RXTX3_SPARE3_MSB 2 +#define PHY_ANALOG_RXTX3_SPARE3_LSB 0 +#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007 +#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 3 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 3 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000008 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX3_DACRSTB_MSB 4 +#define PHY_ANALOG_RXTX3_DACRSTB_LSB 4 +#define PHY_ANALOG_RXTX3_DACRSTB_MASK 0x00000010 +#define PHY_ANALOG_RXTX3_DACRSTB_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXTX3_DACRSTB_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MSB 5 +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_LSB 5 +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MASK 0x00000020 +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040 +#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX3_DACPWD_MSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_LSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080 +#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200 +#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800) +#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000 +#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000 +#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_RXTX3_CALFC_MSB 22 +#define PHY_ANALOG_RXTX3_CALFC_LSB 22 +#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000 +#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000 +#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_RXTX3_CALTX_MSB 24 +#define PHY_ANALOG_RXTX3_CALTX_LSB 24 +#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000 +#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000 +#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_RXTX3_CALPA_MSB 28 +#define PHY_ANALOG_RXTX3_CALPA_LSB 28 +#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000 +#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXTX3_SPURON_MSB 30 +#define PHY_ANALOG_RXTX3_SPURON_LSB 30 +#define PHY_ANALOG_RXTX3_SPURON_MASK 0x40000000 +#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXTX3_SPURON_OVR_MSB 31 +#define PHY_ANALOG_RXTX3_SPURON_OVR_LSB 31 +#define PHY_ANALOG_RXTX3_SPURON_OVR_MASK 0x80000000 +#define PHY_ANALOG_RXTX3_SPURON_OVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX3_SPURON_OVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB1 */ +#define PHY_ANALOG_BB1_ADDRESS 0x00000140 +#define PHY_ANALOG_BB1_OFFSET 0x00000140 +#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001 +#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002 +#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004 +#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010 +#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100 +#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200 +#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400 +#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800 +#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000 +#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_BB1_CMSEL_MSB 15 +#define PHY_ANALOG_BB1_CMSEL_LSB 13 +#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000 +#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BB1_ATBSEL_MSB 17 +#define PHY_ANALOG_BB1_ATBSEL_LSB 16 +#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000 +#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000) +#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000 +#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31 +#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30 +#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000 +#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB2 */ +#define PHY_ANALOG_BB2_ADDRESS 0x00000144 +#define PHY_ANALOG_BB2_OFFSET 0x00000144 +#define PHY_ANALOG_BB2_SPARE_MSB 6 +#define PHY_ANALOG_BB2_SPARE_LSB 0 +#define PHY_ANALOG_BB2_SPARE_MASK 0x0000007f +#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_BB2_SEL_TEST_MSB 9 +#define PHY_ANALOG_BB2_SEL_TEST_LSB 7 +#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000380 +#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_BB2_SCFIR_CAP_MSB 14 +#define PHY_ANALOG_BB2_SCFIR_CAP_LSB 10 +#define PHY_ANALOG_BB2_SCFIR_CAP_MASK 0x00007c00 +#define PHY_ANALOG_BB2_SCFIR_CAP_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_ANALOG_BB2_SCFIR_CAP_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_LSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MASK 0x00008000 +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_BB2_FNOTCH_MSB 19 +#define PHY_ANALOG_BB2_FNOTCH_LSB 16 +#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000 +#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_BB2_FILTERFC_MSB 25 +#define PHY_ANALOG_BB2_FILTERFC_LSB 21 +#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000 +#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TOP1 */ +#define PHY_ANALOG_TOP1_ADDRESS 0x00000280 +#define PHY_ANALOG_TOP1_OFFSET 0x00000280 +#define PHY_ANALOG_TOP1_SEL_KVCO_MSB 1 +#define PHY_ANALOG_TOP1_SEL_KVCO_LSB 0 +#define PHY_ANALOG_TOP1_SEL_KVCO_MASK 0x00000003 +#define PHY_ANALOG_TOP1_SEL_KVCO_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TOP1_SEL_KVCO_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TOP1_PLLATB_MSB 3 +#define PHY_ANALOG_TOP1_PLLATB_LSB 2 +#define PHY_ANALOG_TOP1_PLLATB_MASK 0x0000000c +#define PHY_ANALOG_TOP1_PLLATB_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_TOP1_PLLATB_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_TOP1_PLL_SVREG_MSB 4 +#define PHY_ANALOG_TOP1_PLL_SVREG_LSB 4 +#define PHY_ANALOG_TOP1_PLL_SVREG_MASK 0x00000010 +#define PHY_ANALOG_TOP1_PLL_SVREG_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TOP1_PLL_SVREG_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TOP1_HI_FREQ_EN_MSB 5 +#define PHY_ANALOG_TOP1_HI_FREQ_EN_LSB 5 +#define PHY_ANALOG_TOP1_HI_FREQ_EN_MASK 0x00000020 +#define PHY_ANALOG_TOP1_HI_FREQ_EN_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TOP1_HI_FREQ_EN_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TOP1_PWDPLL_MSB 6 +#define PHY_ANALOG_TOP1_PWDPLL_LSB 6 +#define PHY_ANALOG_TOP1_PWDPLL_MASK 0x00000040 +#define PHY_ANALOG_TOP1_PWDPLL_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_TOP1_PWDPLL_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MSB 7 +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_LSB 7 +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MASK 0x00000080 +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MSB 9 +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_LSB 8 +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MASK 0x00000300 +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MSB 11 +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_LSB 10 +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MASK 0x00000c00 +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_GET(x) (((x) & 0x00000c00) >> 10) +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_SET(x) (((x) << 10) & 0x00000c00) +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MSB 13 +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_LSB 12 +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MASK 0x00003000 +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MSB 15 +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_LSB 14 +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MASK 0x0000c000 +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_TOP1_REFDIV_MSB 19 +#define PHY_ANALOG_TOP1_REFDIV_LSB 16 +#define PHY_ANALOG_TOP1_REFDIV_MASK 0x000f0000 +#define PHY_ANALOG_TOP1_REFDIV_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TOP1_REFDIV_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TOP1_DIV_MSB 29 +#define PHY_ANALOG_TOP1_DIV_LSB 20 +#define PHY_ANALOG_TOP1_DIV_MASK 0x3ff00000 +#define PHY_ANALOG_TOP1_DIV_GET(x) (((x) & 0x3ff00000) >> 20) +#define PHY_ANALOG_TOP1_DIV_SET(x) (((x) << 20) & 0x3ff00000) +#define PHY_ANALOG_TOP1_PLLBYPASS_MSB 30 +#define PHY_ANALOG_TOP1_PLLBYPASS_LSB 30 +#define PHY_ANALOG_TOP1_PLLBYPASS_MASK 0x40000000 +#define PHY_ANALOG_TOP1_PLLBYPASS_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TOP1_PLLBYPASS_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MSB 31 +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_LSB 31 +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MASK 0x80000000 +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TOP2 */ +#define PHY_ANALOG_TOP2_ADDRESS 0x00000284 +#define PHY_ANALOG_TOP2_OFFSET 0x00000284 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MSB 0 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_LSB 0 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MASK 0x00000001 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TOP2_PLL_LEAK_MSB 4 +#define PHY_ANALOG_TOP2_PLL_LEAK_LSB 1 +#define PHY_ANALOG_TOP2_PLL_LEAK_MASK 0x0000001e +#define PHY_ANALOG_TOP2_PLL_LEAK_GET(x) (((x) & 0x0000001e) >> 1) +#define PHY_ANALOG_TOP2_PLL_LEAK_SET(x) (((x) << 1) & 0x0000001e) +#define PHY_ANALOG_TOP2_PLLFRAC_MSB 19 +#define PHY_ANALOG_TOP2_PLLFRAC_LSB 5 +#define PHY_ANALOG_TOP2_PLLFRAC_MASK 0x000fffe0 +#define PHY_ANALOG_TOP2_PLLFRAC_GET(x) (((x) & 0x000fffe0) >> 5) +#define PHY_ANALOG_TOP2_PLLFRAC_SET(x) (((x) << 5) & 0x000fffe0) +#define PHY_ANALOG_TOP2_PWD_PLLSDM_MSB 20 +#define PHY_ANALOG_TOP2_PWD_PLLSDM_LSB 20 +#define PHY_ANALOG_TOP2_PWD_PLLSDM_MASK 0x00100000 +#define PHY_ANALOG_TOP2_PWD_PLLSDM_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TOP2_PWD_PLLSDM_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TOP2_PLLICP_MSB 23 +#define PHY_ANALOG_TOP2_PLLICP_LSB 21 +#define PHY_ANALOG_TOP2_PLLICP_MASK 0x00e00000 +#define PHY_ANALOG_TOP2_PLLICP_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_TOP2_PLLICP_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_TOP2_PLLFILTER_MSB 31 +#define PHY_ANALOG_TOP2_PLLFILTER_LSB 24 +#define PHY_ANALOG_TOP2_PLLFILTER_MASK 0xff000000 +#define PHY_ANALOG_TOP2_PLLFILTER_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_ANALOG_TOP2_PLLFILTER_SET(x) (((x) << 24) & 0xff000000) + +/* macros for TOP3 */ +#define PHY_ANALOG_TOP3_ADDRESS 0x00000288 +#define PHY_ANALOG_TOP3_OFFSET 0x00000288 +#define PHY_ANALOG_TOP3_INT2GND_MSB 0 +#define PHY_ANALOG_TOP3_INT2GND_LSB 0 +#define PHY_ANALOG_TOP3_INT2GND_MASK 0x00000001 +#define PHY_ANALOG_TOP3_INT2GND_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TOP3_INT2GND_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TOP3_PWDPALCLK_MSB 1 +#define PHY_ANALOG_TOP3_PWDPALCLK_LSB 1 +#define PHY_ANALOG_TOP3_PWDPALCLK_MASK 0x00000002 +#define PHY_ANALOG_TOP3_PWDPALCLK_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TOP3_PWDPALCLK_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_TOP3_PWDAGCCLK_MSB 2 +#define PHY_ANALOG_TOP3_PWDAGCCLK_LSB 2 +#define PHY_ANALOG_TOP3_PWDAGCCLK_MASK 0x00000004 +#define PHY_ANALOG_TOP3_PWDAGCCLK_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TOP3_PWDAGCCLK_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_TOP3_PWDV2I_MSB 3 +#define PHY_ANALOG_TOP3_PWDV2I_LSB 3 +#define PHY_ANALOG_TOP3_PWDV2I_MASK 0x00000008 +#define PHY_ANALOG_TOP3_PWDV2I_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TOP3_PWDV2I_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TOP3_PWDBIAS_MSB 4 +#define PHY_ANALOG_TOP3_PWDBIAS_LSB 4 +#define PHY_ANALOG_TOP3_PWDBIAS_MASK 0x00000010 +#define PHY_ANALOG_TOP3_PWDBIAS_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TOP3_PWDBIAS_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TOP3_PWDBG_MSB 5 +#define PHY_ANALOG_TOP3_PWDBG_LSB 5 +#define PHY_ANALOG_TOP3_PWDBG_MASK 0x00000020 +#define PHY_ANALOG_TOP3_PWDBG_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TOP3_PWDBG_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TOP3_XTAL_SELVREG_MSB 6 +#define PHY_ANALOG_TOP3_XTAL_SELVREG_LSB 6 +#define PHY_ANALOG_TOP3_XTAL_SELVREG_MASK 0x00000040 +#define PHY_ANALOG_TOP3_XTAL_SELVREG_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_TOP3_XTAL_SELVREG_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_TOP3_XTAL_PWDREG_MSB 7 +#define PHY_ANALOG_TOP3_XTAL_PWDREG_LSB 7 +#define PHY_ANALOG_TOP3_XTAL_PWDREG_MASK 0x00000080 +#define PHY_ANALOG_TOP3_XTAL_PWDREG_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_TOP3_XTAL_PWDREG_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MSB 8 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_LSB 8 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MASK 0x00000100 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MSB 9 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_LSB 9 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MASK 0x00000200 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_TOP3_XTAL_OSCON_MSB 10 +#define PHY_ANALOG_TOP3_XTAL_OSCON_LSB 10 +#define PHY_ANALOG_TOP3_XTAL_OSCON_MASK 0x00000400 +#define PHY_ANALOG_TOP3_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_TOP3_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MSB 11 +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_LSB 11 +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MASK 0x00000800 +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MSB 12 +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_LSB 12 +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MASK 0x00001000 +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MSB 13 +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_LSB 13 +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MASK 0x00002000 +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MSB 15 +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_LSB 14 +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MASK 0x0000c000 +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MSB 22 +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_LSB 16 +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MASK 0x007f0000 +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MSB 29 +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_LSB 23 +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MASK 0x3f800000 +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MSB 30 +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_LSB 30 +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MASK 0x40000000 +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TOP3_TCXODET_MSB 31 +#define PHY_ANALOG_TOP3_TCXODET_LSB 31 +#define PHY_ANALOG_TOP3_TCXODET_MASK 0x80000000 +#define PHY_ANALOG_TOP3_TCXODET_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for TOP4 */ +#define PHY_ANALOG_TOP4_ADDRESS 0x0000028c +#define PHY_ANALOG_TOP4_OFFSET 0x0000028c +#define PHY_ANALOG_TOP4_SPARE4_MSB 19 +#define PHY_ANALOG_TOP4_SPARE4_LSB 0 +#define PHY_ANALOG_TOP4_SPARE4_MASK 0x000fffff +#define PHY_ANALOG_TOP4_SPARE4_GET(x) (((x) & 0x000fffff) >> 0) +#define PHY_ANALOG_TOP4_SPARE4_SET(x) (((x) << 0) & 0x000fffff) +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MSB 20 +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_LSB 20 +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MASK 0x00100000 +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TOP4_ADCPWD_OVR_MSB 21 +#define PHY_ANALOG_TOP4_ADCPWD_OVR_LSB 21 +#define PHY_ANALOG_TOP4_ADCPWD_OVR_MASK 0x00200000 +#define PHY_ANALOG_TOP4_ADCPWD_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TOP4_ADCPWD_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TOP4_ADCPWD_INT_MSB 22 +#define PHY_ANALOG_TOP4_ADCPWD_INT_LSB 22 +#define PHY_ANALOG_TOP4_ADCPWD_INT_MASK 0x00400000 +#define PHY_ANALOG_TOP4_ADCPWD_INT_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TOP4_ADCPWD_INT_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TOP4_TESTIQ_OFF_MSB 23 +#define PHY_ANALOG_TOP4_TESTIQ_OFF_LSB 23 +#define PHY_ANALOG_TOP4_TESTIQ_OFF_MASK 0x00800000 +#define PHY_ANALOG_TOP4_TESTIQ_OFF_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TOP4_TESTIQ_OFF_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MSB 24 +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_LSB 24 +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MASK 0x01000000 +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MSB 25 +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_LSB 25 +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MASK 0x02000000 +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MSB 26 +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_LSB 26 +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MASK 0x04000000 +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_TOP4_ENBTCLK_MSB 27 +#define PHY_ANALOG_TOP4_ENBTCLK_LSB 27 +#define PHY_ANALOG_TOP4_ENBTCLK_MASK 0x08000000 +#define PHY_ANALOG_TOP4_ENBTCLK_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_TOP4_ENBTCLK_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_TOP4_PAD2GND_MSB 28 +#define PHY_ANALOG_TOP4_PAD2GND_LSB 28 +#define PHY_ANALOG_TOP4_PAD2GND_MASK 0x10000000 +#define PHY_ANALOG_TOP4_PAD2GND_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TOP4_PAD2GND_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TOP4_INTH2PAD_MSB 29 +#define PHY_ANALOG_TOP4_INTH2PAD_LSB 29 +#define PHY_ANALOG_TOP4_INTH2PAD_MASK 0x20000000 +#define PHY_ANALOG_TOP4_INTH2PAD_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_TOP4_INTH2PAD_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_TOP4_INTH2GND_MSB 30 +#define PHY_ANALOG_TOP4_INTH2GND_LSB 30 +#define PHY_ANALOG_TOP4_INTH2GND_MASK 0x40000000 +#define PHY_ANALOG_TOP4_INTH2GND_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TOP4_INTH2GND_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TOP4_INT2PAD_MSB 31 +#define PHY_ANALOG_TOP4_INT2PAD_LSB 31 +#define PHY_ANALOG_TOP4_INT2PAD_MASK 0x80000000 +#define PHY_ANALOG_TOP4_INT2PAD_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TOP4_INT2PAD_SET(x) (((x) << 31) & 0x80000000) + +/* macros for rbist_cntrl */ +#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000) + +/* macros for tx_dc_offset */ +#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000) + +/* macros for tx_tonegen0 */ +#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_tonegen1 */ +#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_lftonegen0 */ +#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_linear_ramp_i */ +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_linear_ramp_q */ +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_prbs_mag */ +#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for tx_prbs_seed_i */ +#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for tx_prbs_seed_q */ +#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for cmac_dc_cancel */ +#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for cmac_dc_offset */ +#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_corr */ +#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00) + +/* macros for cmac_power */ +#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_cross_corr */ +#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_i2q2 */ +#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_power_hpf */ +#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0) + +/* macros for rxdac_set1 */ +#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000) + +/* macros for rxdac_set2 */ +#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000) + +/* macros for rxdac_long_shift */ +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00) + +/* macros for cmac_results_i */ +#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for cmac_results_q */ +#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for PMU1 */ +#define PHY_ANALOG_PMU1_ADDRESS 0x00000740 +#define PHY_ANALOG_PMU1_OFFSET 0x00000740 +#define PHY_ANALOG_PMU1_SPARE_MSB 10 +#define PHY_ANALOG_PMU1_SPARE_LSB 0 +#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff +#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000 +#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000 +#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000 +#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for PMU2 */ +#define PHY_ANALOG_PMU2_ADDRESS 0x00000744 +#define PHY_ANALOG_PMU2_OFFSET 0x00000744 +#define PHY_ANALOG_PMU2_SPARE_MSB 7 +#define PHY_ANALOG_PMU2_SPARE_LSB 0 +#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff +#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000) +#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27 +#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25 +#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000 +#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000 +#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_ares_reg_reg_s { + volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */ + volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */ + volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */ + volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */ + volatile char pad__0[0x30]; /* 0x10 - 0x40 */ + volatile unsigned int TXRF1; /* 0x40 - 0x44 */ + volatile unsigned int TXRF2; /* 0x44 - 0x48 */ + volatile unsigned int TXRF3; /* 0x48 - 0x4c */ + volatile unsigned int TXRF4; /* 0x4c - 0x50 */ + volatile unsigned int TXRF5; /* 0x50 - 0x54 */ + volatile unsigned int TXRF6; /* 0x54 - 0x58 */ + volatile unsigned int TXRF7; /* 0x58 - 0x5c */ + volatile unsigned int TXRF8; /* 0x5c - 0x60 */ + volatile unsigned int TXRF9; /* 0x60 - 0x64 */ + volatile unsigned int TXRF10; /* 0x64 - 0x68 */ + volatile unsigned int TXRF11; /* 0x68 - 0x6c */ + volatile unsigned int TXRF12; /* 0x6c - 0x70 */ + volatile char pad__1[0x10]; /* 0x70 - 0x80 */ + volatile unsigned int SYNTH1; /* 0x80 - 0x84 */ + volatile unsigned int SYNTH2; /* 0x84 - 0x88 */ + volatile unsigned int SYNTH3; /* 0x88 - 0x8c */ + volatile unsigned int SYNTH4; /* 0x8c - 0x90 */ + volatile unsigned int SYNTH5; /* 0x90 - 0x94 */ + volatile unsigned int SYNTH6; /* 0x94 - 0x98 */ + volatile unsigned int SYNTH7; /* 0x98 - 0x9c */ + volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */ + volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */ + volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */ + volatile unsigned int SYNTH11; /* 0xa8 - 0xac */ + volatile unsigned int SYNTH12; /* 0xac - 0xb0 */ + volatile char pad__2[0x10]; /* 0xb0 - 0xc0 */ + volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */ + volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */ + volatile unsigned int BIAS3; /* 0xc8 - 0xcc */ + volatile unsigned int BIAS4; /* 0xcc - 0xd0 */ + volatile char pad__3[0x30]; /* 0xd0 - 0x100 */ + volatile unsigned int RXTX1; /* 0x100 - 0x104 */ + volatile unsigned int RXTX2; /* 0x104 - 0x108 */ + volatile unsigned int RXTX3; /* 0x108 - 0x10c */ + volatile char pad__4[0x34]; /* 0x10c - 0x140 */ + volatile unsigned int BB1; /* 0x140 - 0x144 */ + volatile unsigned int BB2; /* 0x144 - 0x148 */ + volatile char pad__5[0x138]; /* 0x148 - 0x280 */ + volatile unsigned int TOP1; /* 0x280 - 0x284 */ + volatile unsigned int TOP2; /* 0x284 - 0x288 */ + volatile unsigned int TOP3; /* 0x288 - 0x28c */ + volatile unsigned int TOP4; /* 0x28c - 0x290 */ + volatile char pad__6[0xf0]; /* 0x290 - 0x380 */ + volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */ + volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */ + volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */ + volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */ + volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */ + volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */ + volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */ + volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */ + volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */ + volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */ + volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */ + volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */ + volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */ + volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */ + volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */ + volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */ + volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */ + volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */ + volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */ + volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */ + volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */ + volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */ + volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */ + volatile unsigned int PMU1; /* 0x740 - 0x744 */ + volatile unsigned int PMU2; /* 0x744 - 0x748 */ +} analog_intf_ares_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_ARES_REG_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h new file mode 100644 index 000000000000..1c243fbbc810 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h @@ -0,0 +1,3674 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + +/* Copyright (C) 2009 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ + + +#ifndef _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ +#define _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ + + +/* macros for RXRF_BIAS1 */ +#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_BIAS2 */ +#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MSB 10 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_LSB 8 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MASK 0x00000700 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MSB 13 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_LSB 11 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MASK 0x00003800 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MSB 16 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_LSB 14 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MASK 0x0001c000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MSB 19 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_LSB 17 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MASK 0x000e0000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MSB 22 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_LSB 20 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MASK 0x00700000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MSB 25 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_LSB 23 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MASK 0x03800000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXRF_GAINSTAGES */ +#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_AGC */ +#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c +#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MSB 0 +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_LSB 0 +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MASK 0x00000001 +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MSB 1 +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_LSB 1 +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MASK 0x00000002 +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MSB 2 +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_LSB 2 +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MASK 0x00000004 +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MSB 3 +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_LSB 3 +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MASK 0x00000008 +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MSB 4 +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_LSB 4 +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MASK 0x00000010 +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MSB 5 +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_LSB 5 +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MASK 0x00000020 +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF1 */ +#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040 +#define PHY_ANALOG_TXRF1_OFFSET 0x00000040 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_MSB 0 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_LSB 0 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_MASK 0x00000001 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF1_PDLOBUF5G_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF1_PDLODIV5G_MSB 1 +#define PHY_ANALOG_TXRF1_PDLODIV5G_LSB 1 +#define PHY_ANALOG_TXRF1_PDLODIV5G_MASK 0x00000002 +#define PHY_ANALOG_TXRF1_PDLODIV5G_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF1_PDLODIV5G_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MSB 2 +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_LSB 2 +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MASK 0x00000004 +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MSB 3 +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_LSB 3 +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MASK 0x00000008 +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TXRF1_PADRV2GN5G_MSB 7 +#define PHY_ANALOG_TXRF1_PADRV2GN5G_LSB 4 +#define PHY_ANALOG_TXRF1_PADRV2GN5G_MASK 0x000000f0 +#define PHY_ANALOG_TXRF1_PADRV2GN5G_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_TXRF1_PADRV2GN5G_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_TXRF1_PADRV3GN5G_MSB 11 +#define PHY_ANALOG_TXRF1_PADRV3GN5G_LSB 8 +#define PHY_ANALOG_TXRF1_PADRV3GN5G_MASK 0x00000f00 +#define PHY_ANALOG_TXRF1_PADRV3GN5G_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TXRF1_PADRV3GN5G_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TXRF1_PADRV4GN5G_MSB 15 +#define PHY_ANALOG_TXRF1_PADRV4GN5G_LSB 12 +#define PHY_ANALOG_TXRF1_PADRV4GN5G_MASK 0x0000f000 +#define PHY_ANALOG_TXRF1_PADRV4GN5G_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_TXRF1_PADRV4GN5G_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MSB 16 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_LSB 16 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MASK 0x00010000 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 17 +#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 17 +#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00020000 +#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_TXRF1_PDDR2G_MSB 18 +#define PHY_ANALOG_TXRF1_PDDR2G_LSB 18 +#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00040000 +#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 19 +#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 19 +#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00080000 +#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_TXRF1_PDLOBUF2G_MSB 20 +#define PHY_ANALOG_TXRF1_PDLOBUF2G_LSB 20 +#define PHY_ANALOG_TXRF1_PDLOBUF2G_MASK 0x00100000 +#define PHY_ANALOG_TXRF1_PDLOBUF2G_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF1_PDLOBUF2G_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF1_PDLODIV2G_MSB 21 +#define PHY_ANALOG_TXRF1_PDLODIV2G_LSB 21 +#define PHY_ANALOG_TXRF1_PDLODIV2G_MASK 0x00200000 +#define PHY_ANALOG_TXRF1_PDLODIV2G_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF1_PDLODIV2G_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30 +#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24 +#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000 +#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF2 */ +#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044 +#define PHY_ANALOG_TXRF2_OFFSET 0x00000044 +#define PHY_ANALOG_TXRF2_D3B5G_MSB 2 +#define PHY_ANALOG_TXRF2_D3B5G_LSB 0 +#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x00000007 +#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF2_D4B5G_MSB 5 +#define PHY_ANALOG_TXRF2_D4B5G_LSB 3 +#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000038 +#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_TXRF2_OCAS2G_MSB 8 +#define PHY_ANALOG_TXRF2_OCAS2G_LSB 6 +#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0x000001c0 +#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_TXRF2_DCAS2G_MSB 11 +#define PHY_ANALOG_TXRF2_DCAS2G_LSB 9 +#define PHY_ANALOG_TXRF2_DCAS2G_MASK 0x00000e00 +#define PHY_ANALOG_TXRF2_DCAS2G_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_TXRF2_DCAS2G_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MSB 14 +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_LSB 12 +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MASK 0x00007000 +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF2_OB2G_QAM_MSB 17 +#define PHY_ANALOG_TXRF2_OB2G_QAM_LSB 15 +#define PHY_ANALOG_TXRF2_OB2G_QAM_MASK 0x00038000 +#define PHY_ANALOG_TXRF2_OB2G_QAM_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_TXRF2_OB2G_QAM_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_TXRF2_OB2G_PSK_MSB 20 +#define PHY_ANALOG_TXRF2_OB2G_PSK_LSB 18 +#define PHY_ANALOG_TXRF2_OB2G_PSK_MASK 0x001c0000 +#define PHY_ANALOG_TXRF2_OB2G_PSK_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_ANALOG_TXRF2_OB2G_PSK_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_ANALOG_TXRF2_OB2G_CCK_MSB 23 +#define PHY_ANALOG_TXRF2_OB2G_CCK_LSB 21 +#define PHY_ANALOG_TXRF2_OB2G_CCK_MASK 0x00e00000 +#define PHY_ANALOG_TXRF2_OB2G_CCK_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_TXRF2_OB2G_CCK_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_TXRF2_DB2G_MSB 26 +#define PHY_ANALOG_TXRF2_DB2G_LSB 24 +#define PHY_ANALOG_TXRF2_DB2G_MASK 0x07000000 +#define PHY_ANALOG_TXRF2_DB2G_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_TXRF2_DB2G_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 30 +#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 27 +#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x78000000 +#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 31 +#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 31 +#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x80000000 +#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF3 */ +#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048 +#define PHY_ANALOG_TXRF3_OFFSET 0x00000048 +#define PHY_ANALOG_TXRF3_FILTR2G_MSB 1 +#define PHY_ANALOG_TXRF3_FILTR2G_LSB 0 +#define PHY_ANALOG_TXRF3_FILTR2G_MASK 0x00000003 +#define PHY_ANALOG_TXRF3_FILTR2G_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF3_FILTR2G_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF3_PWDFB2_2G_MSB 2 +#define PHY_ANALOG_TXRF3_PWDFB2_2G_LSB 2 +#define PHY_ANALOG_TXRF3_PWDFB2_2G_MASK 0x00000004 +#define PHY_ANALOG_TXRF3_PWDFB2_2G_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TXRF3_PWDFB2_2G_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_TXRF3_PWDFB1_2G_MSB 3 +#define PHY_ANALOG_TXRF3_PWDFB1_2G_LSB 3 +#define PHY_ANALOG_TXRF3_PWDFB1_2G_MASK 0x00000008 +#define PHY_ANALOG_TXRF3_PWDFB1_2G_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF3_PWDFB1_2G_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TXRF3_PDFB2G_MSB 4 +#define PHY_ANALOG_TXRF3_PDFB2G_LSB 4 +#define PHY_ANALOG_TXRF3_PDFB2G_MASK 0x00000010 +#define PHY_ANALOG_TXRF3_PDFB2G_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TXRF3_PDFB2G_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TXRF3_RDIV5G_MSB 6 +#define PHY_ANALOG_TXRF3_RDIV5G_LSB 5 +#define PHY_ANALOG_TXRF3_RDIV5G_MASK 0x00000060 +#define PHY_ANALOG_TXRF3_RDIV5G_GET(x) (((x) & 0x00000060) >> 5) +#define PHY_ANALOG_TXRF3_RDIV5G_SET(x) (((x) << 5) & 0x00000060) +#define PHY_ANALOG_TXRF3_CAPDIV5G_MSB 9 +#define PHY_ANALOG_TXRF3_CAPDIV5G_LSB 7 +#define PHY_ANALOG_TXRF3_CAPDIV5G_MASK 0x00000380 +#define PHY_ANALOG_TXRF3_CAPDIV5G_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_TXRF3_CAPDIV5G_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_TXRF3_PDPREDIST5G_MSB 10 +#define PHY_ANALOG_TXRF3_PDPREDIST5G_LSB 10 +#define PHY_ANALOG_TXRF3_PDPREDIST5G_MASK 0x00000400 +#define PHY_ANALOG_TXRF3_PDPREDIST5G_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_TXRF3_PDPREDIST5G_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_TXRF3_RDIV2G_MSB 12 +#define PHY_ANALOG_TXRF3_RDIV2G_LSB 11 +#define PHY_ANALOG_TXRF3_RDIV2G_MASK 0x00001800 +#define PHY_ANALOG_TXRF3_RDIV2G_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_TXRF3_RDIV2G_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_TXRF3_PDPREDIST2G_MSB 13 +#define PHY_ANALOG_TXRF3_PDPREDIST2G_LSB 13 +#define PHY_ANALOG_TXRF3_PDPREDIST2G_MASK 0x00002000 +#define PHY_ANALOG_TXRF3_PDPREDIST2G_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF3_PDPREDIST2G_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF3_OCAS5G_MSB 16 +#define PHY_ANALOG_TXRF3_OCAS5G_LSB 14 +#define PHY_ANALOG_TXRF3_OCAS5G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF3_OCAS5G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF3_OCAS5G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF3_D2CAS5G_MSB 19 +#define PHY_ANALOG_TXRF3_D2CAS5G_LSB 17 +#define PHY_ANALOG_TXRF3_D2CAS5G_MASK 0x000e0000 +#define PHY_ANALOG_TXRF3_D2CAS5G_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF3_D2CAS5G_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF3_D3CAS5G_MSB 22 +#define PHY_ANALOG_TXRF3_D3CAS5G_LSB 20 +#define PHY_ANALOG_TXRF3_D3CAS5G_MASK 0x00700000 +#define PHY_ANALOG_TXRF3_D3CAS5G_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF3_D3CAS5G_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF3_D4CAS5G_MSB 25 +#define PHY_ANALOG_TXRF3_D4CAS5G_LSB 23 +#define PHY_ANALOG_TXRF3_D4CAS5G_MASK 0x03800000 +#define PHY_ANALOG_TXRF3_D4CAS5G_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF3_D4CAS5G_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF3_OB5G_MSB 28 +#define PHY_ANALOG_TXRF3_OB5G_LSB 26 +#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF3_D2B5G_MSB 31 +#define PHY_ANALOG_TXRF3_D2B5G_LSB 29 +#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF4 */ +#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c +#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MSB 1 +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_LSB 0 +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MASK 0x00000003 +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MSB 4 +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_LSB 2 +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MASK 0x0000001c +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MSB 7 +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_LSB 5 +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MASK 0x000000e0 +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MSB 10 +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_LSB 8 +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MASK 0x00000700 +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF4_COMP2G_QAM_MSB 13 +#define PHY_ANALOG_TXRF4_COMP2G_QAM_LSB 11 +#define PHY_ANALOG_TXRF4_COMP2G_QAM_MASK 0x00003800 +#define PHY_ANALOG_TXRF4_COMP2G_QAM_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_TXRF4_COMP2G_QAM_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 16 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 14 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x0001c000 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 19 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 17 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x000e0000 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 22 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 20 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x00700000 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 25 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 23 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x03800000 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 28 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 26 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x1c000000 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 31 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 29 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF5 */ +#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050 +#define PHY_ANALOG_TXRF5_OFFSET 0x00000050 +#define PHY_ANALOG_TXRF5_SPARE5_MSB 0 +#define PHY_ANALOG_TXRF5_SPARE5_LSB 0 +#define PHY_ANALOG_TXRF5_SPARE5_MASK 0x00000001 +#define PHY_ANALOG_TXRF5_SPARE5_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF5_SPARE5_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF5_PAL_LOCKED_MSB 1 +#define PHY_ANALOG_TXRF5_PAL_LOCKED_LSB 1 +#define PHY_ANALOG_TXRF5_PAL_LOCKED_MASK 0x00000002 +#define PHY_ANALOG_TXRF5_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF5_FBHI2G_MSB 2 +#define PHY_ANALOG_TXRF5_FBHI2G_LSB 2 +#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000004 +#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TXRF5_FBLO2G_MSB 3 +#define PHY_ANALOG_TXRF5_FBLO2G_LSB 3 +#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000008 +#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MSB 4 +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_LSB 4 +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MASK 0x00000010 +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TXRF5_ENPACAL2G_MSB 5 +#define PHY_ANALOG_TXRF5_ENPACAL2G_LSB 5 +#define PHY_ANALOG_TXRF5_ENPACAL2G_MASK 0x00000020 +#define PHY_ANALOG_TXRF5_ENPACAL2G_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TXRF5_ENPACAL2G_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TXRF5_OFFSET2G_MSB 12 +#define PHY_ANALOG_TXRF5_OFFSET2G_LSB 6 +#define PHY_ANALOG_TXRF5_OFFSET2G_MASK 0x00001fc0 +#define PHY_ANALOG_TXRF5_OFFSET2G_GET(x) (((x) & 0x00001fc0) >> 6) +#define PHY_ANALOG_TXRF5_OFFSET2G_SET(x) (((x) << 6) & 0x00001fc0) +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MSB 13 +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_LSB 13 +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MASK 0x00002000 +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF5_REFHI2G_MSB 16 +#define PHY_ANALOG_TXRF5_REFHI2G_LSB 14 +#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF5_REFLO2G_MSB 19 +#define PHY_ANALOG_TXRF5_REFLO2G_LSB 17 +#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000e0000 +#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF5_PALCLAMP2G_MSB 21 +#define PHY_ANALOG_TXRF5_PALCLAMP2G_LSB 20 +#define PHY_ANALOG_TXRF5_PALCLAMP2G_MASK 0x00300000 +#define PHY_ANALOG_TXRF5_PALCLAMP2G_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_ANALOG_TXRF5_PALCLAMP2G_SET(x) (((x) << 20) & 0x00300000) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 23 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 22 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00c00000 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 25 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 24 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x03000000 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 27 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 26 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x0c000000 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 29 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 28 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x30000000 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 28) & 0x30000000) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 31 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 30 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0xc0000000 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for TXRF6 */ +#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054 +#define PHY_ANALOG_TXRF6_OFFSET 0x00000054 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MSB 0 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_LSB 0 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MASK 0x00000001 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MSB 8 +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_LSB 1 +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MASK 0x000001fe +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_SET(x) (((x) << 1) & 0x000001fe) +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MSB 10 +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_LSB 9 +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MASK 0x00000600 +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_GET(x) (((x) & 0x00000600) >> 9) +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_SET(x) (((x) << 9) & 0x00000600) +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MSB 11 +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_LSB 11 +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MASK 0x00000800 +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 14 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 12 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00007000 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 15 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 15 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00008000 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MSB 19 +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_LSB 16 +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MASK 0x000f0000 +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 23 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 20 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x00f00000 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 26 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 24 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x07000000 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 30 +#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 27 +#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x78000000 +#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 31 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 31 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x80000000 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF7 */ +#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058 +#define PHY_ANALOG_TXRF7_OFFSET 0x00000058 +#define PHY_ANALOG_TXRF7_SPARE7_MSB 1 +#define PHY_ANALOG_TXRF7_SPARE7_LSB 0 +#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003 +#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF8 */ +#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c +#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c +#define PHY_ANALOG_TXRF8_SPARE8_MSB 1 +#define PHY_ANALOG_TXRF8_SPARE8_LSB 0 +#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003 +#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF9 */ +#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060 +#define PHY_ANALOG_TXRF9_OFFSET 0x00000060 +#define PHY_ANALOG_TXRF9_SPARE9_MSB 1 +#define PHY_ANALOG_TXRF9_SPARE9_LSB 0 +#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003 +#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF10 */ +#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064 +#define PHY_ANALOG_TXRF10_OFFSET 0x00000064 +#define PHY_ANALOG_TXRF10_SPARE10_MSB 2 +#define PHY_ANALOG_TXRF10_SPARE10_LSB 0 +#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00000007 +#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 3 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 3 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00000008 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 6 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 4 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x00000070 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 9 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 7 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x00000380 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 16 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 10 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x0001fc00 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 10) & 0x0001fc00) +#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 19 +#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 17 +#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x000e0000 +#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 20 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 20 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x00100000 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 21 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 21 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x00200000 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MSB 27 +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_LSB 22 +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MASK 0x0fc00000 +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_GET(x) (((x) & 0x0fc00000) >> 22) +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MSB 31 +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_LSB 28 +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MASK 0xf0000000 +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_GET(x) (((x) & 0xf0000000) >> 28) + +/* macros for TXRF11 */ +#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068 +#define PHY_ANALOG_TXRF11_OFFSET 0x00000068 +#define PHY_ANALOG_TXRF11_SPARE11_MSB 1 +#define PHY_ANALOG_TXRF11_SPARE11_LSB 0 +#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003 +#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 4 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 2 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x0000001c +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 7 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 5 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x000000e0 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 10 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 8 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00000700 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 13 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 11 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x00003800 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 16 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 14 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x0001c000 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MSB 19 +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_LSB 17 +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MASK 0x000e0000 +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF12 */ +#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c +#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c +#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7 +#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0 +#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff +#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 9 +#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8 +#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x00000300 +#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 13 +#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 10 +#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x00003c00 +#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 16 +#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 14 +#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 19 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 17 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x000e0000 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MSB 22 +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_LSB 20 +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MASK 0x00700000 +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 25 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 23 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x03800000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 28 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 26 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0x1c000000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MSB 31 +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_LSB 29 +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH1 */ +#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080 +#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15 +#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13 +#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000 +#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000 +#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000 +#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH2 */ +#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084 +#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f +#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MSB 15 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_LSB 12 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MASK 0x0000f000 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_LSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MASK 0x00010000 +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MSB 19 +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_LSB 18 +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MASK 0x000c0000 +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH3 */ +#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088 +#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH4 */ +#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c +#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MSB 7 +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_LSB 6 +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100 +#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12 +#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11 +#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800 +#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH5 */ +#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090 +#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1 +#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003 +#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000) +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MSB 31 +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_LSB 30 +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MASK 0xc0000000 +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for SYNTH6 */ +#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094 +#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8 +#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2 +#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc +#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2) +#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200 +#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400 +#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000 +#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000 +#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000 +#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000 +#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for SYNTH7 */ +#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098 +#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18 +#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2 +#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc +#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2) +#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc) +#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27 +#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19 +#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000 +#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19) +#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000) +#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000 +#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH8 */ +#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c +#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31 +#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27 +#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH9 */ +#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0 +#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31 +#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27 +#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH10 */ +#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4 +#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4 +#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 1 +#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0 +#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000003 +#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 4 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 2 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000001c +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH11 */ +#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8 +#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8 +#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4 +#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0 +#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f +#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7 +#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6 +#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH12 */ +#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac +#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac +#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 9 +#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0 +#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x000003ff +#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MSB 13 +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_LSB 10 +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MASK 0x00003c00 +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MSB 14 +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_LSB 14 +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MASK 0x00004000 +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MSB 16 +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_LSB 15 +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MASK 0x00018000 +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_GET(x) (((x) & 0x00018000) >> 15) +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_SET(x) (((x) << 15) & 0x00018000) +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MSB 17 +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_LSB 17 +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MASK 0x00020000 +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000 +#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22 +#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19 +#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000 +#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26 +#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23 +#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000 +#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30 +#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27 +#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000 +#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH13 */ +#define PHY_ANALOG_SYNTH13_ADDRESS 0x000000b0 +#define PHY_ANALOG_SYNTH13_OFFSET 0x000000b0 +#define PHY_ANALOG_SYNTH13_SPARE13A_MSB 0 +#define PHY_ANALOG_SYNTH13_SPARE13A_LSB 0 +#define PHY_ANALOG_SYNTH13_SPARE13A_MASK 0x00000001 +#define PHY_ANALOG_SYNTH13_SPARE13A_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH13_SPARE13A_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MSB 3 +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_LSB 1 +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MASK 0x0000000e +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MSB 7 +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_LSB 4 +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MSB 11 +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_LSB 8 +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MSB 16 +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_LSB 12 +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MSB 21 +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_LSB 17 +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MSB 26 +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_LSB 22 +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MSB 31 +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_LSB 27 +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH14 */ +#define PHY_ANALOG_SYNTH14_ADDRESS 0x000000b4 +#define PHY_ANALOG_SYNTH14_OFFSET 0x000000b4 +#define PHY_ANALOG_SYNTH14_SPARE14A_MSB 1 +#define PHY_ANALOG_SYNTH14_SPARE14A_LSB 0 +#define PHY_ANALOG_SYNTH14_SPARE14A_MASK 0x00000003 +#define PHY_ANALOG_SYNTH14_SPARE14A_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH14_SPARE14A_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MSB 3 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_LSB 2 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MASK 0x0000000c +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MSB 5 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_LSB 4 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MASK 0x00000030 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MSB 7 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_LSB 6 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MSB 9 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_LSB 8 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MASK 0x00000300 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MSB 10 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_LSB 10 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MASK 0x00000400 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MSB 11 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_LSB 11 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MASK 0x00000800 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MSB 12 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_LSB 12 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MASK 0x00001000 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MSB 13 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_LSB 13 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MASK 0x00002000 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MSB 16 +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_LSB 14 +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MASK 0x0001c000 +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MSB 19 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_LSB 17 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MASK 0x000e0000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MSB 22 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_LSB 20 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MASK 0x00700000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MSB 25 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_LSB 23 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MASK 0x03800000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MSB 28 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_LSB 26 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MASK 0x1c000000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MSB 31 +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_LSB 29 +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MASK 0xe0000000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS1 */ +#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0 +#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0 +#define PHY_ANALOG_BIAS1_SPARE1_MSB 6 +#define PHY_ANALOG_BIAS1_SPARE1_LSB 0 +#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f +#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31 +#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25 +#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000 +#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25) +#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000) + +/* macros for BIAS2 */ +#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4 +#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4 +#define PHY_ANALOG_BIAS2_SPARE2_MSB 4 +#define PHY_ANALOG_BIAS2_SPARE2_LSB 0 +#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f +#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MSB 7 +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_LSB 5 +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MASK 0x000000e0 +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MSB 19 +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_LSB 17 +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MASK 0x000e0000 +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS3 */ +#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8 +#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8 +#define PHY_ANALOG_BIAS3_SPARE3_MSB 1 +#define PHY_ANALOG_BIAS3_SPARE3_LSB 0 +#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003 +#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MSB 4 +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_LSB 2 +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MASK 0x0000001c +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MSB 13 +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_LSB 11 +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MASK 0x00003800 +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS4 */ +#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc +#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc +#define PHY_ANALOG_BIAS4_SPARE4_MSB 10 +#define PHY_ANALOG_BIAS4_SPARE4_LSB 0 +#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x000007ff +#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MSB 13 +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_LSB 11 +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MASK 0x00003800 +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MSB 22 +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_LSB 20 +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MASK 0x00700000 +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX1 */ +#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100 +#define PHY_ANALOG_RXTX1_OFFSET 0x00000100 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002 +#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c +#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18 +#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15 +#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000 +#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30 +#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27 +#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000 +#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000 +#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXTX2 */ +#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104 +#define PHY_ANALOG_RXTX2_OFFSET 0x00000104 +#define PHY_ANALOG_RXTX2_BMODE_MSB 0 +#define PHY_ANALOG_RXTX2_BMODE_LSB 0 +#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001 +#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002 +#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004 +#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX2_BW_ST_MSB 5 +#define PHY_ANALOG_RXTX2_BW_ST_LSB 4 +#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030 +#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX2_TXON_MSB 7 +#define PHY_ANALOG_RXTX2_TXON_LSB 7 +#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080 +#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX2_PAON_MSB 9 +#define PHY_ANALOG_RXTX2_PAON_LSB 9 +#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200 +#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX2_RXON_MSB 11 +#define PHY_ANALOG_RXTX2_RXON_LSB 11 +#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800 +#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000 +#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RXTX2_AGCON_MSB 13 +#define PHY_ANALOG_RXTX2_AGCON_LSB 13 +#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000 +#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000 +#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX2_TXMOD_MSB 17 +#define PHY_ANALOG_RXTX2_TXMOD_LSB 15 +#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000 +#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25 +#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24 +#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000 +#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28 +#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26 +#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000 +#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31 +#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29 +#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000 +#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX3 */ +#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108 +#define PHY_ANALOG_RXTX3_OFFSET 0x00000108 +#define PHY_ANALOG_RXTX3_SPARE3_MSB 2 +#define PHY_ANALOG_RXTX3_SPARE3_LSB 0 +#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007 +#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_RXTX3_SPURON_MSB 3 +#define PHY_ANALOG_RXTX3_SPURON_LSB 3 +#define PHY_ANALOG_RXTX3_SPURON_MASK 0x00000008 +#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MSB 4 +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_LSB 4 +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MASK 0x00000010 +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 5 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 5 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000020 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040 +#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX3_DACPWD_MSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_LSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080 +#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200 +#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800) +#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000 +#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000 +#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_RXTX3_CALFC_MSB 22 +#define PHY_ANALOG_RXTX3_CALFC_LSB 22 +#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000 +#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000 +#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_RXTX3_CALTX_MSB 24 +#define PHY_ANALOG_RXTX3_CALTX_LSB 24 +#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000 +#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000 +#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_RXTX3_CALPA_MSB 28 +#define PHY_ANALOG_RXTX3_CALPA_LSB 28 +#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000 +#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXTX3_TURBOADC_MSB 30 +#define PHY_ANALOG_RXTX3_TURBOADC_LSB 30 +#define PHY_ANALOG_RXTX3_TURBOADC_MASK 0x40000000 +#define PHY_ANALOG_RXTX3_TURBOADC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXTX3_TURBOADC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MSB 31 +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_LSB 31 +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MASK 0x80000000 +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB1 */ +#define PHY_ANALOG_BB1_ADDRESS 0x00000140 +#define PHY_ANALOG_BB1_OFFSET 0x00000140 +#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001 +#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002 +#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004 +#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010 +#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100 +#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200 +#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400 +#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800 +#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000 +#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_BB1_CMSEL_MSB 15 +#define PHY_ANALOG_BB1_CMSEL_LSB 13 +#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000 +#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BB1_ATBSEL_MSB 17 +#define PHY_ANALOG_BB1_ATBSEL_LSB 16 +#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000 +#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000) +#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000 +#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31 +#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30 +#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000 +#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB2 */ +#define PHY_ANALOG_BB2_ADDRESS 0x00000144 +#define PHY_ANALOG_BB2_OFFSET 0x00000144 +#define PHY_ANALOG_BB2_SPARE_MSB 3 +#define PHY_ANALOG_BB2_SPARE_LSB 0 +#define PHY_ANALOG_BB2_SPARE_MASK 0x0000000f +#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MSB 7 +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_LSB 4 +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MASK 0x000000f0 +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_BB2_SEL_TEST_MSB 9 +#define PHY_ANALOG_BB2_SEL_TEST_LSB 8 +#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000300 +#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_BB2_RCFILTER_CAP_MSB 14 +#define PHY_ANALOG_BB2_RCFILTER_CAP_LSB 10 +#define PHY_ANALOG_BB2_RCFILTER_CAP_MASK 0x00007c00 +#define PHY_ANALOG_BB2_RCFILTER_CAP_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_ANALOG_BB2_RCFILTER_CAP_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_LSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MASK 0x00008000 +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_BB2_FNOTCH_MSB 19 +#define PHY_ANALOG_BB2_FNOTCH_LSB 16 +#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000 +#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_BB2_FILTERFC_MSB 25 +#define PHY_ANALOG_BB2_FILTERFC_LSB 21 +#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000 +#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB3 */ +#define PHY_ANALOG_BB3_ADDRESS 0x00000148 +#define PHY_ANALOG_BB3_OFFSET 0x00000148 +#define PHY_ANALOG_BB3_SPARE_MSB 15 +#define PHY_ANALOG_BB3_SPARE_LSB 0 +#define PHY_ANALOG_BB3_SPARE_MASK 0x0000ffff +#define PHY_ANALOG_BB3_SPARE_GET(x) (((x) & 0x0000ffff) >> 0) +#define PHY_ANALOG_BB3_SPARE_SET(x) (((x) << 0) & 0x0000ffff) +#define PHY_ANALOG_BB3_FILTERFC_MSB 20 +#define PHY_ANALOG_BB3_FILTERFC_LSB 16 +#define PHY_ANALOG_BB3_FILTERFC_MASK 0x001f0000 +#define PHY_ANALOG_BB3_FILTERFC_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MSB 25 +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_LSB 21 +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MASK 0x03e00000 +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_ANALOG_BB3_OFSTCORRI2VI_MSB 30 +#define PHY_ANALOG_BB3_OFSTCORRI2VI_LSB 26 +#define PHY_ANALOG_BB3_OFSTCORRI2VI_MASK 0x7c000000 +#define PHY_ANALOG_BB3_OFSTCORRI2VI_GET(x) (((x) & 0x7c000000) >> 26) +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MSB 31 +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_LSB 31 +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MASK 0x80000000 +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for PLLCLKMODA */ +#define PHY_ANALOG_PLLCLKMODA_ADDRESS 0x00000280 +#define PHY_ANALOG_PLLCLKMODA_OFFSET 0x00000280 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MSB 0 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_LSB 0 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MASK 0x00000001 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MSB 1 +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_LSB 1 +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MASK 0x00000002 +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MSB 16 +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_LSB 2 +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MASK 0x0001fffc +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_GET(x) (((x) & 0x0001fffc) >> 2) +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_SET(x) (((x) << 2) & 0x0001fffc) +#define PHY_ANALOG_PLLCLKMODA_REFDIV_MSB 20 +#define PHY_ANALOG_PLLCLKMODA_REFDIV_LSB 17 +#define PHY_ANALOG_PLLCLKMODA_REFDIV_MASK 0x001e0000 +#define PHY_ANALOG_PLLCLKMODA_REFDIV_GET(x) (((x) & 0x001e0000) >> 17) +#define PHY_ANALOG_PLLCLKMODA_REFDIV_SET(x) (((x) << 17) & 0x001e0000) +#define PHY_ANALOG_PLLCLKMODA_DIV_MSB 30 +#define PHY_ANALOG_PLLCLKMODA_DIV_LSB 21 +#define PHY_ANALOG_PLLCLKMODA_DIV_MASK 0x7fe00000 +#define PHY_ANALOG_PLLCLKMODA_DIV_GET(x) (((x) & 0x7fe00000) >> 21) +#define PHY_ANALOG_PLLCLKMODA_DIV_SET(x) (((x) << 21) & 0x7fe00000) +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MSB 31 +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_LSB 31 +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MASK 0x80000000 +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for PLLCLKMODA2 */ +#define PHY_ANALOG_PLLCLKMODA2_ADDRESS 0x00000284 +#define PHY_ANALOG_PLLCLKMODA2_OFFSET 0x00000284 +#define PHY_ANALOG_PLLCLKMODA2_SPARE_MSB 3 +#define PHY_ANALOG_PLLCLKMODA2_SPARE_LSB 0 +#define PHY_ANALOG_PLLCLKMODA2_SPARE_MASK 0x0000000f +#define PHY_ANALOG_PLLCLKMODA2_SPARE_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_PLLCLKMODA2_SPARE_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MSB 4 +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_LSB 4 +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MASK 0x00000010 +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MSB 5 +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_LSB 5 +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MASK 0x00000020 +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MSB 6 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_LSB 6 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MASK 0x00000040 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MSB 8 +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_LSB 7 +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MASK 0x00000180 +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_GET(x) (((x) & 0x00000180) >> 7) +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_SET(x) (((x) << 7) & 0x00000180) +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MSB 12 +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_LSB 9 +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MASK 0x00001e00 +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_GET(x) (((x) & 0x00001e00) >> 9) +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_SET(x) (((x) << 9) & 0x00001e00) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MSB 13 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_LSB 13 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MASK 0x00002000 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MSB 14 +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_LSB 14 +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MASK 0x00004000 +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MSB 15 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_LSB 15 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MASK 0x00008000 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MSB 17 +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_LSB 16 +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MASK 0x00030000 +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MSB 18 +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_LSB 18 +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MASK 0x00040000 +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MSB 19 +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_LSB 19 +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MASK 0x00080000 +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MSB 20 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_LSB 20 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MASK 0x00100000 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MSB 21 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_LSB 21 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MASK 0x00200000 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MSB 23 +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_LSB 22 +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MASK 0x00c00000 +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MSB 26 +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_LSB 24 +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MASK 0x07000000 +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MSB 31 +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_LSB 27 +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MASK 0xf8000000 +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for TOP */ +#define PHY_ANALOG_TOP_ADDRESS 0x00000288 +#define PHY_ANALOG_TOP_OFFSET 0x00000288 +#define PHY_ANALOG_TOP_SPARE_MSB 2 +#define PHY_ANALOG_TOP_SPARE_LSB 0 +#define PHY_ANALOG_TOP_SPARE_MASK 0x00000007 +#define PHY_ANALOG_TOP_SPARE_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TOP_SPARE_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TOP_PWDBIAS_MSB 3 +#define PHY_ANALOG_TOP_PWDBIAS_LSB 3 +#define PHY_ANALOG_TOP_PWDBIAS_MASK 0x00000008 +#define PHY_ANALOG_TOP_PWDBIAS_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TOP_PWDBIAS_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TOP_FLIP_XPABIAS_MSB 4 +#define PHY_ANALOG_TOP_FLIP_XPABIAS_LSB 4 +#define PHY_ANALOG_TOP_FLIP_XPABIAS_MASK 0x00000010 +#define PHY_ANALOG_TOP_FLIP_XPABIAS_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TOP_FLIP_XPABIAS_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TOP_XPAON2_MSB 5 +#define PHY_ANALOG_TOP_XPAON2_LSB 5 +#define PHY_ANALOG_TOP_XPAON2_MASK 0x00000020 +#define PHY_ANALOG_TOP_XPAON2_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TOP_XPAON2_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TOP_XPAON5_MSB 6 +#define PHY_ANALOG_TOP_XPAON5_LSB 6 +#define PHY_ANALOG_TOP_XPAON5_MASK 0x00000040 +#define PHY_ANALOG_TOP_XPAON5_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_TOP_XPAON5_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_TOP_XPASHORT2GND_MSB 7 +#define PHY_ANALOG_TOP_XPASHORT2GND_LSB 7 +#define PHY_ANALOG_TOP_XPASHORT2GND_MASK 0x00000080 +#define PHY_ANALOG_TOP_XPASHORT2GND_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_TOP_XPASHORT2GND_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_TOP_XPABIASLVL_MSB 11 +#define PHY_ANALOG_TOP_XPABIASLVL_LSB 8 +#define PHY_ANALOG_TOP_XPABIASLVL_MASK 0x00000f00 +#define PHY_ANALOG_TOP_XPABIASLVL_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TOP_XPABIASLVL_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TOP_XPABIAS_EN_MSB 12 +#define PHY_ANALOG_TOP_XPABIAS_EN_LSB 12 +#define PHY_ANALOG_TOP_XPABIAS_EN_MASK 0x00001000 +#define PHY_ANALOG_TOP_XPABIAS_EN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_TOP_XPABIAS_EN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_TOP_ATBSELECT_MSB 13 +#define PHY_ANALOG_TOP_ATBSELECT_LSB 13 +#define PHY_ANALOG_TOP_ATBSELECT_MASK 0x00002000 +#define PHY_ANALOG_TOP_ATBSELECT_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TOP_ATBSELECT_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TOP_LOCAL_XPA_MSB 14 +#define PHY_ANALOG_TOP_LOCAL_XPA_LSB 14 +#define PHY_ANALOG_TOP_LOCAL_XPA_MASK 0x00004000 +#define PHY_ANALOG_TOP_LOCAL_XPA_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_TOP_LOCAL_XPA_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MSB 15 +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_LSB 15 +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MASK 0x00008000 +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_TOP_TEST_PADQ_EN_MSB 16 +#define PHY_ANALOG_TOP_TEST_PADQ_EN_LSB 16 +#define PHY_ANALOG_TOP_TEST_PADQ_EN_MASK 0x00010000 +#define PHY_ANALOG_TOP_TEST_PADQ_EN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_TOP_TEST_PADQ_EN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_TOP_TEST_PADI_EN_MSB 17 +#define PHY_ANALOG_TOP_TEST_PADI_EN_LSB 17 +#define PHY_ANALOG_TOP_TEST_PADI_EN_MASK 0x00020000 +#define PHY_ANALOG_TOP_TEST_PADI_EN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_TOP_TEST_PADI_EN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_TOP_TESTIQ_RSEL_MSB 18 +#define PHY_ANALOG_TOP_TESTIQ_RSEL_LSB 18 +#define PHY_ANALOG_TOP_TESTIQ_RSEL_MASK 0x00040000 +#define PHY_ANALOG_TOP_TESTIQ_RSEL_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_TOP_TESTIQ_RSEL_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MSB 19 +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_LSB 19 +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MASK 0x00080000 +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_TOP_PAD2GND_MSB 20 +#define PHY_ANALOG_TOP_PAD2GND_LSB 20 +#define PHY_ANALOG_TOP_PAD2GND_MASK 0x00100000 +#define PHY_ANALOG_TOP_PAD2GND_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TOP_PAD2GND_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TOP_INTH2PAD_MSB 21 +#define PHY_ANALOG_TOP_INTH2PAD_LSB 21 +#define PHY_ANALOG_TOP_INTH2PAD_MASK 0x00200000 +#define PHY_ANALOG_TOP_INTH2PAD_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TOP_INTH2PAD_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TOP_INTH2GND_MSB 22 +#define PHY_ANALOG_TOP_INTH2GND_LSB 22 +#define PHY_ANALOG_TOP_INTH2GND_MASK 0x00400000 +#define PHY_ANALOG_TOP_INTH2GND_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TOP_INTH2GND_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TOP_INT2PAD_MSB 23 +#define PHY_ANALOG_TOP_INT2PAD_LSB 23 +#define PHY_ANALOG_TOP_INT2PAD_MASK 0x00800000 +#define PHY_ANALOG_TOP_INT2PAD_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TOP_INT2PAD_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TOP_INT2GND_MSB 24 +#define PHY_ANALOG_TOP_INT2GND_LSB 24 +#define PHY_ANALOG_TOP_INT2GND_MASK 0x01000000 +#define PHY_ANALOG_TOP_INT2GND_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_TOP_INT2GND_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_TOP_PWDPALCLK_MSB 25 +#define PHY_ANALOG_TOP_PWDPALCLK_LSB 25 +#define PHY_ANALOG_TOP_PWDPALCLK_MASK 0x02000000 +#define PHY_ANALOG_TOP_PWDPALCLK_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_TOP_PWDPALCLK_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_TOP_INV_CLK320_ADC_MSB 26 +#define PHY_ANALOG_TOP_INV_CLK320_ADC_LSB 26 +#define PHY_ANALOG_TOP_INV_CLK320_ADC_MASK 0x04000000 +#define PHY_ANALOG_TOP_INV_CLK320_ADC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_TOP_INV_CLK320_ADC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_TOP_FLIP_REFCLK40_MSB 27 +#define PHY_ANALOG_TOP_FLIP_REFCLK40_LSB 27 +#define PHY_ANALOG_TOP_FLIP_REFCLK40_MASK 0x08000000 +#define PHY_ANALOG_TOP_FLIP_REFCLK40_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_TOP_FLIP_REFCLK40_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MSB 28 +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_LSB 28 +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MASK 0x10000000 +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MSB 29 +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_LSB 29 +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MASK 0x20000000 +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_TOP_CLK_SEL_MSB 31 +#define PHY_ANALOG_TOP_CLK_SEL_LSB 30 +#define PHY_ANALOG_TOP_CLK_SEL_MASK 0xc0000000 +#define PHY_ANALOG_TOP_CLK_SEL_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_TOP_CLK_SEL_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for THERM */ +#define PHY_ANALOG_THERM_ADDRESS 0x0000028c +#define PHY_ANALOG_THERM_OFFSET 0x0000028c +#define PHY_ANALOG_THERM_LOREG_LVL_MSB 2 +#define PHY_ANALOG_THERM_LOREG_LVL_LSB 0 +#define PHY_ANALOG_THERM_LOREG_LVL_MASK 0x00000007 +#define PHY_ANALOG_THERM_LOREG_LVL_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_THERM_LOREG_LVL_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_THERM_RFREG_LVL_MSB 5 +#define PHY_ANALOG_THERM_RFREG_LVL_LSB 3 +#define PHY_ANALOG_THERM_RFREG_LVL_MASK 0x00000038 +#define PHY_ANALOG_THERM_RFREG_LVL_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_THERM_RFREG_LVL_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_THERM_SAR_ADC_DONE_MSB 6 +#define PHY_ANALOG_THERM_SAR_ADC_DONE_LSB 6 +#define PHY_ANALOG_THERM_SAR_ADC_DONE_MASK 0x00000040 +#define PHY_ANALOG_THERM_SAR_ADC_DONE_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_THERM_SAR_ADC_OUT_MSB 14 +#define PHY_ANALOG_THERM_SAR_ADC_OUT_LSB 7 +#define PHY_ANALOG_THERM_SAR_ADC_OUT_MASK 0x00007f80 +#define PHY_ANALOG_THERM_SAR_ADC_OUT_GET(x) (((x) & 0x00007f80) >> 7) +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MSB 22 +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_LSB 15 +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MASK 0x007f8000 +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_GET(x) (((x) & 0x007f8000) >> 15) +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_SET(x) (((x) << 15) & 0x007f8000) +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MSB 23 +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_LSB 23 +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MASK 0x00800000 +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MSB 24 +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_LSB 24 +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MASK 0x01000000 +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_THERM_THERMSEL_MSB 26 +#define PHY_ANALOG_THERM_THERMSEL_LSB 25 +#define PHY_ANALOG_THERM_THERMSEL_MASK 0x06000000 +#define PHY_ANALOG_THERM_THERMSEL_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_ANALOG_THERM_THERMSEL_SET(x) (((x) << 25) & 0x06000000) +#define PHY_ANALOG_THERM_SAR_SLOW_EN_MSB 27 +#define PHY_ANALOG_THERM_SAR_SLOW_EN_LSB 27 +#define PHY_ANALOG_THERM_SAR_SLOW_EN_MASK 0x08000000 +#define PHY_ANALOG_THERM_SAR_SLOW_EN_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_THERM_SAR_SLOW_EN_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_THERM_THERMSTART_MSB 28 +#define PHY_ANALOG_THERM_THERMSTART_LSB 28 +#define PHY_ANALOG_THERM_THERMSTART_MASK 0x10000000 +#define PHY_ANALOG_THERM_THERMSTART_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_THERM_THERMSTART_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MSB 29 +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_LSB 29 +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MASK 0x20000000 +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_THERM_THERMON_MSB 30 +#define PHY_ANALOG_THERM_THERMON_LSB 30 +#define PHY_ANALOG_THERM_THERMON_MASK 0x40000000 +#define PHY_ANALOG_THERM_THERMON_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_THERM_THERMON_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_THERM_LOCAL_THERM_MSB 31 +#define PHY_ANALOG_THERM_LOCAL_THERM_LSB 31 +#define PHY_ANALOG_THERM_LOCAL_THERM_MASK 0x80000000 +#define PHY_ANALOG_THERM_LOCAL_THERM_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_THERM_LOCAL_THERM_SET(x) (((x) << 31) & 0x80000000) + +/* macros for XTAL */ +#define PHY_ANALOG_XTAL_ADDRESS 0x00000290 +#define PHY_ANALOG_XTAL_OFFSET 0x00000290 +#define PHY_ANALOG_XTAL_SPARE_MSB 5 +#define PHY_ANALOG_XTAL_SPARE_LSB 0 +#define PHY_ANALOG_XTAL_SPARE_MASK 0x0000003f +#define PHY_ANALOG_XTAL_SPARE_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_XTAL_SPARE_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MSB 6 +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_LSB 6 +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MASK 0x00000040 +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_XTAL_LOCALBIAS2X_MSB 7 +#define PHY_ANALOG_XTAL_LOCALBIAS2X_LSB 7 +#define PHY_ANALOG_XTAL_LOCALBIAS2X_MASK 0x00000080 +#define PHY_ANALOG_XTAL_LOCALBIAS2X_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_XTAL_LOCALBIAS2X_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_XTAL_LOCAL_XTAL_MSB 8 +#define PHY_ANALOG_XTAL_LOCAL_XTAL_LSB 8 +#define PHY_ANALOG_XTAL_LOCAL_XTAL_MASK 0x00000100 +#define PHY_ANALOG_XTAL_LOCAL_XTAL_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_XTAL_LOCAL_XTAL_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MSB 9 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_LSB 9 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MASK 0x00000200 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_XTAL_XTAL_OSCON_MSB 10 +#define PHY_ANALOG_XTAL_XTAL_OSCON_LSB 10 +#define PHY_ANALOG_XTAL_XTAL_OSCON_MASK 0x00000400 +#define PHY_ANALOG_XTAL_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_XTAL_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MSB 11 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_LSB 11 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MASK 0x00000800 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MSB 12 +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_LSB 12 +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MASK 0x00001000 +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MSB 13 +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_LSB 13 +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MASK 0x00002000 +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MSB 15 +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_LSB 14 +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MASK 0x0000c000 +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MSB 22 +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_LSB 16 +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MASK 0x007f0000 +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MSB 29 +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_LSB 23 +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MASK 0x3f800000 +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MSB 30 +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_LSB 30 +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MASK 0x40000000 +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_XTAL_TCXODET_MSB 31 +#define PHY_ANALOG_XTAL_TCXODET_LSB 31 +#define PHY_ANALOG_XTAL_TCXODET_MASK 0x80000000 +#define PHY_ANALOG_XTAL_TCXODET_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for rbist_cntrl */ +#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000) + +/* macros for tx_dc_offset */ +#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000) + +/* macros for tx_tonegen0 */ +#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_tonegen1 */ +#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_lftonegen0 */ +#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_linear_ramp_i */ +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_linear_ramp_q */ +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_prbs_mag */ +#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for tx_prbs_seed_i */ +#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for tx_prbs_seed_q */ +#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for cmac_dc_cancel */ +#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for cmac_dc_offset */ +#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_corr */ +#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00) + +/* macros for cmac_power */ +#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_cross_corr */ +#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_i2q2 */ +#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_power_hpf */ +#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0) + +/* macros for rxdac_set1 */ +#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000) + +/* macros for rxdac_set2 */ +#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000) + +/* macros for rxdac_long_shift */ +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00) + +/* macros for cmac_results_i */ +#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for cmac_results_q */ +#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for PMU1 */ +#define PHY_ANALOG_PMU1_ADDRESS 0x00000740 +#define PHY_ANALOG_PMU1_OFFSET 0x00000740 +#define PHY_ANALOG_PMU1_SPARE_MSB 10 +#define PHY_ANALOG_PMU1_SPARE_LSB 0 +#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff +#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000 +#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000 +#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000 +#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for PMU2 */ +#define PHY_ANALOG_PMU2_ADDRESS 0x00000744 +#define PHY_ANALOG_PMU2_OFFSET 0x00000744 +#define PHY_ANALOG_PMU2_SPARE_MSB 7 +#define PHY_ANALOG_PMU2_SPARE_LSB 0 +#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff +#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000) +#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27 +#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25 +#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000 +#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000 +#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_athr_wlan_reg_reg_s { + volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */ + volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */ + volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */ + volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */ + volatile char pad__0[0x30]; /* 0x10 - 0x40 */ + volatile unsigned int TXRF1; /* 0x40 - 0x44 */ + volatile unsigned int TXRF2; /* 0x44 - 0x48 */ + volatile unsigned int TXRF3; /* 0x48 - 0x4c */ + volatile unsigned int TXRF4; /* 0x4c - 0x50 */ + volatile unsigned int TXRF5; /* 0x50 - 0x54 */ + volatile unsigned int TXRF6; /* 0x54 - 0x58 */ + volatile unsigned int TXRF7; /* 0x58 - 0x5c */ + volatile unsigned int TXRF8; /* 0x5c - 0x60 */ + volatile unsigned int TXRF9; /* 0x60 - 0x64 */ + volatile unsigned int TXRF10; /* 0x64 - 0x68 */ + volatile unsigned int TXRF11; /* 0x68 - 0x6c */ + volatile unsigned int TXRF12; /* 0x6c - 0x70 */ + volatile char pad__1[0x10]; /* 0x70 - 0x80 */ + volatile unsigned int SYNTH1; /* 0x80 - 0x84 */ + volatile unsigned int SYNTH2; /* 0x84 - 0x88 */ + volatile unsigned int SYNTH3; /* 0x88 - 0x8c */ + volatile unsigned int SYNTH4; /* 0x8c - 0x90 */ + volatile unsigned int SYNTH5; /* 0x90 - 0x94 */ + volatile unsigned int SYNTH6; /* 0x94 - 0x98 */ + volatile unsigned int SYNTH7; /* 0x98 - 0x9c */ + volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */ + volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */ + volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */ + volatile unsigned int SYNTH11; /* 0xa8 - 0xac */ + volatile unsigned int SYNTH12; /* 0xac - 0xb0 */ + volatile unsigned int SYNTH13; /* 0xb0 - 0xb4 */ + volatile unsigned int SYNTH14; /* 0xb4 - 0xb8 */ + volatile char pad__2[0x8]; /* 0xb8 - 0xc0 */ + volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */ + volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */ + volatile unsigned int BIAS3; /* 0xc8 - 0xcc */ + volatile unsigned int BIAS4; /* 0xcc - 0xd0 */ + volatile char pad__3[0x30]; /* 0xd0 - 0x100 */ + volatile unsigned int RXTX1; /* 0x100 - 0x104 */ + volatile unsigned int RXTX2; /* 0x104 - 0x108 */ + volatile unsigned int RXTX3; /* 0x108 - 0x10c */ + volatile char pad__4[0x34]; /* 0x10c - 0x140 */ + volatile unsigned int BB1; /* 0x140 - 0x144 */ + volatile unsigned int BB2; /* 0x144 - 0x148 */ + volatile unsigned int BB3; /* 0x148 - 0x14c */ + volatile char pad__5[0x134]; /* 0x14c - 0x280 */ + volatile unsigned int PLLCLKMODA; /* 0x280 - 0x284 */ + volatile unsigned int PLLCLKMODA2; /* 0x284 - 0x288 */ + volatile unsigned int TOP; /* 0x288 - 0x28c */ + volatile unsigned int THERM; /* 0x28c - 0x290 */ + volatile unsigned int XTAL; /* 0x290 - 0x294 */ + volatile char pad__6[0xec]; /* 0x294 - 0x380 */ + volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */ + volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */ + volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */ + volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */ + volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */ + volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */ + volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */ + volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */ + volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */ + volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */ + volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */ + volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */ + volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */ + volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */ + volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */ + volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */ + volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */ + volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */ + volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */ + volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */ + volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */ + volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */ + volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */ + volatile unsigned int PMU1; /* 0x740 - 0x744 */ + volatile unsigned int PMU2; /* 0x744 - 0x748 */ +} analog_intf_athr_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h new file mode 100644 index 000000000000..01b9eb54a43c --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h @@ -0,0 +1,37 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "analog_intf_athr_wlan_reg.h" + + +#ifndef BT_HEADERS + + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h new file mode 100644 index 000000000000..609eb9841f59 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h @@ -0,0 +1,40 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _APB_ATHR_WLAN_MAP_H_ +#define _APB_ATHR_WLAN_MAP_H_ + +#define WLAN_RTC_BASE_ADDRESS 0x00004000 +#define WLAN_VMC_BASE_ADDRESS 0x00008000 +#define WLAN_UART_BASE_ADDRESS 0x0000c000 +#define WLAN_DBG_UART_BASE_ADDRESS 0x0000d000 +#define WLAN_UMBOX_BASE_ADDRESS 0x0000e000 +#define WLAN_SI_BASE_ADDRESS 0x00010000 +#define WLAN_GPIO_BASE_ADDRESS 0x00014000 +#define WLAN_MBOX_BASE_ADDRESS 0x00018000 +#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define WLAN_MAC_BASE_ADDRESS 0x00020000 +#define WLAN_RDMA_BASE_ADDRESS 0x00030100 +#define EFUSE_BASE_ADDRESS 0x00031000 + +#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h new file mode 100644 index 000000000000..e4d2d62f0bb4 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h @@ -0,0 +1,48 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "apb_athr_wlan_map.h" + + +#ifndef BT_HEADERS + +#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS +#define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS +#define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS +#define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS +#define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS +#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS +#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS +#define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS +#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS +#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS +#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h new file mode 100644 index 000000000000..271192953162 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h @@ -0,0 +1,7076 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + +/* Copyright (C) 2009 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ + + +#ifndef _BB_LC_REG_REG_H_ +#define _BB_LC_REG_REG_H_ + + +/* macros for BB_test_controls */ +#define PHY_BB_TEST_CONTROLS_ADDRESS 0x00009800 +#define PHY_BB_TEST_CONTROLS_OFFSET 0x00009800 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MSB 3 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB 0 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK 0x0000000f +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MSB 4 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB 4 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK 0x00000010 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MSB 6 +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB 5 +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK 0x00000060 +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_GET(x) (((x) & 0x00000060) >> 5) +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_SET(x) (((x) << 5) & 0x00000060) +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MSB 9 +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB 8 +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK 0x00000300 +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MSB 10 +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB 10 +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK 0x00000400 +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MSB 13 +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB 13 +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK 0x00002000 +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MSB 15 +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB 15 +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK 0x00008000 +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MSB 17 +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB 17 +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK 0x00020000 +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MSB 18 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB 18 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK 0x00040000 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MSB 22 +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB 19 +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK 0x00780000 +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_SET(x) (((x) << 19) & 0x00780000) +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MSB 23 +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB 23 +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK 0x00800000 +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MSB 24 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB 24 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK 0x01000000 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MSB 28 +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB 28 +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK 0x10000000 +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MSB 31 +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB 30 +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK 0xc0000000 +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB_gen_controls */ +#define PHY_BB_GEN_CONTROLS_ADDRESS 0x00009804 +#define PHY_BB_GEN_CONTROLS_OFFSET 0x00009804 +#define PHY_BB_GEN_CONTROLS_TURBO_MSB 0 +#define PHY_BB_GEN_CONTROLS_TURBO_LSB 0 +#define PHY_BB_GEN_CONTROLS_TURBO_MASK 0x00000001 +#define PHY_BB_GEN_CONTROLS_TURBO_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_GEN_CONTROLS_TURBO_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MSB 1 +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_LSB 1 +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MASK 0x00000002 +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_MSB 2 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_LSB 2 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_MASK 0x00000004 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MSB 3 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_LSB 3 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MASK 0x00000008 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MSB 4 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_LSB 4 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MASK 0x00000010 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MSB 5 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_LSB 5 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MASK 0x00000020 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MSB 6 +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_LSB 6 +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MASK 0x00000040 +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MSB 7 +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB 7 +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK 0x00000080 +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MSB 8 +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_LSB 8 +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MASK 0x00000100 +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MSB 9 +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_LSB 9 +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MASK 0x00000200 +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MSB 10 +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB 10 +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK 0x00000400 +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MSB 11 +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_LSB 11 +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MASK 0x00000800 +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_SET(x) (((x) << 11) & 0x00000800) + +/* macros for BB_test_controls_status */ +#define PHY_BB_TEST_CONTROLS_STATUS_ADDRESS 0x00009808 +#define PHY_BB_TEST_CONTROLS_STATUS_OFFSET 0x00009808 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MSB 0 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB 0 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK 0x00000001 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MSB 1 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB 1 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK 0x00000002 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MSB 4 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB 2 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK 0x0000001c +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MSB 6 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB 5 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK 0x00000060 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_GET(x) (((x) & 0x00000060) >> 5) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_SET(x) (((x) << 5) & 0x00000060) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MSB 7 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB 7 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK 0x00000080 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MSB 8 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB 8 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK 0x00000100 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MSB 9 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB 9 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK 0x00000200 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MSB 13 +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB 10 +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK 0x00003c00 +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MSB 14 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB 14 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK 0x00004000 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MSB 15 +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB 15 +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK 0x00008000 +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MSB 18 +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB 16 +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK 0x00070000 +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MSB 19 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB 19 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK 0x00080000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MSB 23 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB 23 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK 0x00800000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MSB 27 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB 27 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK 0x08000000 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MSB 28 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB 28 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK 0x10000000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MSB 30 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB 29 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK 0x60000000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_SET(x) (((x) << 29) & 0x60000000) + +/* macros for BB_timing_controls_1 */ +#define PHY_BB_TIMING_CONTROLS_1_ADDRESS 0x0000980c +#define PHY_BB_TIMING_CONTROLS_1_OFFSET 0x0000980c +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MSB 6 +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB 0 +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK 0x0000007f +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MSB 12 +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB 7 +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK 0x00001f80 +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_GET(x) (((x) & 0x00001f80) >> 7) +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_SET(x) (((x) << 7) & 0x00001f80) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MSB 16 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_LSB 13 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MASK 0x0001e000 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_GET(x) (((x) & 0x0001e000) >> 13) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_SET(x) (((x) << 13) & 0x0001e000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MSB 17 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_LSB 17 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MASK 0x00020000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MSB 19 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB 18 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK 0x000c0000 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MSB 21 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB 20 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK 0x00300000 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_SET(x) (((x) << 20) & 0x00300000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MSB 22 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB 22 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK 0x00400000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MSB 23 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB 23 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK 0x00800000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MSB 24 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB 24 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK 0x01000000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MSB 26 +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB 25 +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK 0x06000000 +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_SET(x) (((x) << 25) & 0x06000000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MSB 27 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB 27 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK 0x08000000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MSB 28 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB 28 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK 0x10000000 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MSB 30 +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB 29 +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK 0x60000000 +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_SET(x) (((x) << 29) & 0x60000000) +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MSB 31 +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB 31 +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_controls_2 */ +#define PHY_BB_TIMING_CONTROLS_2_ADDRESS 0x00009810 +#define PHY_BB_TIMING_CONTROLS_2_OFFSET 0x00009810 +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MSB 11 +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB 0 +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK 0x00000fff +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MSB 12 +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB 12 +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK 0x00001000 +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MSB 13 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB 13 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK 0x00002000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MSB 14 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_LSB 14 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MASK 0x00004000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MSB 15 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB 15 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK 0x00008000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MSB 22 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB 16 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK 0x007f0000 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MSB 26 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB 24 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK 0x07000000 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_SET(x) (((x) << 24) & 0x07000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MSB 27 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB 27 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK 0x08000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MSB 28 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB 28 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK 0x10000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MSB 29 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB 29 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK 0x20000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MSB 30 +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB 30 +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MSB 31 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB 31 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_controls_3 */ +#define PHY_BB_TIMING_CONTROLS_3_ADDRESS 0x00009814 +#define PHY_BB_TIMING_CONTROLS_3_OFFSET 0x00009814 +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MSB 7 +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB 0 +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK 0x000000ff +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MSB 8 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB 8 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK 0x00000100 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MSB 9 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB 9 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK 0x00000200 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MSB 10 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB 10 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK 0x00000400 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MSB 11 +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB 11 +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK 0x00000800 +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MSB 12 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB 12 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK 0x00001000 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MSB 16 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB 13 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK 0x0001e000 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_GET(x) (((x) & 0x0001e000) >> 13) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_SET(x) (((x) << 13) & 0x0001e000) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MSB 31 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB 17 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK 0xfffe0000 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_GET(x) (((x) & 0xfffe0000) >> 17) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_SET(x) (((x) << 17) & 0xfffe0000) + +/* macros for BB_D2_chip_id */ +#define PHY_BB_D2_CHIP_ID_ADDRESS 0x00009818 +#define PHY_BB_D2_CHIP_ID_OFFSET 0x00009818 +#define PHY_BB_D2_CHIP_ID_OLD_ID_MSB 7 +#define PHY_BB_D2_CHIP_ID_OLD_ID_LSB 0 +#define PHY_BB_D2_CHIP_ID_OLD_ID_MASK 0x000000ff +#define PHY_BB_D2_CHIP_ID_OLD_ID_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_D2_CHIP_ID_ID_MSB 31 +#define PHY_BB_D2_CHIP_ID_ID_LSB 8 +#define PHY_BB_D2_CHIP_ID_ID_MASK 0xffffff00 +#define PHY_BB_D2_CHIP_ID_ID_GET(x) (((x) & 0xffffff00) >> 8) + +/* macros for BB_active */ +#define PHY_BB_ACTIVE_ADDRESS 0x0000981c +#define PHY_BB_ACTIVE_OFFSET 0x0000981c +#define PHY_BB_ACTIVE_CF_ACTIVE_MSB 0 +#define PHY_BB_ACTIVE_CF_ACTIVE_LSB 0 +#define PHY_BB_ACTIVE_CF_ACTIVE_MASK 0x00000001 +#define PHY_BB_ACTIVE_CF_ACTIVE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_ACTIVE_CF_ACTIVE_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_tx_timing_1 */ +#define PHY_BB_TX_TIMING_1_ADDRESS 0x00009820 +#define PHY_BB_TX_TIMING_1_OFFSET 0x00009820 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MSB 7 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB 0 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK 0x000000ff +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MSB 15 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB 8 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK 0x0000ff00 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MSB 23 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB 16 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK 0x00ff0000 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MSB 31 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB 24 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK 0xff000000 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_tx_timing_2 */ +#define PHY_BB_TX_TIMING_2_ADDRESS 0x00009824 +#define PHY_BB_TX_TIMING_2_OFFSET 0x00009824 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MSB 7 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB 0 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK 0x000000ff +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MSB 15 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB 8 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK 0x0000ff00 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MSB 23 +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB 16 +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK 0x00ff0000 +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MSB 31 +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB 24 +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK 0xff000000 +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_tx_timing_3 */ +#define PHY_BB_TX_TIMING_3_ADDRESS 0x00009828 +#define PHY_BB_TX_TIMING_3_OFFSET 0x00009828 +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MSB 7 +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB 0 +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK 0x000000ff +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MSB 15 +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB 8 +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK 0x0000ff00 +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MSB 23 +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB 16 +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK 0x00ff0000 +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MSB 31 +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB 24 +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK 0xff000000 +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_addac_parallel_control */ +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ADDRESS 0x0000982c +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFFSET 0x0000982c +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MSB 12 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB 12 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK 0x00001000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MSB 13 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB 13 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK 0x00002000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MSB 15 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB 15 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK 0x00008000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MSB 28 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB 28 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK 0x10000000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MSB 29 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB 29 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK 0x20000000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MSB 31 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB 31 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK 0x80000000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_xpa_timing_control */ +#define PHY_BB_XPA_TIMING_CONTROL_ADDRESS 0x00009834 +#define PHY_BB_XPA_TIMING_CONTROL_OFFSET 0x00009834 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MSB 7 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB 0 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK 0x000000ff +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MSB 15 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB 8 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK 0x0000ff00 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MSB 23 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB 16 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK 0x00ff0000 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MSB 31 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB 24 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK 0xff000000 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_misc_pa_control */ +#define PHY_BB_MISC_PA_CONTROL_ADDRESS 0x00009838 +#define PHY_BB_MISC_PA_CONTROL_OFFSET 0x00009838 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MSB 0 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB 0 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK 0x00000001 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MSB 1 +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB 1 +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK 0x00000002 +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MSB 2 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB 2 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK 0x00000004 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MSB 3 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB 3 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK 0x00000008 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_SET(x) (((x) << 3) & 0x00000008) + +/* macros for BB_tstdac_constant */ +#define PHY_BB_TSTDAC_CONSTANT_ADDRESS 0x0000983c +#define PHY_BB_TSTDAC_CONSTANT_OFFSET 0x0000983c +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MSB 10 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB 0 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK 0x000007ff +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MSB 21 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB 11 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK 0x003ff800 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_GET(x) (((x) & 0x003ff800) >> 11) +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_SET(x) (((x) << 11) & 0x003ff800) + +/* macros for BB_find_signal_low */ +#define PHY_BB_FIND_SIGNAL_LOW_ADDRESS 0x00009840 +#define PHY_BB_FIND_SIGNAL_LOW_OFFSET 0x00009840 +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MSB 5 +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB 0 +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK 0x0000003f +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MSB 11 +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB 6 +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK 0x00000fc0 +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MSB 19 +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB 12 +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK 0x000ff000 +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_GET(x) (((x) & 0x000ff000) >> 12) +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_SET(x) (((x) << 12) & 0x000ff000) +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MSB 23 +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB 20 +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK 0x00f00000 +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MSB 30 +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB 24 +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK 0x7f000000 +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for BB_settling_time */ +#define PHY_BB_SETTLING_TIME_ADDRESS 0x00009844 +#define PHY_BB_SETTLING_TIME_OFFSET 0x00009844 +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MSB 6 +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_LSB 0 +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MASK 0x0000007f +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MSB 13 +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_LSB 7 +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MASK 0x00003f80 +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MSB 19 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_LSB 14 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MASK 0x000fc000 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MSB 25 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_LSB 20 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MASK 0x03f00000 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MSB 29 +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_LSB 26 +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MASK 0x3c000000 +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_GET(x) (((x) & 0x3c000000) >> 26) +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_SET(x) (((x) << 26) & 0x3c000000) + +/* macros for BB_gain_force_max_gains_b0 */ +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ADDRESS 0x00009848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_OFFSET 0x00009848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MSB 13 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_LSB 7 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MASK 0x00003f80 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MSB 20 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_LSB 14 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MASK 0x001fc000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_SET(x) (((x) << 14) & 0x001fc000) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MSB 21 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_LSB 21 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MASK 0x00200000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MSB 31 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_LSB 31 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MASK 0x80000000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_gains_min_offsets_b0 */ +#define PHY_BB_GAINS_MIN_OFFSETS_B0_ADDRESS 0x0000984c +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSET 0x0000984c +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MSB 6 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_LSB 0 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MASK 0x0000007f +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MSB 11 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_LSB 7 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MASK 0x00000f80 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_GET(x) (((x) & 0x00000f80) >> 7) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_SET(x) (((x) << 7) & 0x00000f80) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MSB 16 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_LSB 12 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MASK 0x0001f000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MSB 24 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_LSB 17 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MASK 0x01fe0000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_GET(x) (((x) & 0x01fe0000) >> 17) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_SET(x) (((x) << 17) & 0x01fe0000) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_LSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MASK 0x02000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_LSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MASK 0x04000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_SET(x) (((x) << 26) & 0x04000000) + +/* macros for BB_desired_sigsize */ +#define PHY_BB_DESIRED_SIGSIZE_ADDRESS 0x00009850 +#define PHY_BB_DESIRED_SIGSIZE_OFFSET 0x00009850 +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MSB 7 +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_LSB 0 +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MASK 0x000000ff +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MSB 27 +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_LSB 20 +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MASK 0x0ff00000 +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_GET(x) (((x) & 0x0ff00000) >> 20) +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_SET(x) (((x) << 20) & 0x0ff00000) +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MSB 29 +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_LSB 28 +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MASK 0x30000000 +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_SET(x) (((x) << 28) & 0x30000000) +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MSB 30 +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_LSB 30 +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MASK 0x40000000 +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MSB 31 +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_LSB 31 +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MASK 0x80000000 +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_control_3a */ +#define PHY_BB_TIMING_CONTROL_3A_ADDRESS 0x00009854 +#define PHY_BB_TIMING_CONTROL_3A_OFFSET 0x00009854 +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MSB 6 +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_LSB 0 +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MASK 0x0000007f +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_SET(x) (((x) << 0) & 0x0000007f) + +/* macros for BB_find_signal */ +#define PHY_BB_FIND_SIGNAL_ADDRESS 0x00009858 +#define PHY_BB_FIND_SIGNAL_OFFSET 0x00009858 +#define PHY_BB_FIND_SIGNAL_RELSTEP_MSB 5 +#define PHY_BB_FIND_SIGNAL_RELSTEP_LSB 0 +#define PHY_BB_FIND_SIGNAL_RELSTEP_MASK 0x0000003f +#define PHY_BB_FIND_SIGNAL_RELSTEP_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_FIND_SIGNAL_RELSTEP_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_FIND_SIGNAL_RELPWR_MSB 11 +#define PHY_BB_FIND_SIGNAL_RELPWR_LSB 6 +#define PHY_BB_FIND_SIGNAL_RELPWR_MASK 0x00000fc0 +#define PHY_BB_FIND_SIGNAL_RELPWR_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_FIND_SIGNAL_RELPWR_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_FIND_SIGNAL_FIRSTEP_MSB 17 +#define PHY_BB_FIND_SIGNAL_FIRSTEP_LSB 12 +#define PHY_BB_FIND_SIGNAL_FIRSTEP_MASK 0x0003f000 +#define PHY_BB_FIND_SIGNAL_FIRSTEP_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_FIND_SIGNAL_FIRSTEP_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_FIND_SIGNAL_FIRPWR_MSB 25 +#define PHY_BB_FIND_SIGNAL_FIRPWR_LSB 18 +#define PHY_BB_FIND_SIGNAL_FIRPWR_MASK 0x03fc0000 +#define PHY_BB_FIND_SIGNAL_FIRPWR_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_BB_FIND_SIGNAL_FIRPWR_SET(x) (((x) << 18) & 0x03fc0000) +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MSB 31 +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_LSB 26 +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MASK 0xfc000000 +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for BB_agc */ +#define PHY_BB_AGC_ADDRESS 0x0000985c +#define PHY_BB_AGC_OFFSET 0x0000985c +#define PHY_BB_AGC_COARSEPWR_CONST_MSB 6 +#define PHY_BB_AGC_COARSEPWR_CONST_LSB 0 +#define PHY_BB_AGC_COARSEPWR_CONST_MASK 0x0000007f +#define PHY_BB_AGC_COARSEPWR_CONST_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_AGC_COARSEPWR_CONST_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_AGC_COARSE_LOW_MSB 14 +#define PHY_BB_AGC_COARSE_LOW_LSB 7 +#define PHY_BB_AGC_COARSE_LOW_MASK 0x00007f80 +#define PHY_BB_AGC_COARSE_LOW_GET(x) (((x) & 0x00007f80) >> 7) +#define PHY_BB_AGC_COARSE_LOW_SET(x) (((x) << 7) & 0x00007f80) +#define PHY_BB_AGC_COARSE_HIGH_MSB 21 +#define PHY_BB_AGC_COARSE_HIGH_LSB 15 +#define PHY_BB_AGC_COARSE_HIGH_MASK 0x003f8000 +#define PHY_BB_AGC_COARSE_HIGH_GET(x) (((x) & 0x003f8000) >> 15) +#define PHY_BB_AGC_COARSE_HIGH_SET(x) (((x) << 15) & 0x003f8000) +#define PHY_BB_AGC_QUICK_DROP_MSB 29 +#define PHY_BB_AGC_QUICK_DROP_LSB 22 +#define PHY_BB_AGC_QUICK_DROP_MASK 0x3fc00000 +#define PHY_BB_AGC_QUICK_DROP_GET(x) (((x) & 0x3fc00000) >> 22) +#define PHY_BB_AGC_QUICK_DROP_SET(x) (((x) << 22) & 0x3fc00000) +#define PHY_BB_AGC_RSSI_OUT_SELECT_MSB 31 +#define PHY_BB_AGC_RSSI_OUT_SELECT_LSB 30 +#define PHY_BB_AGC_RSSI_OUT_SELECT_MASK 0xc0000000 +#define PHY_BB_AGC_RSSI_OUT_SELECT_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_BB_AGC_RSSI_OUT_SELECT_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB_agc_control */ +#define PHY_BB_AGC_CONTROL_ADDRESS 0x00009860 +#define PHY_BB_AGC_CONTROL_OFFSET 0x00009860 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MSB 0 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB 0 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK 0x00000001 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MSB 1 +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB 1 +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK 0x00000002 +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MSB 5 +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB 3 +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK 0x00000038 +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_SET(x) (((x) << 3) & 0x00000038) +#define PHY_BB_AGC_CONTROL_YCOK_MAX_MSB 9 +#define PHY_BB_AGC_CONTROL_YCOK_MAX_LSB 6 +#define PHY_BB_AGC_CONTROL_YCOK_MAX_MASK 0x000003c0 +#define PHY_BB_AGC_CONTROL_YCOK_MAX_GET(x) (((x) & 0x000003c0) >> 6) +#define PHY_BB_AGC_CONTROL_YCOK_MAX_SET(x) (((x) << 6) & 0x000003c0) +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MSB 10 +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB 10 +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK 0x00000400 +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MSB 11 +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB 11 +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK 0x00000800 +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MSB 12 +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_LSB 12 +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MASK 0x00001000 +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MSB 13 +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_LSB 13 +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MASK 0x00002000 +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MSB 15 +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB 15 +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK 0x00008000 +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MSB 16 +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB 16 +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK 0x00010000 +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MSB 17 +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB 17 +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK 0x00020000 +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MSB 18 +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB 18 +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK 0x00040000 +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MSB 19 +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB 19 +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK 0x00080000 +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MSB 20 +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB 20 +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK 0x00100000 +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_SET(x) (((x) << 20) & 0x00100000) + +/* macros for BB_cca_b0 */ +#define PHY_BB_CCA_B0_ADDRESS 0x00009864 +#define PHY_BB_CCA_B0_OFFSET 0x00009864 +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MSB 8 +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_LSB 0 +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MASK 0x000001ff +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MSB 11 +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_LSB 9 +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MASK 0x00000e00 +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_BB_CCA_B0_CF_THRESH62_MSB 19 +#define PHY_BB_CCA_B0_CF_THRESH62_LSB 12 +#define PHY_BB_CCA_B0_CF_THRESH62_MASK 0x000ff000 +#define PHY_BB_CCA_B0_CF_THRESH62_GET(x) (((x) & 0x000ff000) >> 12) +#define PHY_BB_CCA_B0_CF_THRESH62_SET(x) (((x) << 12) & 0x000ff000) +#define PHY_BB_CCA_B0_MINCCAPWR_0_MSB 28 +#define PHY_BB_CCA_B0_MINCCAPWR_0_LSB 20 +#define PHY_BB_CCA_B0_MINCCAPWR_0_MASK 0x1ff00000 +#define PHY_BB_CCA_B0_MINCCAPWR_0_GET(x) (((x) & 0x1ff00000) >> 20) + +/* macros for BB_sfcorr */ +#define PHY_BB_SFCORR_ADDRESS 0x00009868 +#define PHY_BB_SFCORR_OFFSET 0x00009868 +#define PHY_BB_SFCORR_M2COUNT_THR_MSB 4 +#define PHY_BB_SFCORR_M2COUNT_THR_LSB 0 +#define PHY_BB_SFCORR_M2COUNT_THR_MASK 0x0000001f +#define PHY_BB_SFCORR_M2COUNT_THR_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_SFCORR_M2COUNT_THR_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_SFCORR_ADCSAT_THRESH_MSB 10 +#define PHY_BB_SFCORR_ADCSAT_THRESH_LSB 5 +#define PHY_BB_SFCORR_ADCSAT_THRESH_MASK 0x000007e0 +#define PHY_BB_SFCORR_ADCSAT_THRESH_GET(x) (((x) & 0x000007e0) >> 5) +#define PHY_BB_SFCORR_ADCSAT_THRESH_SET(x) (((x) << 5) & 0x000007e0) +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MSB 16 +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_LSB 11 +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MASK 0x0001f800 +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_SET(x) (((x) << 11) & 0x0001f800) +#define PHY_BB_SFCORR_M1_THRES_MSB 23 +#define PHY_BB_SFCORR_M1_THRES_LSB 17 +#define PHY_BB_SFCORR_M1_THRES_MASK 0x00fe0000 +#define PHY_BB_SFCORR_M1_THRES_GET(x) (((x) & 0x00fe0000) >> 17) +#define PHY_BB_SFCORR_M1_THRES_SET(x) (((x) << 17) & 0x00fe0000) +#define PHY_BB_SFCORR_M2_THRES_MSB 30 +#define PHY_BB_SFCORR_M2_THRES_LSB 24 +#define PHY_BB_SFCORR_M2_THRES_MASK 0x7f000000 +#define PHY_BB_SFCORR_M2_THRES_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_SFCORR_M2_THRES_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for BB_self_corr_low */ +#define PHY_BB_SELF_CORR_LOW_ADDRESS 0x0000986c +#define PHY_BB_SELF_CORR_LOW_OFFSET 0x0000986c +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MSB 0 +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB 0 +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK 0x00000001 +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MSB 7 +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB 1 +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK 0x000000fe +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MSB 13 +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB 8 +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK 0x00003f00 +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MSB 20 +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB 14 +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK 0x001fc000 +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_SET(x) (((x) << 14) & 0x001fc000) +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MSB 27 +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB 21 +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK 0x0fe00000 +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_SET(x) (((x) << 21) & 0x0fe00000) + +/* macros for BB_synth_control */ +#define PHY_BB_SYNTH_CONTROL_ADDRESS 0x00009874 +#define PHY_BB_SYNTH_CONTROL_OFFSET 0x00009874 +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MSB 16 +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB 0 +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK 0x0001ffff +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_GET(x) (((x) & 0x0001ffff) >> 0) +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_SET(x) (((x) << 0) & 0x0001ffff) +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MSB 25 +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB 17 +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK 0x03fe0000 +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_GET(x) (((x) & 0x03fe0000) >> 17) +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_SET(x) (((x) << 17) & 0x03fe0000) +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MSB 27 +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB 26 +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK 0x0c000000 +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MSB 28 +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB 28 +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK 0x10000000 +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_SYNTH_CONTROL_RFBMODE_MSB 29 +#define PHY_BB_SYNTH_CONTROL_RFBMODE_LSB 29 +#define PHY_BB_SYNTH_CONTROL_RFBMODE_MASK 0x20000000 +#define PHY_BB_SYNTH_CONTROL_RFBMODE_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_SYNTH_CONTROL_RFBMODE_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MSB 30 +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB 30 +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK 0x40000000 +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_addac_clk_select */ +#define PHY_BB_ADDAC_CLK_SELECT_ADDRESS 0x00009878 +#define PHY_BB_ADDAC_CLK_SELECT_OFFSET 0x00009878 +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MSB 3 +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB 2 +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK 0x0000000c +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MSB 5 +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_LSB 4 +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MASK 0x00000030 +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_SET(x) (((x) << 4) & 0x00000030) + +/* macros for BB_pll_cntl */ +#define PHY_BB_PLL_CNTL_ADDRESS 0x0000987c +#define PHY_BB_PLL_CNTL_OFFSET 0x0000987c +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MSB 9 +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB 0 +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK 0x000003ff +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MSB 13 +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB 10 +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK 0x00003c00 +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MSB 15 +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB 14 +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK 0x0000c000 +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MSB 16 +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB 16 +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK 0x00010000 +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MSB 27 +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB 17 +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK 0x0ffe0000 +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_GET(x) (((x) & 0x0ffe0000) >> 17) +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_SET(x) (((x) << 17) & 0x0ffe0000) + +/* macros for BB_vit_spur_mask_A */ +#define PHY_BB_VIT_SPUR_MASK_A_ADDRESS 0x00009900 +#define PHY_BB_VIT_SPUR_MASK_A_OFFSET 0x00009900 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MSB 9 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_LSB 0 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MASK 0x000003ff +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MSB 16 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_LSB 10 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MASK 0x0001fc00 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_SET(x) (((x) << 10) & 0x0001fc00) + +/* macros for BB_vit_spur_mask_B */ +#define PHY_BB_VIT_SPUR_MASK_B_ADDRESS 0x00009904 +#define PHY_BB_VIT_SPUR_MASK_B_OFFSET 0x00009904 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MSB 9 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_LSB 0 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MASK 0x000003ff +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MSB 16 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_LSB 10 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MASK 0x0001fc00 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_SET(x) (((x) << 10) & 0x0001fc00) + +/* macros for BB_pilot_spur_mask */ +#define PHY_BB_PILOT_SPUR_MASK_ADDRESS 0x00009908 +#define PHY_BB_PILOT_SPUR_MASK_OFFSET 0x00009908 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MSB 4 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_LSB 0 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MASK 0x0000001f +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MSB 11 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_LSB 5 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MASK 0x00000fe0 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MSB 16 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_LSB 12 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MASK 0x0001f000 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MSB 23 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_LSB 17 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MASK 0x00fe0000 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000) + +/* macros for BB_chan_spur_mask */ +#define PHY_BB_CHAN_SPUR_MASK_ADDRESS 0x0000990c +#define PHY_BB_CHAN_SPUR_MASK_OFFSET 0x0000990c +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MSB 4 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_LSB 0 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MASK 0x0000001f +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MSB 11 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_LSB 5 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MASK 0x00000fe0 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MSB 16 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_LSB 12 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MASK 0x0001f000 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MSB 23 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_LSB 17 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MASK 0x00fe0000 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000) + +/* macros for BB_spectral_scan */ +#define PHY_BB_SPECTRAL_SCAN_ADDRESS 0x00009910 +#define PHY_BB_SPECTRAL_SCAN_OFFSET 0x00009910 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MSB 0 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB 0 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK 0x00000001 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MSB 1 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB 1 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK 0x00000002 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MSB 2 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_LSB 2 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MASK 0x00000004 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MSB 3 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_LSB 3 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MASK 0x00000008 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MSB 7 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_LSB 4 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MASK 0x000000f0 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MSB 15 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB 8 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK 0x0000ff00 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MSB 27 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB 16 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK 0x0fff0000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_GET(x) (((x) & 0x0fff0000) >> 16) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_SET(x) (((x) << 16) & 0x0fff0000) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MSB 28 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_LSB 28 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MASK 0x10000000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MSB 29 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB 29 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK 0x20000000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MSB 30 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_LSB 30 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MASK 0x40000000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_analog_power_on_time */ +#define PHY_BB_ANALOG_POWER_ON_TIME_ADDRESS 0x00009914 +#define PHY_BB_ANALOG_POWER_ON_TIME_OFFSET 0x00009914 +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MSB 13 +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB 0 +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK 0x00003fff +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_SET(x) (((x) << 0) & 0x00003fff) + +/* macros for BB_search_start_delay */ +#define PHY_BB_SEARCH_START_DELAY_ADDRESS 0x00009918 +#define PHY_BB_SEARCH_START_DELAY_OFFSET 0x00009918 +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MSB 11 +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_LSB 0 +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MASK 0x00000fff +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MSB 12 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_LSB 12 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MASK 0x00001000 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MSB 13 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_LSB 13 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MASK 0x00002000 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_SET(x) (((x) << 13) & 0x00002000) + +/* macros for BB_max_rx_length */ +#define PHY_BB_MAX_RX_LENGTH_ADDRESS 0x0000991c +#define PHY_BB_MAX_RX_LENGTH_OFFSET 0x0000991c +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MSB 11 +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB 0 +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK 0x00000fff +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MSB 29 +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB 12 +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK 0x3ffff000 +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_GET(x) (((x) & 0x3ffff000) >> 12) +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_SET(x) (((x) << 12) & 0x3ffff000) + +/* macros for BB_timing_control_4 */ +#define PHY_BB_TIMING_CONTROL_4_ADDRESS 0x00009920 +#define PHY_BB_TIMING_CONTROL_4_OFFSET 0x00009920 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MSB 15 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB 12 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK 0x0000f000 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MSB 16 +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB 16 +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK 0x00010000 +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MSB 20 +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB 17 +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK 0x001e0000 +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_GET(x) (((x) & 0x001e0000) >> 17) +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_SET(x) (((x) << 17) & 0x001e0000) +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MSB 27 +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB 21 +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK 0x0fe00000 +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_SET(x) (((x) << 21) & 0x0fe00000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MSB 28 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB 28 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK 0x10000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MSB 29 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB 29 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK 0x20000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MSB 30 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_LSB 30 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MSB 31 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB 31 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_control_5 */ +#define PHY_BB_TIMING_CONTROL_5_ADDRESS 0x00009924 +#define PHY_BB_TIMING_CONTROL_5_OFFSET 0x00009924 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MSB 0 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB 0 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK 0x00000001 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MSB 7 +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB 1 +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK 0x000000fe +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MSB 15 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB 15 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK 0x00008000 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MSB 22 +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB 16 +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK 0x007f0000 +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MSB 29 +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB 23 +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK 0x3f800000 +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MSB 30 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_LSB 30 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MSB 31 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_LSB 31 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_phyonly_warm_reset */ +#define PHY_BB_PHYONLY_WARM_RESET_ADDRESS 0x00009928 +#define PHY_BB_PHYONLY_WARM_RESET_OFFSET 0x00009928 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MSB 0 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_LSB 0 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MASK 0x00000001 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_phyonly_control */ +#define PHY_BB_PHYONLY_CONTROL_ADDRESS 0x0000992c +#define PHY_BB_PHYONLY_CONTROL_OFFSET 0x0000992c +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MSB 0 +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB 0 +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK 0x00000001 +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MSB 1 +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB 1 +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK 0x00000002 +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MSB 2 +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_LSB 2 +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MASK 0x00000004 +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MSB 3 +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB 3 +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK 0x00000008 +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MSB 4 +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB 4 +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK 0x00000010 +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MSB 5 +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB 5 +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK 0x00000020 +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MSB 6 +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB 6 +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK 0x00000040 +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MSB 7 +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB 7 +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK 0x00000080 +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_SET(x) (((x) << 7) & 0x00000080) + +/* macros for BB_powertx_rate1 */ +#define PHY_BB_POWERTX_RATE1_ADDRESS 0x00009934 +#define PHY_BB_POWERTX_RATE1_OFFSET 0x00009934 +#define PHY_BB_POWERTX_RATE1_POWERTX_0_MSB 5 +#define PHY_BB_POWERTX_RATE1_POWERTX_0_LSB 0 +#define PHY_BB_POWERTX_RATE1_POWERTX_0_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE1_POWERTX_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE1_POWERTX_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE1_POWERTX_1_MSB 13 +#define PHY_BB_POWERTX_RATE1_POWERTX_1_LSB 8 +#define PHY_BB_POWERTX_RATE1_POWERTX_1_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE1_POWERTX_1_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE1_POWERTX_1_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE1_POWERTX_2_MSB 21 +#define PHY_BB_POWERTX_RATE1_POWERTX_2_LSB 16 +#define PHY_BB_POWERTX_RATE1_POWERTX_2_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE1_POWERTX_2_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE1_POWERTX_2_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE1_POWERTX_3_MSB 29 +#define PHY_BB_POWERTX_RATE1_POWERTX_3_LSB 24 +#define PHY_BB_POWERTX_RATE1_POWERTX_3_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE1_POWERTX_3_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE1_POWERTX_3_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate2 */ +#define PHY_BB_POWERTX_RATE2_ADDRESS 0x00009938 +#define PHY_BB_POWERTX_RATE2_OFFSET 0x00009938 +#define PHY_BB_POWERTX_RATE2_POWERTX_4_MSB 5 +#define PHY_BB_POWERTX_RATE2_POWERTX_4_LSB 0 +#define PHY_BB_POWERTX_RATE2_POWERTX_4_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE2_POWERTX_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE2_POWERTX_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE2_POWERTX_5_MSB 13 +#define PHY_BB_POWERTX_RATE2_POWERTX_5_LSB 8 +#define PHY_BB_POWERTX_RATE2_POWERTX_5_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE2_POWERTX_5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE2_POWERTX_5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE2_POWERTX_6_MSB 21 +#define PHY_BB_POWERTX_RATE2_POWERTX_6_LSB 16 +#define PHY_BB_POWERTX_RATE2_POWERTX_6_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE2_POWERTX_6_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE2_POWERTX_6_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE2_POWERTX_7_MSB 29 +#define PHY_BB_POWERTX_RATE2_POWERTX_7_LSB 24 +#define PHY_BB_POWERTX_RATE2_POWERTX_7_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE2_POWERTX_7_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE2_POWERTX_7_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_max */ +#define PHY_BB_POWERTX_MAX_ADDRESS 0x0000993c +#define PHY_BB_POWERTX_MAX_OFFSET 0x0000993c +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MSB 6 +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_LSB 6 +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MASK 0x00000040 +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_SET(x) (((x) << 6) & 0x00000040) + +/* macros for BB_extension_radar */ +#define PHY_BB_EXTENSION_RADAR_ADDRESS 0x00009940 +#define PHY_BB_EXTENSION_RADAR_OFFSET 0x00009940 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MSB 13 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_LSB 8 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MASK 0x00003f00 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MSB 14 +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_LSB 14 +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MASK 0x00004000 +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MSB 22 +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_LSB 15 +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MASK 0x007f8000 +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_GET(x) (((x) & 0x007f8000) >> 15) +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_SET(x) (((x) << 15) & 0x007f8000) +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MSB 30 +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB 23 +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK 0x7f800000 +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_GET(x) (((x) & 0x7f800000) >> 23) +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_SET(x) (((x) << 23) & 0x7f800000) +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MSB 31 +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_LSB 31 +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MASK 0x80000000 +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_frame_control */ +#define PHY_BB_FRAME_CONTROL_ADDRESS 0x00009944 +#define PHY_BB_FRAME_CONTROL_OFFSET 0x00009944 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MSB 1 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB 0 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK 0x00000003 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_SET(x) (((x) << 0) & 0x00000003) +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MSB 2 +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_LSB 2 +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MASK 0x00000004 +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MSB 5 +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB 3 +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK 0x00000038 +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_SET(x) (((x) << 3) & 0x00000038) +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MSB 7 +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB 6 +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK 0x000000c0 +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MSB 15 +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB 8 +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK 0x0000ff00 +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MSB 16 +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB 16 +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK 0x00010000 +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MSB 17 +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB 17 +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK 0x00020000 +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MSB 18 +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB 18 +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK 0x00040000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MSB 19 +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_LSB 19 +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MASK 0x00080000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MSB 20 +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB 20 +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK 0x00100000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MSB 21 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB 21 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK 0x00200000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MSB 22 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB 22 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK 0x00400000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MSB 23 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB 23 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK 0x00800000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MSB 24 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB 24 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK 0x01000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MSB 25 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB 25 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK 0x02000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MSB 26 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB 26 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK 0x04000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MSB 27 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB 27 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK 0x08000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MSB 28 +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_LSB 28 +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MASK 0x10000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MSB 29 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB 29 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK 0x20000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MSB 30 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB 30 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK 0x40000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MSB 31 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB 31 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK 0x80000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_control_6 */ +#define PHY_BB_TIMING_CONTROL_6_ADDRESS 0x00009948 +#define PHY_BB_TIMING_CONTROL_6_OFFSET 0x00009948 +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MSB 7 +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB 0 +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK 0x000000ff +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MSB 14 +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB 8 +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK 0x00007f00 +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_GET(x) (((x) & 0x00007f00) >> 8) +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_SET(x) (((x) << 8) & 0x00007f00) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MSB 20 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB 15 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK 0x001f8000 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_GET(x) (((x) & 0x001f8000) >> 15) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_SET(x) (((x) << 15) & 0x001f8000) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MSB 27 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB 21 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK 0x0fe00000 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_SET(x) (((x) << 21) & 0x0fe00000) +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MSB 31 +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_LSB 28 +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MASK 0xf0000000 +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_GET(x) (((x) & 0xf0000000) >> 28) +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_SET(x) (((x) << 28) & 0xf0000000) + +/* macros for BB_spur_mask_controls */ +#define PHY_BB_SPUR_MASK_CONTROLS_ADDRESS 0x0000994c +#define PHY_BB_SPUR_MASK_CONTROLS_OFFSET 0x0000994c +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MSB 7 +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB 0 +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK 0x000000ff +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MSB 8 +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB 8 +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK 0x00000100 +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MSB 17 +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB 17 +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK 0x00020000 +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MSB 25 +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB 18 +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK 0x03fc0000 +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_SET(x) (((x) << 18) & 0x03fc0000) + +/* macros for BB_rx_iq_corr_b0 */ +#define PHY_BB_RX_IQ_CORR_B0_ADDRESS 0x00009950 +#define PHY_BB_RX_IQ_CORR_B0_OFFSET 0x00009950 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MSB 6 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_LSB 0 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MASK 0x0000007f +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MSB 13 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_LSB 7 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MASK 0x00003f80 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MSB 14 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB 14 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK 0x00004000 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MSB 21 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB 15 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK 0x003f8000 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x003f8000) >> 15) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 15) & 0x003f8000) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MSB 28 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB 22 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK 0x1fc00000 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x1fc00000) >> 22) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_SET(x) (((x) << 22) & 0x1fc00000) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MSB 29 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_LSB 29 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MASK 0x20000000 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_SET(x) (((x) << 29) & 0x20000000) + +/* macros for BB_radar_detection */ +#define PHY_BB_RADAR_DETECTION_ADDRESS 0x00009954 +#define PHY_BB_RADAR_DETECTION_OFFSET 0x00009954 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MSB 0 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB 0 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK 0x00000001 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MSB 5 +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_LSB 1 +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MASK 0x0000003e +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_SET(x) (((x) << 1) & 0x0000003e) +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MSB 11 +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB 6 +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK 0x00000fc0 +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MSB 17 +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB 12 +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK 0x0003f000 +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MSB 23 +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_LSB 18 +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MASK 0x00fc0000 +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MSB 30 +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB 24 +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK 0x7f000000 +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MSB 31 +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_LSB 31 +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MASK 0x80000000 +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_radar_detection_2 */ +#define PHY_BB_RADAR_DETECTION_2_ADDRESS 0x00009958 +#define PHY_BB_RADAR_DETECTION_2_OFFSET 0x00009958 +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MSB 7 +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_LSB 0 +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MASK 0x000000ff +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MSB 12 +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB 8 +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK 0x00001f00 +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MSB 13 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB 13 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK 0x00002000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MSB 14 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_LSB 14 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MASK 0x00004000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MSB 15 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_LSB 15 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MASK 0x00008000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MSB 21 +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_LSB 16 +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MASK 0x003f0000 +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MSB 22 +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_LSB 22 +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MASK 0x00400000 +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MSB 23 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_LSB 23 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MASK 0x00800000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MSB 26 +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_LSB 24 +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MASK 0x07000000 +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_SET(x) (((x) << 24) & 0x07000000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MSB 27 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB 27 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK 0x08000000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_tx_phase_ramp_b0 */ +#define PHY_BB_TX_PHASE_RAMP_B0_ADDRESS 0x0000995c +#define PHY_BB_TX_PHASE_RAMP_B0_OFFSET 0x0000995c +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MSB 0 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB 0 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK 0x00000001 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MSB 6 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB 1 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK 0x0000007e +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_GET(x) (((x) & 0x0000007e) >> 1) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_SET(x) (((x) << 1) & 0x0000007e) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MSB 16 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB 7 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK 0x0001ff80 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_GET(x) (((x) & 0x0001ff80) >> 7) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_SET(x) (((x) << 7) & 0x0001ff80) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MSB 24 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB 17 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK 0x01fe0000 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_GET(x) (((x) & 0x01fe0000) >> 17) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_SET(x) (((x) << 17) & 0x01fe0000) + +/* macros for BB_switch_table_chn_b0 */ +#define PHY_BB_SWITCH_TABLE_CHN_B0_ADDRESS 0x00009960 +#define PHY_BB_SWITCH_TABLE_CHN_B0_OFFSET 0x00009960 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MSB 1 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB 0 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK 0x00000003 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_SET(x) (((x) << 0) & 0x00000003) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MSB 3 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB 2 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK 0x0000000c +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MSB 5 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB 4 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK 0x00000030 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_SET(x) (((x) << 4) & 0x00000030) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MSB 7 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB 6 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK 0x000000c0 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MSB 9 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB 8 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK 0x00000300 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_SET(x) (((x) << 8) & 0x00000300) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MSB 11 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB 10 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK 0x00000c00 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_GET(x) (((x) & 0x00000c00) >> 10) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_SET(x) (((x) << 10) & 0x00000c00) + +/* macros for BB_switch_table_com1 */ +#define PHY_BB_SWITCH_TABLE_COM1_ADDRESS 0x00009964 +#define PHY_BB_SWITCH_TABLE_COM1_OFFSET 0x00009964 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MSB 3 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB 0 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK 0x0000000f +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MSB 7 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB 4 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK 0x000000f0 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MSB 11 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB 8 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK 0x00000f00 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MSB 15 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB 12 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK 0x0000f000 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_SET(x) (((x) << 12) & 0x0000f000) + +/* macros for BB_cca_ctrl_2_b0 */ +#define PHY_BB_CCA_CTRL_2_B0_ADDRESS 0x00009968 +#define PHY_BB_CCA_CTRL_2_B0_OFFSET 0x00009968 +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MSB 8 +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_LSB 0 +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MASK 0x000001ff +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MSB 9 +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_LSB 9 +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MASK 0x00000200 +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MSB 17 +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_LSB 10 +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MASK 0x0003fc00 +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_GET(x) (((x) & 0x0003fc00) >> 10) +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_SET(x) (((x) << 10) & 0x0003fc00) +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MSB 18 +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_LSB 18 +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MASK 0x00040000 +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_SET(x) (((x) << 18) & 0x00040000) + +/* macros for BB_switch_table_com2 */ +#define PHY_BB_SWITCH_TABLE_COM2_ADDRESS 0x0000996c +#define PHY_BB_SWITCH_TABLE_COM2_OFFSET 0x0000996c +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MSB 3 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_LSB 0 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MASK 0x0000000f +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MSB 7 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_LSB 4 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MASK 0x000000f0 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MSB 11 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_LSB 8 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MASK 0x00000f00 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MSB 15 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_LSB 12 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MASK 0x0000f000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MSB 19 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_LSB 16 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MASK 0x000f0000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MSB 23 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_LSB 20 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MASK 0x00f00000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MSB 27 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_LSB 24 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MASK 0x0f000000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MSB 31 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_LSB 28 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MASK 0xf0000000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_GET(x) (((x) & 0xf0000000) >> 28) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_SET(x) (((x) << 28) & 0xf0000000) + +/* macros for BB_restart */ +#define PHY_BB_RESTART_ADDRESS 0x00009970 +#define PHY_BB_RESTART_OFFSET 0x00009970 +#define PHY_BB_RESTART_ENABLE_RESTART_MSB 0 +#define PHY_BB_RESTART_ENABLE_RESTART_LSB 0 +#define PHY_BB_RESTART_ENABLE_RESTART_MASK 0x00000001 +#define PHY_BB_RESTART_ENABLE_RESTART_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RESTART_ENABLE_RESTART_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MSB 5 +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_LSB 1 +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MASK 0x0000003e +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_SET(x) (((x) << 1) & 0x0000003e) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MSB 6 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_LSB 6 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MASK 0x00000040 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MSB 11 +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_LSB 7 +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MASK 0x00000f80 +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_GET(x) (((x) & 0x00000f80) >> 7) +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_SET(x) (((x) << 7) & 0x00000f80) +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MSB 17 +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_LSB 12 +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MASK 0x0003f000 +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MSB 20 +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_LSB 18 +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MASK 0x001c0000 +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MSB 21 +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_LSB 21 +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MASK 0x00200000 +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MSB 28 +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_LSB 22 +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MASK 0x1fc00000 +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_GET(x) (((x) & 0x1fc00000) >> 22) +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_SET(x) (((x) << 22) & 0x1fc00000) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MSB 29 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_LSB 29 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MASK 0x20000000 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_RESTART_DISABLE_DC_RESTART_MSB 30 +#define PHY_BB_RESTART_DISABLE_DC_RESTART_LSB 30 +#define PHY_BB_RESTART_DISABLE_DC_RESTART_MASK 0x40000000 +#define PHY_BB_RESTART_DISABLE_DC_RESTART_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_RESTART_DISABLE_DC_RESTART_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_RESTART_RESTART_MODE_BW40_MSB 31 +#define PHY_BB_RESTART_RESTART_MODE_BW40_LSB 31 +#define PHY_BB_RESTART_RESTART_MODE_BW40_MASK 0x80000000 +#define PHY_BB_RESTART_RESTART_MODE_BW40_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_RESTART_RESTART_MODE_BW40_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_scrambler_seed */ +#define PHY_BB_SCRAMBLER_SEED_ADDRESS 0x00009978 +#define PHY_BB_SCRAMBLER_SEED_OFFSET 0x00009978 +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MSB 6 +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB 0 +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK 0x0000007f +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_SET(x) (((x) << 0) & 0x0000007f) + +/* macros for BB_rfbus_request */ +#define PHY_BB_RFBUS_REQUEST_ADDRESS 0x0000997c +#define PHY_BB_RFBUS_REQUEST_OFFSET 0x0000997c +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MSB 0 +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB 0 +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK 0x00000001 +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_timing_control_11 */ +#define PHY_BB_TIMING_CONTROL_11_ADDRESS 0x000099a0 +#define PHY_BB_TIMING_CONTROL_11_OFFSET 0x000099a0 +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MSB 19 +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_LSB 0 +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MASK 0x000fffff +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_GET(x) (((x) & 0x000fffff) >> 0) +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_SET(x) (((x) << 0) & 0x000fffff) +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MSB 29 +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB 20 +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK 0x3ff00000 +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_GET(x) (((x) & 0x3ff00000) >> 20) +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_SET(x) (((x) << 20) & 0x3ff00000) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MSB 30 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB 30 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MSB 31 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB 31 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_multichain_enable */ +#define PHY_BB_MULTICHAIN_ENABLE_ADDRESS 0x000099a4 +#define PHY_BB_MULTICHAIN_ENABLE_OFFSET 0x000099a4 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MSB 2 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB 0 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK 0x00000007 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007) + +/* macros for BB_multichain_control */ +#define PHY_BB_MULTICHAIN_CONTROL_ADDRESS 0x000099a8 +#define PHY_BB_MULTICHAIN_CONTROL_OFFSET 0x000099a8 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MSB 0 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB 0 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK 0x00000001 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MSB 7 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB 1 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK 0x000000fe +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MSB 8 +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB 8 +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK 0x00000100 +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MSB 9 +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB 9 +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK 0x00000200 +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MSB 20 +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB 10 +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK 0x001ffc00 +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_GET(x) (((x) & 0x001ffc00) >> 10) +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_SET(x) (((x) << 10) & 0x001ffc00) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MSB 28 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB 22 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK 0x1fc00000 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_GET(x) (((x) & 0x1fc00000) >> 22) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_SET(x) (((x) << 22) & 0x1fc00000) +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MSB 29 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB 29 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK 0x20000000 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_SET(x) (((x) << 29) & 0x20000000) + +/* macros for BB_multichain_gain_ctrl */ +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ADDRESS 0x000099ac +#define PHY_BB_MULTICHAIN_GAIN_CTRL_OFFSET 0x000099ac +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MSB 7 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_LSB 0 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MASK 0x000000ff +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MSB 8 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_LSB 8 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MASK 0x00000100 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MSB 14 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_LSB 9 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MASK 0x00007e00 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_GET(x) (((x) & 0x00007e00) >> 9) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_SET(x) (((x) << 9) & 0x00007e00) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MSB 20 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_LSB 15 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MASK 0x001f8000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_GET(x) (((x) & 0x001f8000) >> 15) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_SET(x) (((x) << 15) & 0x001f8000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MSB 21 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_LSB 21 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MASK 0x00200000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MSB 22 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_LSB 22 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MASK 0x00400000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MSB 23 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_LSB 23 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MASK 0x00800000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MSB 24 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_LSB 24 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MASK 0x01000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MSB 26 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_LSB 25 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MASK 0x06000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_SET(x) (((x) << 25) & 0x06000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MSB 28 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_LSB 27 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MASK 0x18000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_GET(x) (((x) & 0x18000000) >> 27) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_SET(x) (((x) << 27) & 0x18000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MSB 29 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_LSB 29 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MASK 0x20000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MSB 30 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_LSB 30 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MASK 0x40000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_adc_gain_dc_corr_b0 */ +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADDRESS 0x000099b4 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_OFFSET 0x000099b4 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MSB 5 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB 0 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK 0x0000003f +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MSB 11 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB 6 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK 0x00000fc0 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MSB 20 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB 12 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK 0x001ff000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_GET(x) (((x) & 0x001ff000) >> 12) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_SET(x) (((x) << 12) & 0x001ff000) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MSB 29 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB 21 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK 0x3fe00000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_GET(x) (((x) & 0x3fe00000) >> 21) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_SET(x) (((x) << 21) & 0x3fe00000) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MSB 30 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB 30 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK 0x40000000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MSB 31 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB 31 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK 0x80000000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_ext_chan_pwr_thr_1 */ +#define PHY_BB_EXT_CHAN_PWR_THR_1_ADDRESS 0x000099b8 +#define PHY_BB_EXT_CHAN_PWR_THR_1_OFFSET 0x000099b8 +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MSB 7 +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_LSB 0 +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MASK 0x000000ff +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MSB 15 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_LSB 8 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MASK 0x0000ff00 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MSB 20 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_LSB 16 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MASK 0x001f0000 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MSB 26 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_LSB 21 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MASK 0x07e00000 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_SET(x) (((x) << 21) & 0x07e00000) + +/* macros for BB_ext_chan_pwr_thr_2_b0 */ +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_ADDRESS 0x000099bc +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_OFFSET 0x000099bc +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MSB 8 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_LSB 0 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MASK 0x000001ff +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MSB 15 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_LSB 9 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MASK 0x0000fe00 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_GET(x) (((x) & 0x0000fe00) >> 9) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_SET(x) (((x) << 9) & 0x0000fe00) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MSB 24 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_LSB 16 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MASK 0x01ff0000 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_GET(x) (((x) & 0x01ff0000) >> 16) + +/* macros for BB_ext_chan_scorr_thr */ +#define PHY_BB_EXT_CHAN_SCORR_THR_ADDRESS 0x000099c0 +#define PHY_BB_EXT_CHAN_SCORR_THR_OFFSET 0x000099c0 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MSB 6 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_LSB 0 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MASK 0x0000007f +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MSB 13 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_LSB 7 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MASK 0x00003f80 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MSB 20 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_LSB 14 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MASK 0x001fc000 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_SET(x) (((x) << 14) & 0x001fc000) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MSB 27 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_LSB 21 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MASK 0x0fe00000 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_SET(x) (((x) << 21) & 0x0fe00000) +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MSB 28 +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_LSB 28 +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MASK 0x10000000 +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_SET(x) (((x) << 28) & 0x10000000) + +/* macros for BB_ext_chan_detect_win */ +#define PHY_BB_EXT_CHAN_DETECT_WIN_ADDRESS 0x000099c4 +#define PHY_BB_EXT_CHAN_DETECT_WIN_OFFSET 0x000099c4 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MSB 3 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LSB 0 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MASK 0x0000000f +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MSB 7 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_LSB 4 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MASK 0x000000f0 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MSB 12 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_LSB 8 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MASK 0x00001f00 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MSB 15 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_LSB 13 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MASK 0x0000e000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MSB 18 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_LSB 16 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MASK 0x00070000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MSB 24 +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_LSB 19 +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MASK 0x01f80000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MSB 28 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_LSB 25 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MASK 0x1e000000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_GET(x) (((x) & 0x1e000000) >> 25) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_SET(x) (((x) << 25) & 0x1e000000) + +/* macros for BB_pwr_thr_20_40_det */ +#define PHY_BB_PWR_THR_20_40_DET_ADDRESS 0x000099c8 +#define PHY_BB_PWR_THR_20_40_DET_OFFSET 0x000099c8 +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MSB 4 +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_LSB 0 +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MASK 0x0000001f +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MSB 10 +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_LSB 5 +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MASK 0x000007e0 +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_GET(x) (((x) & 0x000007e0) >> 5) +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_SET(x) (((x) << 5) & 0x000007e0) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MSB 15 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_LSB 11 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MASK 0x0000f800 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_GET(x) (((x) & 0x0000f800) >> 11) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_SET(x) (((x) << 11) & 0x0000f800) +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MSB 23 +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_LSB 16 +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MASK 0x00ff0000 +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MSB 28 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_LSB 24 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MASK 0x1f000000 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_SET(x) (((x) << 24) & 0x1f000000) +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MSB 29 +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_LSB 29 +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MASK 0x20000000 +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MSB 30 +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_LSB 30 +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MASK 0x40000000 +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_short_gi_delta_slope */ +#define PHY_BB_SHORT_GI_DELTA_SLOPE_ADDRESS 0x000099d0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_OFFSET 0x000099d0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MSB 3 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_LSB 0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MASK 0x0000000f +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MSB 18 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_LSB 4 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MASK 0x0007fff0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_GET(x) (((x) & 0x0007fff0) >> 4) +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_SET(x) (((x) << 4) & 0x0007fff0) + +/* macros for BB_chaninfo_ctrl */ +#define PHY_BB_CHANINFO_CTRL_ADDRESS 0x000099dc +#define PHY_BB_CHANINFO_CTRL_OFFSET 0x000099dc +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB 0 +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB 0 +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK 0x00000001 +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MSB 1 +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB 1 +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK 0x00000002 +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_SET(x) (((x) << 1) & 0x00000002) + +/* macros for BB_heavy_clip_ctrl */ +#define PHY_BB_HEAVY_CLIP_CTRL_ADDRESS 0x000099e0 +#define PHY_BB_HEAVY_CLIP_CTRL_OFFSET 0x000099e0 +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MSB 8 +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_LSB 0 +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MASK 0x000001ff +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MSB 9 +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_LSB 9 +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MASK 0x00000200 +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_SET(x) (((x) << 9) & 0x00000200) + +/* macros for BB_heavy_clip_20 */ +#define PHY_BB_HEAVY_CLIP_20_ADDRESS 0x000099e4 +#define PHY_BB_HEAVY_CLIP_20_OFFSET 0x000099e4 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MSB 7 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_LSB 0 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MASK 0x000000ff +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MSB 15 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_LSB 8 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MASK 0x0000ff00 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MSB 23 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_LSB 16 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MASK 0x00ff0000 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MSB 31 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_LSB 24 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MASK 0xff000000 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_heavy_clip_40 */ +#define PHY_BB_HEAVY_CLIP_40_ADDRESS 0x000099e8 +#define PHY_BB_HEAVY_CLIP_40_OFFSET 0x000099e8 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MSB 7 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_LSB 0 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MASK 0x000000ff +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MSB 15 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_LSB 8 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MASK 0x0000ff00 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MSB 23 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_LSB 16 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MASK 0x00ff0000 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MSB 31 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_LSB 24 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MASK 0xff000000 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_rifs_srch */ +#define PHY_BB_RIFS_SRCH_ADDRESS 0x000099ec +#define PHY_BB_RIFS_SRCH_OFFSET 0x000099ec +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MSB 7 +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_LSB 0 +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MASK 0x000000ff +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MSB 15 +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_LSB 8 +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MASK 0x0000ff00 +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MSB 25 +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_LSB 16 +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MASK 0x03ff0000 +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_SET(x) (((x) << 16) & 0x03ff0000) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MSB 26 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_LSB 26 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MASK 0x04000000 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MSB 27 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_LSB 27 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MASK 0x08000000 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_iq_adc_cal_mode */ +#define PHY_BB_IQ_ADC_CAL_MODE_ADDRESS 0x000099f0 +#define PHY_BB_IQ_ADC_CAL_MODE_OFFSET 0x000099f0 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MSB 1 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB 0 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK 0x00000003 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_SET(x) (((x) << 0) & 0x00000003) +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MSB 2 +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB 2 +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK 0x00000004 +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_SET(x) (((x) << 2) & 0x00000004) + +/* macros for BB_per_chain_csd */ +#define PHY_BB_PER_CHAIN_CSD_ADDRESS 0x000099fc +#define PHY_BB_PER_CHAIN_CSD_OFFSET 0x000099fc +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MSB 4 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_LSB 0 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MASK 0x0000001f +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MSB 9 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_LSB 5 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MASK 0x000003e0 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MSB 14 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_LSB 10 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MASK 0x00007c00 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_SET(x) (((x) << 10) & 0x00007c00) + +/* macros for BB_rx_ocgain */ +#define PHY_BB_RX_OCGAIN_ADDRESS 0x00009a00 +#define PHY_BB_RX_OCGAIN_OFFSET 0x00009a00 +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MSB 31 +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_LSB 0 +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MASK 0xffffffff +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_crc */ +#define PHY_BB_TX_CRC_ADDRESS 0x00009c00 +#define PHY_BB_TX_CRC_OFFSET 0x00009c00 +#define PHY_BB_TX_CRC_TX_CRC_MSB 15 +#define PHY_BB_TX_CRC_TX_CRC_LSB 0 +#define PHY_BB_TX_CRC_TX_CRC_MASK 0x0000ffff +#define PHY_BB_TX_CRC_TX_CRC_GET(x) (((x) & 0x0000ffff) >> 0) + +/* macros for BB_iq_adc_meas_0_b0 */ +#define PHY_BB_IQ_ADC_MEAS_0_B0_ADDRESS 0x00009c10 +#define PHY_BB_IQ_ADC_MEAS_0_B0_OFFSET 0x00009c10 +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_iq_adc_meas_1_b0 */ +#define PHY_BB_IQ_ADC_MEAS_1_B0_ADDRESS 0x00009c14 +#define PHY_BB_IQ_ADC_MEAS_1_B0_OFFSET 0x00009c14 +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_iq_adc_meas_2_b0 */ +#define PHY_BB_IQ_ADC_MEAS_2_B0_ADDRESS 0x00009c18 +#define PHY_BB_IQ_ADC_MEAS_2_B0_OFFSET 0x00009c18 +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_iq_adc_meas_3_b0 */ +#define PHY_BB_IQ_ADC_MEAS_3_B0_ADDRESS 0x00009c1c +#define PHY_BB_IQ_ADC_MEAS_3_B0_OFFSET 0x00009c1c +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_rfbus_grant */ +#define PHY_BB_RFBUS_GRANT_ADDRESS 0x00009c20 +#define PHY_BB_RFBUS_GRANT_OFFSET 0x00009c20 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MSB 0 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB 0 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK 0x00000001 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RFBUS_GRANT_BT_ANT_MSB 1 +#define PHY_BB_RFBUS_GRANT_BT_ANT_LSB 1 +#define PHY_BB_RFBUS_GRANT_BT_ANT_MASK 0x00000002 +#define PHY_BB_RFBUS_GRANT_BT_ANT_GET(x) (((x) & 0x00000002) >> 1) + +/* macros for BB_tstadc */ +#define PHY_BB_TSTADC_ADDRESS 0x00009c24 +#define PHY_BB_TSTADC_OFFSET 0x00009c24 +#define PHY_BB_TSTADC_TSTADC_OUT_Q_MSB 9 +#define PHY_BB_TSTADC_TSTADC_OUT_Q_LSB 0 +#define PHY_BB_TSTADC_TSTADC_OUT_Q_MASK 0x000003ff +#define PHY_BB_TSTADC_TSTADC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_TSTADC_TSTADC_OUT_I_MSB 19 +#define PHY_BB_TSTADC_TSTADC_OUT_I_LSB 10 +#define PHY_BB_TSTADC_TSTADC_OUT_I_MASK 0x000ffc00 +#define PHY_BB_TSTADC_TSTADC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10) + +/* macros for BB_tstdac */ +#define PHY_BB_TSTDAC_ADDRESS 0x00009c28 +#define PHY_BB_TSTDAC_OFFSET 0x00009c28 +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MSB 9 +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB 0 +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK 0x000003ff +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MSB 19 +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB 10 +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK 0x000ffc00 +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10) + +/* macros for BB_illegal_tx_rate */ +#define PHY_BB_ILLEGAL_TX_RATE_ADDRESS 0x00009c30 +#define PHY_BB_ILLEGAL_TX_RATE_OFFSET 0x00009c30 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MSB 0 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_LSB 0 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MASK 0x00000001 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_GET(x) (((x) & 0x00000001) >> 0) + +/* macros for BB_spur_report_b0 */ +#define PHY_BB_SPUR_REPORT_B0_ADDRESS 0x00009c34 +#define PHY_BB_SPUR_REPORT_B0_OFFSET 0x00009c34 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MSB 7 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB 0 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK 0x000000ff +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MSB 15 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB 8 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK 0x0000ff00 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MSB 31 +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB 16 +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK 0xffff0000 +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_GET(x) (((x) & 0xffff0000) >> 16) + +/* macros for BB_channel_status */ +#define PHY_BB_CHANNEL_STATUS_ADDRESS 0x00009c38 +#define PHY_BB_CHANNEL_STATUS_OFFSET 0x00009c38 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MSB 0 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB 0 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK 0x00000001 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MSB 1 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB 1 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK 0x00000002 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MSB 2 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB 2 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK 0x00000004 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MSB 3 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB 3 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK 0x00000008 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MSB 5 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB 4 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK 0x00000030 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MSB 7 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB 6 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK 0x000000c0 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MSB 9 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB 8 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK 0x00000300 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MSB 13 +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB 10 +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK 0x00003c00 +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MSB 16 +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB 14 +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK 0x0001c000 +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_GET(x) (((x) & 0x0001c000) >> 14) + +/* macros for BB_rssi_b0 */ +#define PHY_BB_RSSI_B0_ADDRESS 0x00009c3c +#define PHY_BB_RSSI_B0_OFFSET 0x00009c3c +#define PHY_BB_RSSI_B0_RSSI_0_MSB 7 +#define PHY_BB_RSSI_B0_RSSI_0_LSB 0 +#define PHY_BB_RSSI_B0_RSSI_0_MASK 0x000000ff +#define PHY_BB_RSSI_B0_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RSSI_B0_RSSI_EXT_0_MSB 15 +#define PHY_BB_RSSI_B0_RSSI_EXT_0_LSB 8 +#define PHY_BB_RSSI_B0_RSSI_EXT_0_MASK 0x0000ff00 +#define PHY_BB_RSSI_B0_RSSI_EXT_0_GET(x) (((x) & 0x0000ff00) >> 8) + +/* macros for BB_spur_est_cck_report_b0 */ +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_ADDRESS 0x00009c40 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_OFFSET 0x00009c40 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MSB 7 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_LSB 0 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MASK 0x000000ff +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MSB 15 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_LSB 8 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MASK 0x0000ff00 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MSB 23 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_LSB 16 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MASK 0x00ff0000 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MSB 31 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_LSB 24 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MASK 0xff000000 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_GET(x) (((x) & 0xff000000) >> 24) + +/* macros for BB_chan_info_noise_pwr */ +#define PHY_BB_CHAN_INFO_NOISE_PWR_ADDRESS 0x00009cac +#define PHY_BB_CHAN_INFO_NOISE_PWR_OFFSET 0x00009cac +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MSB 11 +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_LSB 0 +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MASK 0x00000fff +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_GET(x) (((x) & 0x00000fff) >> 0) + +/* macros for BB_chan_info_gain_diff */ +#define PHY_BB_CHAN_INFO_GAIN_DIFF_ADDRESS 0x00009cb0 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_OFFSET 0x00009cb0 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MSB 11 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_LSB 0 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MASK 0x00000fff +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_GET(x) (((x) & 0x00000fff) >> 0) + +/* macros for BB_chan_info_fine_timing */ +#define PHY_BB_CHAN_INFO_FINE_TIMING_ADDRESS 0x00009cb4 +#define PHY_BB_CHAN_INFO_FINE_TIMING_OFFSET 0x00009cb4 +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MSB 11 +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB 0 +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK 0x00000fff +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MSB 21 +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB 12 +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK 0x003ff000 +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_GET(x) (((x) & 0x003ff000) >> 12) + +/* macros for BB_chan_info_gain_b0 */ +#define PHY_BB_CHAN_INFO_GAIN_B0_ADDRESS 0x00009cb8 +#define PHY_BB_CHAN_INFO_GAIN_B0_OFFSET 0x00009cb8 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MSB 7 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB 0 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK 0x000000ff +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MSB 15 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB 8 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK 0x0000ff00 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MSB 16 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB 16 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK 0x00010000 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MSB 17 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB 17 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK 0x00020000 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_GET(x) (((x) & 0x00020000) >> 17) + +/* macros for BB_chan_info_chan_tab_b0 */ +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_ADDRESS 0x00009cbc +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_OFFSET 0x00009cbc +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MSB 5 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_LSB 0 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MASK 0x0000003f +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MSB 11 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_LSB 6 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MASK 0x00000fc0 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MSB 15 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_LSB 12 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MASK 0x0000f000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MSB 21 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_LSB 16 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MASK 0x003f0000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MSB 27 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_LSB 22 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MASK 0x0fc00000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_GET(x) (((x) & 0x0fc00000) >> 22) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MSB 31 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_LSB 28 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MASK 0xf0000000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_GET(x) (((x) & 0xf0000000) >> 28) + +/* macros for BB_paprd_am2am_mask */ +#define PHY_BB_PAPRD_AM2AM_MASK_ADDRESS 0x00009de4 +#define PHY_BB_PAPRD_AM2AM_MASK_OFFSET 0x00009de4 +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MSB 24 +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB 0 +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK 0x01ffffff +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_GET(x) (((x) & 0x01ffffff) >> 0) +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_SET(x) (((x) << 0) & 0x01ffffff) + +/* macros for BB_paprd_am2pm_mask */ +#define PHY_BB_PAPRD_AM2PM_MASK_ADDRESS 0x00009de8 +#define PHY_BB_PAPRD_AM2PM_MASK_OFFSET 0x00009de8 +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MSB 24 +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB 0 +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK 0x01ffffff +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_GET(x) (((x) & 0x01ffffff) >> 0) +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_SET(x) (((x) << 0) & 0x01ffffff) + +/* macros for BB_paprd_ht40_mask */ +#define PHY_BB_PAPRD_HT40_MASK_ADDRESS 0x00009dec +#define PHY_BB_PAPRD_HT40_MASK_OFFSET 0x00009dec +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MSB 24 +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB 0 +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK 0x01ffffff +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_GET(x) (((x) & 0x01ffffff) >> 0) +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_SET(x) (((x) << 0) & 0x01ffffff) + +/* macros for BB_paprd_ctrl0 */ +#define PHY_BB_PAPRD_CTRL0_ADDRESS 0x00009df0 +#define PHY_BB_PAPRD_CTRL0_OFFSET 0x00009df0 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MSB 0 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_LSB 0 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MASK 0x00000001 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MSB 1 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_LSB 1 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MASK 0x00000002 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MSB 26 +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_LSB 2 +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MASK 0x07fffffc +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_GET(x) (((x) & 0x07fffffc) >> 2) +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_SET(x) (((x) << 2) & 0x07fffffc) +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MSB 31 +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_LSB 27 +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MASK 0xf8000000 +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for BB_paprd_ctrl1 */ +#define PHY_BB_PAPRD_CTRL1_ADDRESS 0x00009df4 +#define PHY_BB_PAPRD_CTRL1_OFFSET 0x00009df4 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MSB 0 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_LSB 0 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MASK 0x00000001 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MSB 1 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_LSB 1 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MASK 0x00000002 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MSB 2 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_LSB 2 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MASK 0x00000004 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MSB 8 +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_LSB 3 +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MASK 0x000001f8 +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_GET(x) (((x) & 0x000001f8) >> 3) +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_SET(x) (((x) << 3) & 0x000001f8) +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MSB 16 +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_LSB 9 +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MASK 0x0001fe00 +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_GET(x) (((x) & 0x0001fe00) >> 9) +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_SET(x) (((x) << 9) & 0x0001fe00) +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MSB 26 +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_LSB 17 +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MASK 0x07fe0000 +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_GET(x) (((x) & 0x07fe0000) >> 17) +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_SET(x) (((x) << 17) & 0x07fe0000) +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MSB 27 +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_LSB 27 +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MASK 0x08000000 +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_pa_gain123 */ +#define PHY_BB_PA_GAIN123_ADDRESS 0x00009df8 +#define PHY_BB_PA_GAIN123_OFFSET 0x00009df8 +#define PHY_BB_PA_GAIN123_PA_GAIN1_MSB 9 +#define PHY_BB_PA_GAIN123_PA_GAIN1_LSB 0 +#define PHY_BB_PA_GAIN123_PA_GAIN1_MASK 0x000003ff +#define PHY_BB_PA_GAIN123_PA_GAIN1_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PA_GAIN123_PA_GAIN1_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PA_GAIN123_PA_GAIN2_MSB 19 +#define PHY_BB_PA_GAIN123_PA_GAIN2_LSB 10 +#define PHY_BB_PA_GAIN123_PA_GAIN2_MASK 0x000ffc00 +#define PHY_BB_PA_GAIN123_PA_GAIN2_GET(x) (((x) & 0x000ffc00) >> 10) +#define PHY_BB_PA_GAIN123_PA_GAIN2_SET(x) (((x) << 10) & 0x000ffc00) +#define PHY_BB_PA_GAIN123_PA_GAIN3_MSB 29 +#define PHY_BB_PA_GAIN123_PA_GAIN3_LSB 20 +#define PHY_BB_PA_GAIN123_PA_GAIN3_MASK 0x3ff00000 +#define PHY_BB_PA_GAIN123_PA_GAIN3_GET(x) (((x) & 0x3ff00000) >> 20) +#define PHY_BB_PA_GAIN123_PA_GAIN3_SET(x) (((x) << 20) & 0x3ff00000) + +/* macros for BB_pa_gain45 */ +#define PHY_BB_PA_GAIN45_ADDRESS 0x00009dfc +#define PHY_BB_PA_GAIN45_OFFSET 0x00009dfc +#define PHY_BB_PA_GAIN45_PA_GAIN4_MSB 9 +#define PHY_BB_PA_GAIN45_PA_GAIN4_LSB 0 +#define PHY_BB_PA_GAIN45_PA_GAIN4_MASK 0x000003ff +#define PHY_BB_PA_GAIN45_PA_GAIN4_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PA_GAIN45_PA_GAIN4_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PA_GAIN45_PA_GAIN5_MSB 19 +#define PHY_BB_PA_GAIN45_PA_GAIN5_LSB 10 +#define PHY_BB_PA_GAIN45_PA_GAIN5_MASK 0x000ffc00 +#define PHY_BB_PA_GAIN45_PA_GAIN5_GET(x) (((x) & 0x000ffc00) >> 10) +#define PHY_BB_PA_GAIN45_PA_GAIN5_SET(x) (((x) << 10) & 0x000ffc00) +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MSB 24 +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_LSB 20 +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MASK 0x01f00000 +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_SET(x) (((x) << 20) & 0x01f00000) + +/* macros for BB_paprd_pre_post_scale_0 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_ADDRESS 0x00009e00 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_OFFSET 0x00009e00 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_1 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_ADDRESS 0x00009e04 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_OFFSET 0x00009e04 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_2 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_ADDRESS 0x00009e08 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_OFFSET 0x00009e08 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_3 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_ADDRESS 0x00009e0c +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_OFFSET 0x00009e0c +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_4 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_ADDRESS 0x00009e10 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_OFFSET 0x00009e10 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_5 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_ADDRESS 0x00009e14 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_OFFSET 0x00009e14 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_6 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_ADDRESS 0x00009e18 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_OFFSET 0x00009e18 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_7 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_ADDRESS 0x00009e1c +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_OFFSET 0x00009e1c +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_mem_tab */ +#define PHY_BB_PAPRD_MEM_TAB_ADDRESS 0x00009e20 +#define PHY_BB_PAPRD_MEM_TAB_OFFSET 0x00009e20 +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MSB 21 +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_LSB 0 +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MASK 0x003fffff +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_GET(x) (((x) & 0x003fffff) >> 0) +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_SET(x) (((x) << 0) & 0x003fffff) + +/* macros for BB_peak_det_ctrl_1 */ +#define PHY_BB_PEAK_DET_CTRL_1_ADDRESS 0x0000a000 +#define PHY_BB_PEAK_DET_CTRL_1_OFFSET 0x0000a000 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MSB 0 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_LSB 0 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MASK 0x00000001 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MSB 1 +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_LSB 1 +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MASK 0x00000002 +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MSB 7 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_LSB 2 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MASK 0x000000fc +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MSB 12 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_LSB 8 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MASK 0x00001f00 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MSB 17 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_LSB 13 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MASK 0x0003e000 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_GET(x) (((x) & 0x0003e000) >> 13) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_SET(x) (((x) << 13) & 0x0003e000) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MSB 22 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_LSB 18 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MASK 0x007c0000 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_GET(x) (((x) & 0x007c0000) >> 18) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_SET(x) (((x) << 18) & 0x007c0000) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MSB 29 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_LSB 23 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MASK 0x3f800000 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MSB 30 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_LSB 30 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MASK 0x40000000 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MSB 31 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_LSB 31 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MASK 0x80000000 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_peak_det_ctrl_2 */ +#define PHY_BB_PEAK_DET_CTRL_2_ADDRESS 0x0000a004 +#define PHY_BB_PEAK_DET_CTRL_2_OFFSET 0x0000a004 +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MSB 9 +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_LSB 0 +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MASK 0x000003ff +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MSB 14 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_LSB 10 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MASK 0x00007c00 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MSB 19 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_LSB 15 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MASK 0x000f8000 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MSB 24 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_LSB 20 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MASK 0x01f00000 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MSB 29 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_LSB 25 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MASK 0x3e000000 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_rx_gain_bounds_1 */ +#define PHY_BB_RX_GAIN_BOUNDS_1_ADDRESS 0x0000a008 +#define PHY_BB_RX_GAIN_BOUNDS_1_OFFSET 0x0000a008 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MSB 7 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_LSB 0 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MASK 0x000000ff +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MSB 15 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_LSB 8 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MASK 0x0000ff00 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MSB 23 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_LSB 16 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MASK 0x00ff0000 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MSB 24 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_LSB 24 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MASK 0x01000000 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MSB 25 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_LSB 25 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MASK 0x02000000 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_SET(x) (((x) << 25) & 0x02000000) + +/* macros for BB_rx_gain_bounds_2 */ +#define PHY_BB_RX_GAIN_BOUNDS_2_ADDRESS 0x0000a00c +#define PHY_BB_RX_GAIN_BOUNDS_2_OFFSET 0x0000a00c +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MSB 7 +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_LSB 0 +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MASK 0x000000ff +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MSB 15 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_LSB 8 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MASK 0x0000ff00 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MSB 23 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_LSB 16 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MASK 0x00ff0000 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MSB 31 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_LSB 24 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MASK 0xff000000 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_peak_det_cal_ctrl */ +#define PHY_BB_PEAK_DET_CAL_CTRL_ADDRESS 0x0000a010 +#define PHY_BB_PEAK_DET_CAL_CTRL_OFFSET 0x0000a010 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MSB 5 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_LSB 0 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MASK 0x0000003f +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MSB 11 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_LSB 6 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MASK 0x00000fc0 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MSB 13 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_LSB 12 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MASK 0x00003000 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000) + +/* macros for BB_agc_dig_dc_ctrl */ +#define PHY_BB_AGC_DIG_DC_CTRL_ADDRESS 0x0000a014 +#define PHY_BB_AGC_DIG_DC_CTRL_OFFSET 0x0000a014 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MSB 0 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_LSB 0 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MASK 0x00000001 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MSB 3 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_LSB 1 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MASK 0x0000000e +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MSB 9 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_LSB 4 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MASK 0x000003f0 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_GET(x) (((x) & 0x000003f0) >> 4) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_SET(x) (((x) << 4) & 0x000003f0) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MSB 31 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_LSB 16 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MASK 0xffff0000 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_GET(x) (((x) & 0xffff0000) >> 16) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_SET(x) (((x) << 16) & 0xffff0000) + +/* macros for BB_agc_dig_dc_status_i_b0 */ +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_ADDRESS 0x0000a018 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_OFFSET 0x0000a018 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MSB 8 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_LSB 0 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MASK 0x000001ff +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MSB 17 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_LSB 9 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MASK 0x0003fe00 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_GET(x) (((x) & 0x0003fe00) >> 9) +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MSB 26 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_LSB 18 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MASK 0x07fc0000 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_GET(x) (((x) & 0x07fc0000) >> 18) + +/* macros for BB_agc_dig_dc_status_q_b0 */ +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_ADDRESS 0x0000a01c +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_OFFSET 0x0000a01c +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MSB 8 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_LSB 0 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MASK 0x000001ff +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MSB 17 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_LSB 9 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MASK 0x0003fe00 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_GET(x) (((x) & 0x0003fe00) >> 9) +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MSB 26 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_LSB 18 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MASK 0x07fc0000 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_GET(x) (((x) & 0x07fc0000) >> 18) + +/* macros for BB_bbb_txfir_0 */ +#define PHY_BB_BBB_TXFIR_0_ADDRESS 0x0000a1f4 +#define PHY_BB_BBB_TXFIR_0_OFFSET 0x0000a1f4 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MSB 3 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB 0 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK 0x0000000f +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MSB 11 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB 8 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK 0x00000f00 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MSB 20 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB 16 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK 0x001f0000 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MSB 28 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB 24 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK 0x1f000000 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_SET(x) (((x) << 24) & 0x1f000000) + +/* macros for BB_bbb_txfir_1 */ +#define PHY_BB_BBB_TXFIR_1_ADDRESS 0x0000a1f8 +#define PHY_BB_BBB_TXFIR_1_OFFSET 0x0000a1f8 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MSB 5 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB 0 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK 0x0000003f +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MSB 13 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB 8 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK 0x00003f00 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MSB 22 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB 16 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK 0x007f0000 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MSB 30 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB 24 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK 0x7f000000 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for BB_bbb_txfir_2 */ +#define PHY_BB_BBB_TXFIR_2_ADDRESS 0x0000a1fc +#define PHY_BB_BBB_TXFIR_2_OFFSET 0x0000a1fc +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MSB 7 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB 0 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK 0x000000ff +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MSB 15 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB 8 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK 0x0000ff00 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MSB 23 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB 16 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK 0x00ff0000 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MSB 31 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB 24 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK 0xff000000 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_modes_select */ +#define PHY_BB_MODES_SELECT_ADDRESS 0x0000a200 +#define PHY_BB_MODES_SELECT_OFFSET 0x0000a200 +#define PHY_BB_MODES_SELECT_CCK_MODE_MSB 0 +#define PHY_BB_MODES_SELECT_CCK_MODE_LSB 0 +#define PHY_BB_MODES_SELECT_CCK_MODE_MASK 0x00000001 +#define PHY_BB_MODES_SELECT_CCK_MODE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_MODES_SELECT_CCK_MODE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MSB 2 +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB 2 +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK 0x00000004 +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MSB 5 +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB 5 +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK 0x00000020 +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MSB 6 +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB 6 +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK 0x00000040 +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MSB 7 +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB 7 +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK 0x00000080 +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MSB 8 +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB 8 +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK 0x00000100 +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_SET(x) (((x) << 8) & 0x00000100) + +/* macros for BB_bbb_tx_ctrl */ +#define PHY_BB_BBB_TX_CTRL_ADDRESS 0x0000a204 +#define PHY_BB_BBB_TX_CTRL_OFFSET 0x0000a204 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MSB 0 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB 0 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK 0x00000001 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MSB 1 +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB 1 +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK 0x00000002 +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MSB 3 +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB 2 +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK 0x0000000c +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MSB 4 +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB 4 +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK 0x00000010 +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MSB 5 +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB 5 +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK 0x00000020 +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MSB 8 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB 6 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK 0x000001c0 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MSB 11 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB 9 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK 0x00000e00 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_SET(x) (((x) << 9) & 0x00000e00) + +/* macros for BB_bbb_sig_detect */ +#define PHY_BB_BBB_SIG_DETECT_ADDRESS 0x0000a208 +#define PHY_BB_BBB_SIG_DETECT_OFFSET 0x0000a208 +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MSB 5 +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_LSB 0 +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MASK 0x0000003f +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MSB 12 +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_LSB 6 +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MASK 0x00001fc0 +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_GET(x) (((x) & 0x00001fc0) >> 6) +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_SET(x) (((x) << 6) & 0x00001fc0) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MSB 13 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_LSB 13 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MASK 0x00002000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MSB 14 +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_LSB 14 +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MASK 0x00004000 +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MSB 15 +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_LSB 15 +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MASK 0x00008000 +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MSB 16 +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_LSB 16 +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MASK 0x00010000 +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MSB 17 +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_LSB 17 +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MASK 0x00020000 +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MSB 18 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_LSB 18 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MASK 0x00040000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MSB 19 +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_LSB 19 +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MASK 0x00080000 +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MSB 20 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_LSB 20 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MASK 0x00100000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MSB 21 +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_LSB 21 +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MASK 0x00200000 +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MSB 22 +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_LSB 22 +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MASK 0x00400000 +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MSB 31 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_LSB 31 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MASK 0x80000000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_ext_atten_switch_ctl_b0 */ +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_ADDRESS 0x0000a20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_OFFSET 0x0000a20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MSB 5 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_LSB 0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MASK 0x0000003f +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MSB 11 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_LSB 6 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MASK 0x00000fc0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MSB 16 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_LSB 12 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MASK 0x0001f000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MSB 21 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_LSB 17 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MASK 0x003e0000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_SET(x) (((x) << 17) & 0x003e0000) + +/* macros for BB_bbb_rx_ctrl_1 */ +#define PHY_BB_BBB_RX_CTRL_1_ADDRESS 0x0000a210 +#define PHY_BB_BBB_RX_CTRL_1_OFFSET 0x0000a210 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MSB 2 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_LSB 0 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MASK 0x00000007 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MSB 7 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_LSB 3 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MASK 0x000000f8 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_GET(x) (((x) & 0x000000f8) >> 3) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_SET(x) (((x) << 3) & 0x000000f8) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MSB 10 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_LSB 8 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MASK 0x00000700 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_SET(x) (((x) << 8) & 0x00000700) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MSB 15 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_LSB 11 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MASK 0x0000f800 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_GET(x) (((x) & 0x0000f800) >> 11) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_SET(x) (((x) << 11) & 0x0000f800) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MSB 20 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_LSB 16 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MASK 0x001f0000 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MSB 23 +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_LSB 21 +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MASK 0x00e00000 +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MSB 30 +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_LSB 24 +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MASK 0x7f000000 +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MSB 31 +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_LSB 31 +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MASK 0x80000000 +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_bbb_rx_ctrl_2 */ +#define PHY_BB_BBB_RX_CTRL_2_ADDRESS 0x0000a214 +#define PHY_BB_BBB_RX_CTRL_2_OFFSET 0x0000a214 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MSB 5 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_LSB 0 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MASK 0x0000003f +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MSB 11 +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_LSB 6 +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MASK 0x00000fc0 +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MSB 16 +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_LSB 12 +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MASK 0x0001f000 +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MSB 21 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_LSB 17 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MASK 0x003e0000 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MSB 25 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_LSB 22 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MASK 0x03c00000 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_GET(x) (((x) & 0x03c00000) >> 22) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_SET(x) (((x) << 22) & 0x03c00000) +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MSB 31 +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_LSB 26 +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MASK 0xfc000000 +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for BB_bbb_rx_ctrl_3 */ +#define PHY_BB_BBB_RX_CTRL_3_ADDRESS 0x0000a218 +#define PHY_BB_BBB_RX_CTRL_3_OFFSET 0x0000a218 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MSB 7 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_LSB 0 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MASK 0x000000ff +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MSB 15 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_LSB 8 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MASK 0x0000ff00 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MSB 23 +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_LSB 16 +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MASK 0x00ff0000 +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_SET(x) (((x) << 16) & 0x00ff0000) + +/* macros for BB_bbb_rx_ctrl_4 */ +#define PHY_BB_BBB_RX_CTRL_4_ADDRESS 0x0000a21c +#define PHY_BB_BBB_RX_CTRL_4_OFFSET 0x0000a21c +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MSB 3 +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_LSB 0 +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MASK 0x0000000f +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MSB 15 +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_LSB 4 +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MASK 0x0000fff0 +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_GET(x) (((x) & 0x0000fff0) >> 4) +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_SET(x) (((x) << 4) & 0x0000fff0) +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MSB 16 +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_LSB 16 +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MASK 0x00010000 +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MSB 17 +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_LSB 17 +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MASK 0x00020000 +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MSB 18 +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_LSB 18 +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MASK 0x00040000 +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MSB 24 +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_LSB 19 +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MASK 0x01f80000 +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MSB 30 +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_LSB 25 +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MASK 0x7e000000 +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_GET(x) (((x) & 0x7e000000) >> 25) +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_SET(x) (((x) << 25) & 0x7e000000) + +/* macros for BB_bbb_rx_ctrl_5 */ +#define PHY_BB_BBB_RX_CTRL_5_ADDRESS 0x0000a220 +#define PHY_BB_BBB_RX_CTRL_5_OFFSET 0x0000a220 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MSB 4 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_LSB 0 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MASK 0x0000001f +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MSB 9 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_LSB 5 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MASK 0x000003e0 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MSB 15 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_LSB 10 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MASK 0x0000fc00 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_GET(x) (((x) & 0x0000fc00) >> 10) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_SET(x) (((x) << 10) & 0x0000fc00) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MSB 20 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_LSB 16 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MASK 0x001f0000 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MSB 26 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_LSB 21 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MASK 0x07e00000 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_SET(x) (((x) << 21) & 0x07e00000) + +/* macros for BB_bbb_rx_ctrl_6 */ +#define PHY_BB_BBB_RX_CTRL_6_ADDRESS 0x0000a224 +#define PHY_BB_BBB_RX_CTRL_6_OFFSET 0x0000a224 +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MSB 9 +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_LSB 0 +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MASK 0x000003ff +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MSB 10 +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_LSB 10 +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MASK 0x00000400 +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MSB 20 +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_LSB 11 +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MASK 0x001ff800 +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_GET(x) (((x) & 0x001ff800) >> 11) +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_SET(x) (((x) << 11) & 0x001ff800) + +/* macros for BB_bbb_dagc_ctrl */ +#define PHY_BB_BBB_DAGC_CTRL_ADDRESS 0x0000a228 +#define PHY_BB_BBB_DAGC_CTRL_OFFSET 0x0000a228 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MSB 0 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_LSB 0 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MASK 0x00000001 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MSB 8 +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_LSB 1 +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MASK 0x000001fe +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_SET(x) (((x) << 1) & 0x000001fe) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MSB 9 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_LSB 9 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MASK 0x00000200 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MSB 16 +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_LSB 10 +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MASK 0x0001fc00 +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_SET(x) (((x) << 10) & 0x0001fc00) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MSB 17 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_LSB 17 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MASK 0x00020000 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MSB 23 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_LSB 18 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MASK 0x00fc0000 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MSB 27 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_LSB 24 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MASK 0x0f000000 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_SET(x) (((x) << 24) & 0x0f000000) + +/* macros for BB_force_clken_cck */ +#define PHY_BB_FORCE_CLKEN_CCK_ADDRESS 0x0000a22c +#define PHY_BB_FORCE_CLKEN_CCK_OFFSET 0x0000a22c +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MSB 0 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_LSB 0 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MASK 0x00000001 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MSB 1 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_LSB 1 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MASK 0x00000002 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MSB 2 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_LSB 2 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MASK 0x00000004 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MSB 3 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_LSB 3 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MASK 0x00000008 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MSB 4 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_LSB 4 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MASK 0x00000010 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MSB 5 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_LSB 5 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MASK 0x00000020 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_SET(x) (((x) << 5) & 0x00000020) + +/* macros for BB_rx_clear_delay */ +#define PHY_BB_RX_CLEAR_DELAY_ADDRESS 0x0000a230 +#define PHY_BB_RX_CLEAR_DELAY_OFFSET 0x0000a230 +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MSB 9 +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_LSB 0 +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MASK 0x000003ff +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_SET(x) (((x) << 0) & 0x000003ff) + +/* macros for BB_powertx_rate3 */ +#define PHY_BB_POWERTX_RATE3_ADDRESS 0x0000a234 +#define PHY_BB_POWERTX_RATE3_OFFSET 0x0000a234 +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MSB 5 +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_LSB 0 +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MSB 21 +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_LSB 16 +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MSB 29 +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_LSB 24 +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate4 */ +#define PHY_BB_POWERTX_RATE4_ADDRESS 0x0000a238 +#define PHY_BB_POWERTX_RATE4_OFFSET 0x0000a238 +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MSB 5 +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_LSB 0 +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MSB 13 +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_LSB 8 +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MSB 21 +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_LSB 16 +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MSB 29 +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_LSB 24 +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_cck_spur_mit */ +#define PHY_BB_CCK_SPUR_MIT_ADDRESS 0x0000a240 +#define PHY_BB_CCK_SPUR_MIT_OFFSET 0x0000a240 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MSB 0 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_LSB 0 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MASK 0x00000001 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MSB 8 +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_LSB 1 +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MASK 0x000001fe +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_SET(x) (((x) << 1) & 0x000001fe) +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MSB 28 +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_LSB 9 +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MASK 0x1ffffe00 +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_GET(x) (((x) & 0x1ffffe00) >> 9) +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_SET(x) (((x) << 9) & 0x1ffffe00) +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MSB 30 +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_LSB 29 +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MASK 0x60000000 +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_SET(x) (((x) << 29) & 0x60000000) + +/* macros for BB_panic_watchdog_status */ +#define PHY_BB_PANIC_WATCHDOG_STATUS_ADDRESS 0x0000a244 +#define PHY_BB_PANIC_WATCHDOG_STATUS_OFFSET 0x0000a244 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MSB 2 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_LSB 0 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MASK 0x00000007 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MSB 3 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_LSB 3 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MASK 0x00000008 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MSB 7 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_LSB 4 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MASK 0x000000f0 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MSB 11 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_LSB 8 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MASK 0x00000f00 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MSB 15 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_LSB 12 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MASK 0x0000f000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MSB 19 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_LSB 16 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MASK 0x000f0000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MSB 23 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_LSB 20 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MASK 0x00f00000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MSB 27 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_LSB 24 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MASK 0x0f000000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MSB 31 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_LSB 28 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MASK 0xf0000000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_GET(x) (((x) & 0xf0000000) >> 28) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_SET(x) (((x) << 28) & 0xf0000000) + +/* macros for BB_panic_watchdog_ctrl_1 */ +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ADDRESS 0x0000a248 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_OFFSET 0x0000a248 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_LSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MASK 0x00000001 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_LSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MASK 0x00000002 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MSB 15 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_LSB 2 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MASK 0x0000fffc +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_GET(x) (((x) & 0x0000fffc) >> 2) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_SET(x) (((x) << 2) & 0x0000fffc) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MSB 31 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_LSB 16 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MASK 0xffff0000 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_GET(x) (((x) & 0xffff0000) >> 16) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_SET(x) (((x) << 16) & 0xffff0000) + +/* macros for BB_panic_watchdog_ctrl_2 */ +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_ADDRESS 0x0000a24c +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_OFFSET 0x0000a24c +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK 0x00000001 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_LSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MASK 0x00000002 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MSB 2 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_LSB 2 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MASK 0x00000004 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_SET(x) (((x) << 2) & 0x00000004) + +/* macros for BB_iqcorr_ctrl_cck */ +#define PHY_BB_IQCORR_CTRL_CCK_ADDRESS 0x0000a250 +#define PHY_BB_IQCORR_CTRL_CCK_OFFSET 0x0000a250 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MSB 4 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_LSB 0 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MASK 0x0000001f +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MSB 10 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_LSB 5 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MASK 0x000007e0 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_GET(x) (((x) & 0x000007e0) >> 5) +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_SET(x) (((x) << 5) & 0x000007e0) +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MSB 11 +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_LSB 11 +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MASK 0x00000800 +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MSB 13 +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_LSB 12 +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MASK 0x00003000 +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000) +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MSB 15 +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_LSB 14 +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MASK 0x0000c000 +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MSB 20 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_LSB 16 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MASK 0x001f0000 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MSB 21 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_LSB 21 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MASK 0x00200000 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_SET(x) (((x) << 21) & 0x00200000) + +/* macros for BB_bluetooth_cntl */ +#define PHY_BB_BLUETOOTH_CNTL_ADDRESS 0x0000a254 +#define PHY_BB_BLUETOOTH_CNTL_OFFSET 0x0000a254 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MSB 0 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB 0 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK 0x00000001 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MSB 1 +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB 1 +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK 0x00000002 +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_SET(x) (((x) << 1) & 0x00000002) + +/* macros for BB_tpc_1 */ +#define PHY_BB_TPC_1_ADDRESS 0x0000a258 +#define PHY_BB_TPC_1_OFFSET 0x0000a258 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MSB 0 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_LSB 0 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MASK 0x00000001 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MSB 5 +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_LSB 1 +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MASK 0x0000003e +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_SET(x) (((x) << 1) & 0x0000003e) +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MSB 13 +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_LSB 6 +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MASK 0x00003fc0 +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_GET(x) (((x) & 0x00003fc0) >> 6) +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_SET(x) (((x) << 6) & 0x00003fc0) +#define PHY_BB_TPC_1_NUM_PD_GAIN_MSB 15 +#define PHY_BB_TPC_1_NUM_PD_GAIN_LSB 14 +#define PHY_BB_TPC_1_NUM_PD_GAIN_MASK 0x0000c000 +#define PHY_BB_TPC_1_NUM_PD_GAIN_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_BB_TPC_1_NUM_PD_GAIN_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MSB 17 +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_LSB 16 +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MASK 0x00030000 +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_SET(x) (((x) << 16) & 0x00030000) +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MSB 19 +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_LSB 18 +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MASK 0x000c0000 +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MSB 21 +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_LSB 20 +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MASK 0x00300000 +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_SET(x) (((x) << 20) & 0x00300000) +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MSB 22 +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_LSB 22 +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MASK 0x00400000 +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MSB 28 +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_LSB 23 +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MASK 0x1f800000 +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_GET(x) (((x) & 0x1f800000) >> 23) +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_SET(x) (((x) << 23) & 0x1f800000) +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MSB 29 +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_LSB 29 +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MASK 0x20000000 +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MSB 31 +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_LSB 30 +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MASK 0xc0000000 +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB_tpc_2 */ +#define PHY_BB_TPC_2_ADDRESS 0x0000a25c +#define PHY_BB_TPC_2_OFFSET 0x0000a25c +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MSB 7 +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB 0 +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK 0x000000ff +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MSB 15 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB 8 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK 0x0000ff00 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MSB 23 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB 16 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK 0x00ff0000 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_SET(x) (((x) << 16) & 0x00ff0000) + +/* macros for BB_tpc_3 */ +#define PHY_BB_TPC_3_ADDRESS 0x0000a260 +#define PHY_BB_TPC_3_OFFSET 0x0000a260 +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MSB 7 +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB 0 +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK 0x000000ff +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MSB 15 +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB 8 +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK 0x0000ff00 +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MSB 18 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_LSB 16 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MASK 0x00070000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MSB 21 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_LSB 19 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MASK 0x00380000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_SET(x) (((x) << 19) & 0x00380000) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MSB 24 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB 22 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK 0x01c00000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MSB 27 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB 25 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK 0x0e000000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MSB 31 +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB 31 +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK 0x80000000 +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_tpc_4_b0 */ +#define PHY_BB_TPC_4_B0_ADDRESS 0x0000a264 +#define PHY_BB_TPC_4_B0_OFFSET 0x0000a264 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MSB 0 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_LSB 0 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MASK 0x00000001 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MSB 8 +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_LSB 1 +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MASK 0x000001fe +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MSB 13 +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_LSB 9 +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MASK 0x00003e00 +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_GET(x) (((x) & 0x00003e00) >> 9) +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MSB 19 +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_LSB 14 +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MASK 0x000fc000 +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_BB_TPC_4_B0_RATE_SENT_0_MSB 24 +#define PHY_BB_TPC_4_B0_RATE_SENT_0_LSB 20 +#define PHY_BB_TPC_4_B0_RATE_SENT_0_MASK 0x01f00000 +#define PHY_BB_TPC_4_B0_RATE_SENT_0_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MSB 30 +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_LSB 25 +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MASK 0x7e000000 +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_GET(x) (((x) & 0x7e000000) >> 25) +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_SET(x) (((x) << 25) & 0x7e000000) + +/* macros for BB_analog_swap */ +#define PHY_BB_ANALOG_SWAP_ADDRESS 0x0000a268 +#define PHY_BB_ANALOG_SWAP_OFFSET 0x0000a268 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MSB 2 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB 0 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK 0x00000007 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MSB 5 +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB 3 +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK 0x00000038 +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_SET(x) (((x) << 3) & 0x00000038) +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MSB 6 +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB 6 +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK 0x00000040 +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MSB 7 +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB 7 +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK 0x00000080 +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MSB 8 +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB 8 +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK 0x00000100 +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_SET(x) (((x) << 8) & 0x00000100) + +/* macros for BB_tpc_5_b0 */ +#define PHY_BB_TPC_5_B0_ADDRESS 0x0000a26c +#define PHY_BB_TPC_5_B0_OFFSET 0x0000a26c +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MSB 3 +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_LSB 0 +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MASK 0x0000000f +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MSB 9 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_LSB 4 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MASK 0x000003f0 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_GET(x) (((x) & 0x000003f0) >> 4) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_SET(x) (((x) << 4) & 0x000003f0) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MSB 15 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_LSB 10 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MASK 0x0000fc00 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_GET(x) (((x) & 0x0000fc00) >> 10) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_SET(x) (((x) << 10) & 0x0000fc00) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MSB 21 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_LSB 16 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MASK 0x003f0000 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MSB 27 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_LSB 22 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MASK 0x0fc00000 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_GET(x) (((x) & 0x0fc00000) >> 22) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_SET(x) (((x) << 22) & 0x0fc00000) + +/* macros for BB_tpc_6_b0 */ +#define PHY_BB_TPC_6_B0_ADDRESS 0x0000a270 +#define PHY_BB_TPC_6_B0_OFFSET 0x0000a270 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MSB 5 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_LSB 0 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MASK 0x0000003f +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MSB 11 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_LSB 6 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MASK 0x00000fc0 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MSB 17 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_LSB 12 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MASK 0x0003f000 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MSB 23 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_LSB 18 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MASK 0x00fc0000 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MSB 25 +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_LSB 24 +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MASK 0x03000000 +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_SET(x) (((x) << 24) & 0x03000000) +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MSB 28 +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_LSB 26 +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MASK 0x1c000000 +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_SET(x) (((x) << 26) & 0x1c000000) + +/* macros for BB_tpc_7 */ +#define PHY_BB_TPC_7_ADDRESS 0x0000a274 +#define PHY_BB_TPC_7_OFFSET 0x0000a274 +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MSB 5 +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB 0 +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK 0x0000003f +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MSB 11 +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_LSB 6 +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MASK 0x00000fc0 +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MSB 12 +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB 12 +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK 0x00001000 +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MSB 13 +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB 13 +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK 0x00002000 +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MSB 14 +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB 14 +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK 0x00004000 +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MSB 15 +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB 15 +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK 0x00008000 +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_SET(x) (((x) << 15) & 0x00008000) + +/* macros for BB_tpc_8 */ +#define PHY_BB_TPC_8_ADDRESS 0x0000a278 +#define PHY_BB_TPC_8_OFFSET 0x0000a278 +#define PHY_BB_TPC_8_DESIRED_SCALE_0_MSB 4 +#define PHY_BB_TPC_8_DESIRED_SCALE_0_LSB 0 +#define PHY_BB_TPC_8_DESIRED_SCALE_0_MASK 0x0000001f +#define PHY_BB_TPC_8_DESIRED_SCALE_0_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_8_DESIRED_SCALE_0_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_8_DESIRED_SCALE_1_MSB 9 +#define PHY_BB_TPC_8_DESIRED_SCALE_1_LSB 5 +#define PHY_BB_TPC_8_DESIRED_SCALE_1_MASK 0x000003e0 +#define PHY_BB_TPC_8_DESIRED_SCALE_1_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_8_DESIRED_SCALE_1_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_8_DESIRED_SCALE_2_MSB 14 +#define PHY_BB_TPC_8_DESIRED_SCALE_2_LSB 10 +#define PHY_BB_TPC_8_DESIRED_SCALE_2_MASK 0x00007c00 +#define PHY_BB_TPC_8_DESIRED_SCALE_2_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_8_DESIRED_SCALE_2_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_8_DESIRED_SCALE_3_MSB 19 +#define PHY_BB_TPC_8_DESIRED_SCALE_3_LSB 15 +#define PHY_BB_TPC_8_DESIRED_SCALE_3_MASK 0x000f8000 +#define PHY_BB_TPC_8_DESIRED_SCALE_3_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_8_DESIRED_SCALE_3_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_8_DESIRED_SCALE_4_MSB 24 +#define PHY_BB_TPC_8_DESIRED_SCALE_4_LSB 20 +#define PHY_BB_TPC_8_DESIRED_SCALE_4_MASK 0x01f00000 +#define PHY_BB_TPC_8_DESIRED_SCALE_4_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_8_DESIRED_SCALE_4_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_8_DESIRED_SCALE_5_MSB 29 +#define PHY_BB_TPC_8_DESIRED_SCALE_5_LSB 25 +#define PHY_BB_TPC_8_DESIRED_SCALE_5_MASK 0x3e000000 +#define PHY_BB_TPC_8_DESIRED_SCALE_5_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_8_DESIRED_SCALE_5_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_9 */ +#define PHY_BB_TPC_9_ADDRESS 0x0000a27c +#define PHY_BB_TPC_9_OFFSET 0x0000a27c +#define PHY_BB_TPC_9_DESIRED_SCALE_6_MSB 4 +#define PHY_BB_TPC_9_DESIRED_SCALE_6_LSB 0 +#define PHY_BB_TPC_9_DESIRED_SCALE_6_MASK 0x0000001f +#define PHY_BB_TPC_9_DESIRED_SCALE_6_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_9_DESIRED_SCALE_6_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_9_DESIRED_SCALE_7_MSB 9 +#define PHY_BB_TPC_9_DESIRED_SCALE_7_LSB 5 +#define PHY_BB_TPC_9_DESIRED_SCALE_7_MASK 0x000003e0 +#define PHY_BB_TPC_9_DESIRED_SCALE_7_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_9_DESIRED_SCALE_7_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MSB 14 +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_LSB 10 +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MASK 0x00007c00 +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MSB 20 +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_LSB 20 +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MASK 0x00100000 +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MSB 26 +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_LSB 21 +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MASK 0x07e00000 +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_SET(x) (((x) << 21) & 0x07e00000) +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MSB 30 +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB 27 +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK 0x78000000 +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_SET(x) (((x) << 27) & 0x78000000) +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MSB 31 +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_LSB 31 +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MASK 0x80000000 +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_pdadc_tab_b0 */ +#define PHY_BB_PDADC_TAB_B0_ADDRESS 0x0000a280 +#define PHY_BB_PDADC_TAB_B0_OFFSET 0x0000a280 +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MSB 31 +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_LSB 0 +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MASK 0xffffffff +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_tab_b0 */ +#define PHY_BB_CL_TAB_B0_ADDRESS 0x0000a300 +#define PHY_BB_CL_TAB_B0_OFFSET 0x0000a300 +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MSB 4 +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB 0 +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK 0x0000001f +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MSB 15 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB 5 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK 0x0000ffe0 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_GET(x) (((x) & 0x0000ffe0) >> 5) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_SET(x) (((x) << 5) & 0x0000ffe0) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MSB 26 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB 16 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK 0x07ff0000 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_GET(x) (((x) & 0x07ff0000) >> 16) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_SET(x) (((x) << 16) & 0x07ff0000) +#define PHY_BB_CL_TAB_B0_BB_GAIN_MSB 30 +#define PHY_BB_CL_TAB_B0_BB_GAIN_LSB 27 +#define PHY_BB_CL_TAB_B0_BB_GAIN_MASK 0x78000000 +#define PHY_BB_CL_TAB_B0_BB_GAIN_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_BB_CL_TAB_B0_BB_GAIN_SET(x) (((x) << 27) & 0x78000000) + +/* macros for BB_cl_map_0_b0 */ +#define PHY_BB_CL_MAP_0_B0_ADDRESS 0x0000a340 +#define PHY_BB_CL_MAP_0_B0_OFFSET 0x0000a340 +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MSB 31 +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB 0 +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK 0xffffffff +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_1_b0 */ +#define PHY_BB_CL_MAP_1_B0_ADDRESS 0x0000a344 +#define PHY_BB_CL_MAP_1_B0_OFFSET 0x0000a344 +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MSB 31 +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB 0 +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK 0xffffffff +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_2_b0 */ +#define PHY_BB_CL_MAP_2_B0_ADDRESS 0x0000a348 +#define PHY_BB_CL_MAP_2_B0_OFFSET 0x0000a348 +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MSB 31 +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB 0 +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK 0xffffffff +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_3_b0 */ +#define PHY_BB_CL_MAP_3_B0_ADDRESS 0x0000a34c +#define PHY_BB_CL_MAP_3_B0_OFFSET 0x0000a34c +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MSB 31 +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB 0 +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK 0xffffffff +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_cal_ctrl */ +#define PHY_BB_CL_CAL_CTRL_ADDRESS 0x0000a358 +#define PHY_BB_CL_CAL_CTRL_OFFSET 0x0000a358 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MSB 0 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB 0 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK 0x00000001 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MSB 1 +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB 1 +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK 0x00000002 +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MSB 3 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB 2 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK 0x0000000c +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MSB 7 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB 4 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK 0x000000f0 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MSB 15 +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB 8 +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK 0x0000ff00 +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MSB 21 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB 16 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK 0x003f0000 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MSB 29 +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB 22 +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK 0x3fc00000 +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_GET(x) (((x) & 0x3fc00000) >> 22) +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_SET(x) (((x) << 22) & 0x3fc00000) +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MSB 30 +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB 30 +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK 0x40000000 +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MSB 31 +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB 31 +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK 0x80000000 +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_cl_map_pal_0_b0 */ +#define PHY_BB_CL_MAP_PAL_0_B0_ADDRESS 0x0000a35c +#define PHY_BB_CL_MAP_PAL_0_B0_OFFSET 0x0000a35c +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MSB 31 +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_LSB 0 +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_pal_1_b0 */ +#define PHY_BB_CL_MAP_PAL_1_B0_ADDRESS 0x0000a360 +#define PHY_BB_CL_MAP_PAL_1_B0_OFFSET 0x0000a360 +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MSB 31 +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_LSB 0 +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_pal_2_b0 */ +#define PHY_BB_CL_MAP_PAL_2_B0_ADDRESS 0x0000a364 +#define PHY_BB_CL_MAP_PAL_2_B0_OFFSET 0x0000a364 +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MSB 31 +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_LSB 0 +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_pal_3_b0 */ +#define PHY_BB_CL_MAP_PAL_3_B0_ADDRESS 0x0000a368 +#define PHY_BB_CL_MAP_PAL_3_B0_OFFSET 0x0000a368 +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MSB 31 +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_LSB 0 +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_rifs */ +#define PHY_BB_RIFS_ADDRESS 0x0000a388 +#define PHY_BB_RIFS_OFFSET 0x0000a388 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_MSB 25 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_LSB 25 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_MASK 0x02000000 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_RIFS_DISABLE_FCC_FIX_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MSB 26 +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB 26 +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK 0x04000000 +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MSB 27 +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_LSB 27 +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MASK 0x08000000 +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MSB 28 +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_LSB 28 +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MASK 0x10000000 +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MSB 29 +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_LSB 29 +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MASK 0x20000000 +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MSB 30 +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_LSB 30 +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MASK 0x40000000 +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_powertx_rate5 */ +#define PHY_BB_POWERTX_RATE5_ADDRESS 0x0000a38c +#define PHY_BB_POWERTX_RATE5_OFFSET 0x0000a38c +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MSB 5 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_LSB 0 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MSB 13 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_LSB 8 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MSB 21 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_LSB 16 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MSB 29 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_LSB 24 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate6 */ +#define PHY_BB_POWERTX_RATE6_ADDRESS 0x0000a390 +#define PHY_BB_POWERTX_RATE6_OFFSET 0x0000a390 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MSB 5 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_LSB 0 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MSB 13 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_LSB 8 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MSB 21 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_LSB 16 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MSB 29 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_LSB 24 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_tpc_10 */ +#define PHY_BB_TPC_10_ADDRESS 0x0000a394 +#define PHY_BB_TPC_10_OFFSET 0x0000a394 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MSB 4 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_LSB 0 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MASK 0x0000001f +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MSB 9 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_LSB 5 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MASK 0x000003e0 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MSB 14 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_LSB 10 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MASK 0x00007c00 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MSB 19 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_LSB 15 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MASK 0x000f8000 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MSB 24 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_LSB 20 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MASK 0x01f00000 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MSB 29 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_LSB 25 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MASK 0x3e000000 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_11_b0 */ +#define PHY_BB_TPC_11_B0_ADDRESS 0x0000a398 +#define PHY_BB_TPC_11_B0_OFFSET 0x0000a398 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MSB 4 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_LSB 0 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MASK 0x0000001f +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MSB 9 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_LSB 5 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MASK 0x000003e0 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MSB 23 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB 16 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK 0x00ff0000 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MSB 31 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_LSB 24 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MASK 0xff000000 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_cal_chain_mask */ +#define PHY_BB_CAL_CHAIN_MASK_ADDRESS 0x0000a39c +#define PHY_BB_CAL_CHAIN_MASK_OFFSET 0x0000a39c +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MSB 2 +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB 0 +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK 0x00000007 +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007) + +/* macros for BB_powertx_sub */ +#define PHY_BB_POWERTX_SUB_ADDRESS 0x0000a3bc +#define PHY_BB_POWERTX_SUB_OFFSET 0x0000a3bc +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MSB 5 +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB 0 +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK 0x0000003f +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_SET(x) (((x) << 0) & 0x0000003f) + +/* macros for BB_powertx_rate7 */ +#define PHY_BB_POWERTX_RATE7_ADDRESS 0x0000a3c0 +#define PHY_BB_POWERTX_RATE7_OFFSET 0x0000a3c0 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MSB 5 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_LSB 0 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MSB 13 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_LSB 8 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MSB 21 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_LSB 16 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MSB 29 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_LSB 24 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate8 */ +#define PHY_BB_POWERTX_RATE8_ADDRESS 0x0000a3c4 +#define PHY_BB_POWERTX_RATE8_OFFSET 0x0000a3c4 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MSB 5 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_LSB 0 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MSB 13 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_LSB 8 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MSB 21 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_LSB 16 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MSB 29 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_LSB 24 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate9 */ +#define PHY_BB_POWERTX_RATE9_ADDRESS 0x0000a3c8 +#define PHY_BB_POWERTX_RATE9_OFFSET 0x0000a3c8 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MSB 5 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_LSB 0 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MSB 13 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_LSB 8 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MSB 21 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_LSB 16 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MSB 29 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_LSB 24 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate10 */ +#define PHY_BB_POWERTX_RATE10_ADDRESS 0x0000a3cc +#define PHY_BB_POWERTX_RATE10_OFFSET 0x0000a3cc +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MSB 5 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_LSB 0 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MSB 13 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_LSB 8 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MSB 21 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_LSB 16 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MSB 29 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_LSB 24 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate11 */ +#define PHY_BB_POWERTX_RATE11_ADDRESS 0x0000a3d0 +#define PHY_BB_POWERTX_RATE11_OFFSET 0x0000a3d0 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MSB 5 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_LSB 0 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MSB 13 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_LSB 8 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MSB 21 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_LSB 16 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MSB 29 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_LSB 24 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate12 */ +#define PHY_BB_POWERTX_RATE12_ADDRESS 0x0000a3d4 +#define PHY_BB_POWERTX_RATE12_OFFSET 0x0000a3d4 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MSB 5 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_LSB 0 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MSB 13 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_LSB 8 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MSB 21 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_LSB 16 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MSB 29 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_LSB 24 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_force_analog */ +#define PHY_BB_FORCE_ANALOG_ADDRESS 0x0000a3d8 +#define PHY_BB_FORCE_ANALOG_OFFSET 0x0000a3d8 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MSB 0 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB 0 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK 0x00000001 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MSB 3 +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB 1 +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK 0x0000000e +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MSB 4 +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_LSB 4 +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MASK 0x00000010 +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MSB 7 +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_LSB 5 +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MASK 0x000000e0 +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_SET(x) (((x) << 5) & 0x000000e0) + +/* macros for BB_tpc_12 */ +#define PHY_BB_TPC_12_ADDRESS 0x0000a3dc +#define PHY_BB_TPC_12_OFFSET 0x0000a3dc +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MSB 4 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_LSB 0 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MASK 0x0000001f +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MSB 9 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_LSB 5 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MASK 0x000003e0 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MSB 14 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_LSB 10 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MASK 0x00007c00 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MSB 19 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_LSB 15 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MASK 0x000f8000 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MSB 24 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_LSB 20 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MASK 0x01f00000 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MSB 29 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_LSB 25 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MASK 0x3e000000 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_13 */ +#define PHY_BB_TPC_13_ADDRESS 0x0000a3e0 +#define PHY_BB_TPC_13_OFFSET 0x0000a3e0 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MSB 4 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_LSB 0 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MASK 0x0000001f +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MSB 9 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_LSB 5 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MASK 0x000003e0 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_SET(x) (((x) << 5) & 0x000003e0) + +/* macros for BB_tpc_14 */ +#define PHY_BB_TPC_14_ADDRESS 0x0000a3e4 +#define PHY_BB_TPC_14_OFFSET 0x0000a3e4 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MSB 4 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_LSB 0 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MASK 0x0000001f +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MSB 9 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_LSB 5 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MASK 0x000003e0 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MSB 14 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_LSB 10 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MASK 0x00007c00 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MSB 19 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_LSB 15 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MASK 0x000f8000 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MSB 24 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_LSB 20 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MASK 0x01f00000 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MSB 29 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_LSB 25 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MASK 0x3e000000 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_15 */ +#define PHY_BB_TPC_15_ADDRESS 0x0000a3e8 +#define PHY_BB_TPC_15_OFFSET 0x0000a3e8 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MSB 4 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_LSB 0 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MASK 0x0000001f +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MSB 9 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_LSB 5 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MASK 0x000003e0 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MSB 14 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_LSB 10 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MASK 0x00007c00 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MSB 19 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_LSB 15 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MASK 0x000f8000 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MSB 24 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_LSB 20 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MASK 0x01f00000 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MSB 29 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_LSB 25 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MASK 0x3e000000 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_16 */ +#define PHY_BB_TPC_16_ADDRESS 0x0000a3ec +#define PHY_BB_TPC_16_OFFSET 0x0000a3ec +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MSB 13 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_LSB 8 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MASK 0x00003f00 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MSB 21 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_LSB 16 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MASK 0x003f0000 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MSB 29 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_LSB 24 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MASK 0x3f000000 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_tpc_17 */ +#define PHY_BB_TPC_17_ADDRESS 0x0000a3f0 +#define PHY_BB_TPC_17_OFFSET 0x0000a3f0 +#define PHY_BB_TPC_17_ENABLE_PAL_MSB 0 +#define PHY_BB_TPC_17_ENABLE_PAL_LSB 0 +#define PHY_BB_TPC_17_ENABLE_PAL_MASK 0x00000001 +#define PHY_BB_TPC_17_ENABLE_PAL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_17_ENABLE_PAL_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MSB 1 +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_LSB 1 +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MASK 0x00000002 +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MSB 2 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_LSB 2 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MASK 0x00000004 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MSB 3 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_LSB 3 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MASK 0x00000008 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MSB 9 +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_LSB 4 +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MASK 0x000003f0 +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_GET(x) (((x) & 0x000003f0) >> 4) +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_SET(x) (((x) << 4) & 0x000003f0) +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MSB 10 +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_LSB 10 +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MASK 0x00000400 +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MSB 16 +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_LSB 11 +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MASK 0x0001f800 +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_SET(x) (((x) << 11) & 0x0001f800) + +/* macros for BB_tpc_18 */ +#define PHY_BB_TPC_18_ADDRESS 0x0000a3f4 +#define PHY_BB_TPC_18_OFFSET 0x0000a3f4 +#define PHY_BB_TPC_18_THERM_CAL_VALUE_MSB 7 +#define PHY_BB_TPC_18_THERM_CAL_VALUE_LSB 0 +#define PHY_BB_TPC_18_THERM_CAL_VALUE_MASK 0x000000ff +#define PHY_BB_TPC_18_THERM_CAL_VALUE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_18_THERM_CAL_VALUE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MSB 15 +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_LSB 8 +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MASK 0x0000ff00 +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_18_USE_LEGACY_TPC_MSB 16 +#define PHY_BB_TPC_18_USE_LEGACY_TPC_LSB 16 +#define PHY_BB_TPC_18_USE_LEGACY_TPC_MASK 0x00010000 +#define PHY_BB_TPC_18_USE_LEGACY_TPC_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_TPC_18_USE_LEGACY_TPC_SET(x) (((x) << 16) & 0x00010000) + +/* macros for BB_tpc_19 */ +#define PHY_BB_TPC_19_ADDRESS 0x0000a3f8 +#define PHY_BB_TPC_19_OFFSET 0x0000a3f8 +#define PHY_BB_TPC_19_ALPHA_THERM_MSB 7 +#define PHY_BB_TPC_19_ALPHA_THERM_LSB 0 +#define PHY_BB_TPC_19_ALPHA_THERM_MASK 0x000000ff +#define PHY_BB_TPC_19_ALPHA_THERM_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_19_ALPHA_THERM_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MSB 15 +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_LSB 8 +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MASK 0x0000ff00 +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_19_ALPHA_VOLT_MSB 20 +#define PHY_BB_TPC_19_ALPHA_VOLT_LSB 16 +#define PHY_BB_TPC_19_ALPHA_VOLT_MASK 0x001f0000 +#define PHY_BB_TPC_19_ALPHA_VOLT_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_TPC_19_ALPHA_VOLT_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MSB 25 +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_LSB 21 +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MASK 0x03e00000 +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_SET(x) (((x) << 21) & 0x03e00000) + +/* macros for BB_tpc_20 */ +#define PHY_BB_TPC_20_ADDRESS 0x0000a3fc +#define PHY_BB_TPC_20_OFFSET 0x0000a3fc +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MSB 0 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_LSB 0 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MASK 0x00000001 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MSB 1 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_LSB 1 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MASK 0x00000002 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MSB 2 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_LSB 2 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MASK 0x00000004 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MSB 3 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_LSB 3 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MASK 0x00000008 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MSB 4 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_LSB 4 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MASK 0x00000010 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MSB 5 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_LSB 5 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MASK 0x00000020 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MSB 6 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_LSB 6 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MASK 0x00000040 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MSB 7 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_LSB 7 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MASK 0x00000080 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MSB 8 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_LSB 8 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MASK 0x00000100 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MSB 9 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_LSB 9 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MASK 0x00000200 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MSB 10 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_LSB 10 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MASK 0x00000400 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MSB 11 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_LSB 11 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MASK 0x00000800 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MSB 12 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_LSB 12 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MASK 0x00001000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MSB 13 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_LSB 13 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MASK 0x00002000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MSB 14 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_LSB 14 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MASK 0x00004000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MSB 15 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_LSB 15 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MASK 0x00008000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MSB 16 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_LSB 16 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MASK 0x00010000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MSB 17 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_LSB 17 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MASK 0x00020000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MSB 18 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_LSB 18 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MASK 0x00040000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MSB 19 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_LSB 19 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MASK 0x00080000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MSB 20 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_LSB 20 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MASK 0x00100000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MSB 21 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_LSB 21 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MASK 0x00200000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MSB 22 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_LSB 22 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MASK 0x00400000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MSB 23 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_LSB 23 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MASK 0x00800000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_SET(x) (((x) << 23) & 0x00800000) + +/* macros for BB_tx_gain_tab_1 */ +#define PHY_BB_TX_GAIN_TAB_1_ADDRESS 0x0000a400 +#define PHY_BB_TX_GAIN_TAB_1_OFFSET 0x0000a400 +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MSB 31 +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_LSB 0 +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_2 */ +#define PHY_BB_TX_GAIN_TAB_2_ADDRESS 0x0000a404 +#define PHY_BB_TX_GAIN_TAB_2_OFFSET 0x0000a404 +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MSB 31 +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_LSB 0 +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_3 */ +#define PHY_BB_TX_GAIN_TAB_3_ADDRESS 0x0000a408 +#define PHY_BB_TX_GAIN_TAB_3_OFFSET 0x0000a408 +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MSB 31 +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_LSB 0 +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_4 */ +#define PHY_BB_TX_GAIN_TAB_4_ADDRESS 0x0000a40c +#define PHY_BB_TX_GAIN_TAB_4_OFFSET 0x0000a40c +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MSB 31 +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_LSB 0 +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_5 */ +#define PHY_BB_TX_GAIN_TAB_5_ADDRESS 0x0000a410 +#define PHY_BB_TX_GAIN_TAB_5_OFFSET 0x0000a410 +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MSB 31 +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_LSB 0 +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_6 */ +#define PHY_BB_TX_GAIN_TAB_6_ADDRESS 0x0000a414 +#define PHY_BB_TX_GAIN_TAB_6_OFFSET 0x0000a414 +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MSB 31 +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_LSB 0 +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_7 */ +#define PHY_BB_TX_GAIN_TAB_7_ADDRESS 0x0000a418 +#define PHY_BB_TX_GAIN_TAB_7_OFFSET 0x0000a418 +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MSB 31 +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_LSB 0 +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_8 */ +#define PHY_BB_TX_GAIN_TAB_8_ADDRESS 0x0000a41c +#define PHY_BB_TX_GAIN_TAB_8_OFFSET 0x0000a41c +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MSB 31 +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_LSB 0 +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_9 */ +#define PHY_BB_TX_GAIN_TAB_9_ADDRESS 0x0000a420 +#define PHY_BB_TX_GAIN_TAB_9_OFFSET 0x0000a420 +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MSB 31 +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_LSB 0 +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_10 */ +#define PHY_BB_TX_GAIN_TAB_10_ADDRESS 0x0000a424 +#define PHY_BB_TX_GAIN_TAB_10_OFFSET 0x0000a424 +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MSB 31 +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_LSB 0 +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_11 */ +#define PHY_BB_TX_GAIN_TAB_11_ADDRESS 0x0000a428 +#define PHY_BB_TX_GAIN_TAB_11_OFFSET 0x0000a428 +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MSB 31 +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_LSB 0 +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_12 */ +#define PHY_BB_TX_GAIN_TAB_12_ADDRESS 0x0000a42c +#define PHY_BB_TX_GAIN_TAB_12_OFFSET 0x0000a42c +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MSB 31 +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_LSB 0 +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_13 */ +#define PHY_BB_TX_GAIN_TAB_13_ADDRESS 0x0000a430 +#define PHY_BB_TX_GAIN_TAB_13_OFFSET 0x0000a430 +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MSB 31 +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_LSB 0 +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_14 */ +#define PHY_BB_TX_GAIN_TAB_14_ADDRESS 0x0000a434 +#define PHY_BB_TX_GAIN_TAB_14_OFFSET 0x0000a434 +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MSB 31 +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_LSB 0 +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_15 */ +#define PHY_BB_TX_GAIN_TAB_15_ADDRESS 0x0000a438 +#define PHY_BB_TX_GAIN_TAB_15_OFFSET 0x0000a438 +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MSB 31 +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_LSB 0 +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_16 */ +#define PHY_BB_TX_GAIN_TAB_16_ADDRESS 0x0000a43c +#define PHY_BB_TX_GAIN_TAB_16_OFFSET 0x0000a43c +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MSB 31 +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_LSB 0 +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_17 */ +#define PHY_BB_TX_GAIN_TAB_17_ADDRESS 0x0000a440 +#define PHY_BB_TX_GAIN_TAB_17_OFFSET 0x0000a440 +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MSB 31 +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_LSB 0 +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_18 */ +#define PHY_BB_TX_GAIN_TAB_18_ADDRESS 0x0000a444 +#define PHY_BB_TX_GAIN_TAB_18_OFFSET 0x0000a444 +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MSB 31 +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_LSB 0 +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_19 */ +#define PHY_BB_TX_GAIN_TAB_19_ADDRESS 0x0000a448 +#define PHY_BB_TX_GAIN_TAB_19_OFFSET 0x0000a448 +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MSB 31 +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_LSB 0 +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_20 */ +#define PHY_BB_TX_GAIN_TAB_20_ADDRESS 0x0000a44c +#define PHY_BB_TX_GAIN_TAB_20_OFFSET 0x0000a44c +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MSB 31 +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_LSB 0 +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_21 */ +#define PHY_BB_TX_GAIN_TAB_21_ADDRESS 0x0000a450 +#define PHY_BB_TX_GAIN_TAB_21_OFFSET 0x0000a450 +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MSB 31 +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_LSB 0 +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_22 */ +#define PHY_BB_TX_GAIN_TAB_22_ADDRESS 0x0000a454 +#define PHY_BB_TX_GAIN_TAB_22_OFFSET 0x0000a454 +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MSB 31 +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_LSB 0 +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_23 */ +#define PHY_BB_TX_GAIN_TAB_23_ADDRESS 0x0000a458 +#define PHY_BB_TX_GAIN_TAB_23_OFFSET 0x0000a458 +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MSB 31 +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_LSB 0 +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_24 */ +#define PHY_BB_TX_GAIN_TAB_24_ADDRESS 0x0000a45c +#define PHY_BB_TX_GAIN_TAB_24_OFFSET 0x0000a45c +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MSB 31 +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_LSB 0 +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_25 */ +#define PHY_BB_TX_GAIN_TAB_25_ADDRESS 0x0000a460 +#define PHY_BB_TX_GAIN_TAB_25_OFFSET 0x0000a460 +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MSB 31 +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_LSB 0 +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_26 */ +#define PHY_BB_TX_GAIN_TAB_26_ADDRESS 0x0000a464 +#define PHY_BB_TX_GAIN_TAB_26_OFFSET 0x0000a464 +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MSB 31 +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_LSB 0 +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_27 */ +#define PHY_BB_TX_GAIN_TAB_27_ADDRESS 0x0000a468 +#define PHY_BB_TX_GAIN_TAB_27_OFFSET 0x0000a468 +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MSB 31 +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_LSB 0 +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_28 */ +#define PHY_BB_TX_GAIN_TAB_28_ADDRESS 0x0000a46c +#define PHY_BB_TX_GAIN_TAB_28_OFFSET 0x0000a46c +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MSB 31 +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_LSB 0 +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_29 */ +#define PHY_BB_TX_GAIN_TAB_29_ADDRESS 0x0000a470 +#define PHY_BB_TX_GAIN_TAB_29_OFFSET 0x0000a470 +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MSB 31 +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_LSB 0 +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_30 */ +#define PHY_BB_TX_GAIN_TAB_30_ADDRESS 0x0000a474 +#define PHY_BB_TX_GAIN_TAB_30_OFFSET 0x0000a474 +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MSB 31 +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_LSB 0 +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_31 */ +#define PHY_BB_TX_GAIN_TAB_31_ADDRESS 0x0000a478 +#define PHY_BB_TX_GAIN_TAB_31_OFFSET 0x0000a478 +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MSB 31 +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_LSB 0 +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_32 */ +#define PHY_BB_TX_GAIN_TAB_32_ADDRESS 0x0000a47c +#define PHY_BB_TX_GAIN_TAB_32_OFFSET 0x0000a47c +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MSB 31 +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_LSB 0 +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_1 */ +#define PHY_BB_TX_GAIN_TAB_PAL_1_ADDRESS 0x0000a480 +#define PHY_BB_TX_GAIN_TAB_PAL_1_OFFSET 0x0000a480 +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_2 */ +#define PHY_BB_TX_GAIN_TAB_PAL_2_ADDRESS 0x0000a484 +#define PHY_BB_TX_GAIN_TAB_PAL_2_OFFSET 0x0000a484 +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_3 */ +#define PHY_BB_TX_GAIN_TAB_PAL_3_ADDRESS 0x0000a488 +#define PHY_BB_TX_GAIN_TAB_PAL_3_OFFSET 0x0000a488 +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_4 */ +#define PHY_BB_TX_GAIN_TAB_PAL_4_ADDRESS 0x0000a48c +#define PHY_BB_TX_GAIN_TAB_PAL_4_OFFSET 0x0000a48c +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_5 */ +#define PHY_BB_TX_GAIN_TAB_PAL_5_ADDRESS 0x0000a490 +#define PHY_BB_TX_GAIN_TAB_PAL_5_OFFSET 0x0000a490 +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_6 */ +#define PHY_BB_TX_GAIN_TAB_PAL_6_ADDRESS 0x0000a494 +#define PHY_BB_TX_GAIN_TAB_PAL_6_OFFSET 0x0000a494 +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_7 */ +#define PHY_BB_TX_GAIN_TAB_PAL_7_ADDRESS 0x0000a498 +#define PHY_BB_TX_GAIN_TAB_PAL_7_OFFSET 0x0000a498 +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_8 */ +#define PHY_BB_TX_GAIN_TAB_PAL_8_ADDRESS 0x0000a49c +#define PHY_BB_TX_GAIN_TAB_PAL_8_OFFSET 0x0000a49c +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_9 */ +#define PHY_BB_TX_GAIN_TAB_PAL_9_ADDRESS 0x0000a4a0 +#define PHY_BB_TX_GAIN_TAB_PAL_9_OFFSET 0x0000a4a0 +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_10 */ +#define PHY_BB_TX_GAIN_TAB_PAL_10_ADDRESS 0x0000a4a4 +#define PHY_BB_TX_GAIN_TAB_PAL_10_OFFSET 0x0000a4a4 +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_11 */ +#define PHY_BB_TX_GAIN_TAB_PAL_11_ADDRESS 0x0000a4a8 +#define PHY_BB_TX_GAIN_TAB_PAL_11_OFFSET 0x0000a4a8 +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_12 */ +#define PHY_BB_TX_GAIN_TAB_PAL_12_ADDRESS 0x0000a4ac +#define PHY_BB_TX_GAIN_TAB_PAL_12_OFFSET 0x0000a4ac +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_13 */ +#define PHY_BB_TX_GAIN_TAB_PAL_13_ADDRESS 0x0000a4b0 +#define PHY_BB_TX_GAIN_TAB_PAL_13_OFFSET 0x0000a4b0 +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_14 */ +#define PHY_BB_TX_GAIN_TAB_PAL_14_ADDRESS 0x0000a4b4 +#define PHY_BB_TX_GAIN_TAB_PAL_14_OFFSET 0x0000a4b4 +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_15 */ +#define PHY_BB_TX_GAIN_TAB_PAL_15_ADDRESS 0x0000a4b8 +#define PHY_BB_TX_GAIN_TAB_PAL_15_OFFSET 0x0000a4b8 +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_16 */ +#define PHY_BB_TX_GAIN_TAB_PAL_16_ADDRESS 0x0000a4bc +#define PHY_BB_TX_GAIN_TAB_PAL_16_OFFSET 0x0000a4bc +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_17 */ +#define PHY_BB_TX_GAIN_TAB_PAL_17_ADDRESS 0x0000a4c0 +#define PHY_BB_TX_GAIN_TAB_PAL_17_OFFSET 0x0000a4c0 +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_18 */ +#define PHY_BB_TX_GAIN_TAB_PAL_18_ADDRESS 0x0000a4c4 +#define PHY_BB_TX_GAIN_TAB_PAL_18_OFFSET 0x0000a4c4 +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_19 */ +#define PHY_BB_TX_GAIN_TAB_PAL_19_ADDRESS 0x0000a4c8 +#define PHY_BB_TX_GAIN_TAB_PAL_19_OFFSET 0x0000a4c8 +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_20 */ +#define PHY_BB_TX_GAIN_TAB_PAL_20_ADDRESS 0x0000a4cc +#define PHY_BB_TX_GAIN_TAB_PAL_20_OFFSET 0x0000a4cc +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_21 */ +#define PHY_BB_TX_GAIN_TAB_PAL_21_ADDRESS 0x0000a4d0 +#define PHY_BB_TX_GAIN_TAB_PAL_21_OFFSET 0x0000a4d0 +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_22 */ +#define PHY_BB_TX_GAIN_TAB_PAL_22_ADDRESS 0x0000a4d4 +#define PHY_BB_TX_GAIN_TAB_PAL_22_OFFSET 0x0000a4d4 +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_23 */ +#define PHY_BB_TX_GAIN_TAB_PAL_23_ADDRESS 0x0000a4d8 +#define PHY_BB_TX_GAIN_TAB_PAL_23_OFFSET 0x0000a4d8 +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_24 */ +#define PHY_BB_TX_GAIN_TAB_PAL_24_ADDRESS 0x0000a4dc +#define PHY_BB_TX_GAIN_TAB_PAL_24_OFFSET 0x0000a4dc +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_25 */ +#define PHY_BB_TX_GAIN_TAB_PAL_25_ADDRESS 0x0000a4e0 +#define PHY_BB_TX_GAIN_TAB_PAL_25_OFFSET 0x0000a4e0 +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_26 */ +#define PHY_BB_TX_GAIN_TAB_PAL_26_ADDRESS 0x0000a4e4 +#define PHY_BB_TX_GAIN_TAB_PAL_26_OFFSET 0x0000a4e4 +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_27 */ +#define PHY_BB_TX_GAIN_TAB_PAL_27_ADDRESS 0x0000a4e8 +#define PHY_BB_TX_GAIN_TAB_PAL_27_OFFSET 0x0000a4e8 +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_28 */ +#define PHY_BB_TX_GAIN_TAB_PAL_28_ADDRESS 0x0000a4ec +#define PHY_BB_TX_GAIN_TAB_PAL_28_OFFSET 0x0000a4ec +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_29 */ +#define PHY_BB_TX_GAIN_TAB_PAL_29_ADDRESS 0x0000a4f0 +#define PHY_BB_TX_GAIN_TAB_PAL_29_OFFSET 0x0000a4f0 +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_30 */ +#define PHY_BB_TX_GAIN_TAB_PAL_30_ADDRESS 0x0000a4f4 +#define PHY_BB_TX_GAIN_TAB_PAL_30_OFFSET 0x0000a4f4 +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_31 */ +#define PHY_BB_TX_GAIN_TAB_PAL_31_ADDRESS 0x0000a4f8 +#define PHY_BB_TX_GAIN_TAB_PAL_31_OFFSET 0x0000a4f8 +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_32 */ +#define PHY_BB_TX_GAIN_TAB_PAL_32_ADDRESS 0x0000a4fc +#define PHY_BB_TX_GAIN_TAB_PAL_32_OFFSET 0x0000a4fc +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_caltx_gain_set_0 */ +#define PHY_BB_CALTX_GAIN_SET_0_ADDRESS 0x0000a518 +#define PHY_BB_CALTX_GAIN_SET_0_OFFSET 0x0000a518 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_2 */ +#define PHY_BB_CALTX_GAIN_SET_2_ADDRESS 0x0000a51c +#define PHY_BB_CALTX_GAIN_SET_2_OFFSET 0x0000a51c +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_4 */ +#define PHY_BB_CALTX_GAIN_SET_4_ADDRESS 0x0000a520 +#define PHY_BB_CALTX_GAIN_SET_4_OFFSET 0x0000a520 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_6 */ +#define PHY_BB_CALTX_GAIN_SET_6_ADDRESS 0x0000a524 +#define PHY_BB_CALTX_GAIN_SET_6_OFFSET 0x0000a524 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_8 */ +#define PHY_BB_CALTX_GAIN_SET_8_ADDRESS 0x0000a528 +#define PHY_BB_CALTX_GAIN_SET_8_OFFSET 0x0000a528 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_10 */ +#define PHY_BB_CALTX_GAIN_SET_10_ADDRESS 0x0000a52c +#define PHY_BB_CALTX_GAIN_SET_10_OFFSET 0x0000a52c +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_12 */ +#define PHY_BB_CALTX_GAIN_SET_12_ADDRESS 0x0000a530 +#define PHY_BB_CALTX_GAIN_SET_12_OFFSET 0x0000a530 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_14 */ +#define PHY_BB_CALTX_GAIN_SET_14_ADDRESS 0x0000a534 +#define PHY_BB_CALTX_GAIN_SET_14_OFFSET 0x0000a534 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_16 */ +#define PHY_BB_CALTX_GAIN_SET_16_ADDRESS 0x0000a538 +#define PHY_BB_CALTX_GAIN_SET_16_OFFSET 0x0000a538 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_18 */ +#define PHY_BB_CALTX_GAIN_SET_18_ADDRESS 0x0000a53c +#define PHY_BB_CALTX_GAIN_SET_18_OFFSET 0x0000a53c +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_20 */ +#define PHY_BB_CALTX_GAIN_SET_20_ADDRESS 0x0000a540 +#define PHY_BB_CALTX_GAIN_SET_20_OFFSET 0x0000a540 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_22 */ +#define PHY_BB_CALTX_GAIN_SET_22_ADDRESS 0x0000a544 +#define PHY_BB_CALTX_GAIN_SET_22_OFFSET 0x0000a544 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_24 */ +#define PHY_BB_CALTX_GAIN_SET_24_ADDRESS 0x0000a548 +#define PHY_BB_CALTX_GAIN_SET_24_OFFSET 0x0000a548 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_26 */ +#define PHY_BB_CALTX_GAIN_SET_26_ADDRESS 0x0000a54c +#define PHY_BB_CALTX_GAIN_SET_26_OFFSET 0x0000a54c +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_28 */ +#define PHY_BB_CALTX_GAIN_SET_28_ADDRESS 0x0000a550 +#define PHY_BB_CALTX_GAIN_SET_28_OFFSET 0x0000a550 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_30 */ +#define PHY_BB_CALTX_GAIN_SET_30_ADDRESS 0x0000a554 +#define PHY_BB_CALTX_GAIN_SET_30_OFFSET 0x0000a554 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiqcal_meas_b0 */ +#define PHY_BB_TXIQCAL_MEAS_B0_ADDRESS 0x0000a558 +#define PHY_BB_TXIQCAL_MEAS_B0_OFFSET 0x0000a558 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MSB 11 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_LSB 0 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MASK 0x00000fff +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MSB 23 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_LSB 12 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MASK 0x00fff000 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_GET(x) (((x) & 0x00fff000) >> 12) + +/* macros for BB_txiqcal_start */ +#define PHY_BB_TXIQCAL_START_ADDRESS 0x0000a6d8 +#define PHY_BB_TXIQCAL_START_OFFSET 0x0000a6d8 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MSB 0 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_LSB 0 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MASK 0x00000001 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_txiqcal_control_0 */ +#define PHY_BB_TXIQCAL_CONTROL_0_ADDRESS 0x0000a6dc +#define PHY_BB_TXIQCAL_CONTROL_0_OFFSET 0x0000a6dc +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MSB 0 +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MASK 0x00000001 +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB 6 +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB 1 +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK 0x0000007e +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_GET(x) (((x) & 0x0000007e) >> 1) +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_SET(x) (((x) << 1) & 0x0000007e) +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MSB 12 +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB 7 +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK 0x00001f80 +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_GET(x) (((x) & 0x00001f80) >> 7) +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_SET(x) (((x) << 7) & 0x00001f80) +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MSB 18 +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB 13 +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK 0x0007e000 +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_GET(x) (((x) & 0x0007e000) >> 13) +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_SET(x) (((x) << 13) & 0x0007e000) +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MSB 22 +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB 19 +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK 0x00780000 +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_SET(x) (((x) << 19) & 0x00780000) +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MSB 29 +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB 23 +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK 0x3f800000 +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_SET(x) (((x) << 23) & 0x3f800000) + +/* macros for BB_txiqcal_control_1 */ +#define PHY_BB_TXIQCAL_CONTROL_1_ADDRESS 0x0000a6e0 +#define PHY_BB_TXIQCAL_CONTROL_1_OFFSET 0x0000a6e0 +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MSB 5 +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK 0x0000003f +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MSB 11 +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB 6 +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK 0x00000fc0 +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MSB 17 +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB 12 +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK 0x0003f000 +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MSB 24 +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB 18 +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK 0x01fc0000 +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_GET(x) (((x) & 0x01fc0000) >> 18) +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_SET(x) (((x) << 18) & 0x01fc0000) + +/* macros for BB_txiqcal_control_2 */ +#define PHY_BB_TXIQCAL_CONTROL_2_ADDRESS 0x0000a6e4 +#define PHY_BB_TXIQCAL_CONTROL_2_OFFSET 0x0000a6e4 +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MSB 3 +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MASK 0x0000000f +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MSB 8 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB 4 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK 0x000001f0 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_GET(x) (((x) & 0x000001f0) >> 4) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_SET(x) (((x) << 4) & 0x000001f0) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MSB 13 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB 9 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK 0x00003e00 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_GET(x) (((x) & 0x00003e00) >> 9) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_SET(x) (((x) << 9) & 0x00003e00) + +/* macros for BB_txiqcal_control_3 */ +#define PHY_BB_TXIQCAL_CONTROL_3_ADDRESS 0x0000a6e8 +#define PHY_BB_TXIQCAL_CONTROL_3_OFFSET 0x0000a6e8 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MSB 5 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK 0x0000003f +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MSB 11 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB 6 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK 0x00000fc0 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MSB 21 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB 12 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK 0x003ff000 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MSB 23 +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB 22 +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK 0x00c00000 +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MSB 24 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_LSB 24 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MASK 0x01000000 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MSB 26 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_LSB 25 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MASK 0x06000000 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_SET(x) (((x) << 25) & 0x06000000) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MSB 28 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_LSB 27 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MASK 0x18000000 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_GET(x) (((x) & 0x18000000) >> 27) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_SET(x) (((x) << 27) & 0x18000000) +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MSB 30 +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB 29 +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK 0x60000000 +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_SET(x) (((x) << 29) & 0x60000000) +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MSB 31 +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB 31 +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK 0x80000000 +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_txiq_corr_coeff_01_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_ADDRESS 0x0000a6ec +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_OFFSET 0x0000a6ec +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_23_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_ADDRESS 0x0000a6f0 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_OFFSET 0x0000a6f0 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_45_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_ADDRESS 0x0000a6f4 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_OFFSET 0x0000a6f4 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_67_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_ADDRESS 0x0000a6f8 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_OFFSET 0x0000a6f8 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_89_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_ADDRESS 0x0000a6fc +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_OFFSET 0x0000a6fc +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_ab_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_ADDRESS 0x0000a700 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_OFFSET 0x0000a700 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_cd_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_ADDRESS 0x0000a704 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_OFFSET 0x0000a704 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_ef_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_ADDRESS 0x0000a708 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_OFFSET 0x0000a708 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_cal_rxbb_gain_tbl_0 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_ADDRESS 0x0000a70c +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_OFFSET 0x0000a70c +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_4 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_ADDRESS 0x0000a710 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_OFFSET 0x0000a710 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_8 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_ADDRESS 0x0000a714 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_OFFSET 0x0000a714 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_12 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_ADDRESS 0x0000a718 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_OFFSET 0x0000a718 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_16 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_ADDRESS 0x0000a71c +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_OFFSET 0x0000a71c +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_20 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_ADDRESS 0x0000a720 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_OFFSET 0x0000a720 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_24 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_ADDRESS 0x0000a724 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_OFFSET 0x0000a724 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_SET(x) (((x) << 0) & 0x0000003f) + +/* macros for BB_txiqcal_status_b0 */ +#define PHY_BB_TXIQCAL_STATUS_B0_ADDRESS 0x0000a728 +#define PHY_BB_TXIQCAL_STATUS_B0_OFFSET 0x0000a728 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MSB 0 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB 0 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK 0x00000001 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MSB 5 +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB 1 +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK 0x0000003e +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MSB 11 +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB 6 +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK 0x00000fc0 +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MSB 17 +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB 12 +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK 0x0003f000 +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MSB 24 +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB 18 +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK 0x01fc0000 +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_GET(x) (((x) & 0x01fc0000) >> 18) + +/* macros for BB_paprd_trainer_cntl1 */ +#define PHY_BB_PAPRD_TRAINER_CNTL1_ADDRESS 0x0000a72c +#define PHY_BB_PAPRD_TRAINER_CNTL1_OFFSET 0x0000a72c +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK 0x00000001 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MSB 7 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB 1 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK 0x000000fe +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MSB 8 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB 8 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK 0x00000100 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MSB 9 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB 9 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK 0x00000200 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MSB 10 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB 10 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK 0x00000400 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_LSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MASK 0x00000800 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MSB 18 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_LSB 12 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MASK 0x0007f000 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_GET(x) (((x) & 0x0007f000) >> 12) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_SET(x) (((x) << 12) & 0x0007f000) + +/* macros for BB_paprd_trainer_cntl2 */ +#define PHY_BB_PAPRD_TRAINER_CNTL2_ADDRESS 0x0000a730 +#define PHY_BB_PAPRD_TRAINER_CNTL2_OFFSET 0x0000a730 +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MSB 31 +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK 0xffffffff +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_paprd_trainer_cntl3 */ +#define PHY_BB_PAPRD_TRAINER_CNTL3_ADDRESS 0x0000a734 +#define PHY_BB_PAPRD_TRAINER_CNTL3_OFFSET 0x0000a734 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MSB 5 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MASK 0x0000003f +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB 6 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK 0x00000fc0 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MSB 16 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB 12 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK 0x0001f000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MSB 19 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB 17 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK 0x000e0000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MSB 23 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB 20 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK 0x00f00000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MSB 27 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB 24 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK 0x0f000000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MSB 28 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB 28 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK 0x10000000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_SET(x) (((x) << 28) & 0x10000000) + +/* macros for BB_paprd_trainer_cntl4 */ +#define PHY_BB_PAPRD_TRAINER_CNTL4_ADDRESS 0x0000a738 +#define PHY_BB_PAPRD_TRAINER_CNTL4_OFFSET 0x0000a738 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK 0x00000fff +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MSB 15 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB 12 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK 0x0000f000 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MSB 25 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB 16 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK 0x03ff0000 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for BB_paprd_trainer_stat1 */ +#define PHY_BB_PAPRD_TRAINER_STAT1_ADDRESS 0x0000a73c +#define PHY_BB_PAPRD_TRAINER_STAT1_OFFSET 0x0000a73c +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK 0x00000001 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MSB 1 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB 1 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK 0x00000002 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MSB 2 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB 2 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK 0x00000004 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MSB 3 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB 3 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK 0x00000008 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MSB 8 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB 4 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK 0x000001f0 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_GET(x) (((x) & 0x000001f0) >> 4) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MSB 16 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB 9 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK 0x0001fe00 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_GET(x) (((x) & 0x0001fe00) >> 9) + +/* macros for BB_paprd_trainer_stat2 */ +#define PHY_BB_PAPRD_TRAINER_STAT2_ADDRESS 0x0000a740 +#define PHY_BB_PAPRD_TRAINER_STAT2_OFFSET 0x0000a740 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MSB 15 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK 0x0000ffff +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_GET(x) (((x) & 0x0000ffff) >> 0) +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MSB 20 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB 16 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK 0x001f0000 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MSB 22 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB 21 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK 0x00600000 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_GET(x) (((x) & 0x00600000) >> 21) + +/* macros for BB_paprd_trainer_stat3 */ +#define PHY_BB_PAPRD_TRAINER_STAT3_ADDRESS 0x0000a744 +#define PHY_BB_PAPRD_TRAINER_STAT3_OFFSET 0x0000a744 +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MSB 19 +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK 0x000fffff +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_GET(x) (((x) & 0x000fffff) >> 0) + +/* macros for BB_fcal_1 */ +#define PHY_BB_FCAL_1_ADDRESS 0x0000a7d8 +#define PHY_BB_FCAL_1_OFFSET 0x0000a7d8 +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MSB 9 +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB 0 +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK 0x000003ff +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MSB 19 +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB 10 +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK 0x000ffc00 +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_GET(x) (((x) & 0x000ffc00) >> 10) +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_SET(x) (((x) << 10) & 0x000ffc00) +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MSB 24 +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB 20 +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK 0x01f00000 +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MSB 29 +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB 25 +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK 0x3e000000 +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_fcal_2_b0 */ +#define PHY_BB_FCAL_2_B0_ADDRESS 0x0000a7dc +#define PHY_BB_FCAL_2_B0_OFFSET 0x0000a7dc +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MSB 2 +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB 0 +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK 0x00000007 +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MSB 7 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB 3 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK 0x000000f8 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_GET(x) (((x) & 0x000000f8) >> 3) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_SET(x) (((x) << 3) & 0x000000f8) +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MSB 9 +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB 8 +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK 0x00000300 +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_SET(x) (((x) << 8) & 0x00000300) +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MSB 12 +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB 10 +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK 0x00001c00 +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MSB 14 +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB 13 +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK 0x00006000 +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_GET(x) (((x) & 0x00006000) >> 13) +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_SET(x) (((x) << 13) & 0x00006000) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MSB 15 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB 15 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK 0x00008000 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MSB 18 +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB 16 +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK 0x00070000 +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MSB 24 +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB 20 +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK 0x01f00000 +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_GET(x) (((x) & 0x01f00000) >> 20) + +/* macros for BB_radar_bw_filter */ +#define PHY_BB_RADAR_BW_FILTER_ADDRESS 0x0000a7e0 +#define PHY_BB_RADAR_BW_FILTER_OFFSET 0x0000a7e0 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MSB 0 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_LSB 0 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MASK 0x00000001 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MSB 1 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_LSB 1 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MASK 0x00000002 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MSB 3 +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_LSB 2 +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MASK 0x0000000c +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MSB 5 +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_LSB 4 +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MASK 0x00000030 +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_SET(x) (((x) << 4) & 0x00000030) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MSB 14 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_LSB 8 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MASK 0x00007f00 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_GET(x) (((x) & 0x00007f00) >> 8) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_SET(x) (((x) << 8) & 0x00007f00) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MSB 20 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_LSB 15 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MASK 0x001f8000 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_GET(x) (((x) & 0x001f8000) >> 15) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_SET(x) (((x) << 15) & 0x001f8000) +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MSB 26 +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_LSB 21 +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MASK 0x07e00000 +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_SET(x) (((x) << 21) & 0x07e00000) + +/* macros for BB_dft_tone_ctrl_b0 */ +#define PHY_BB_DFT_TONE_CTRL_B0_ADDRESS 0x0000a7e4 +#define PHY_BB_DFT_TONE_CTRL_B0_OFFSET 0x0000a7e4 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MSB 0 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB 0 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK 0x00000001 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MSB 3 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB 2 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK 0x0000000c +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MSB 12 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB 4 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK 0x00001ff0 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_GET(x) (((x) & 0x00001ff0) >> 4) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_SET(x) (((x) << 4) & 0x00001ff0) + +/* macros for BB_therm_adc_1 */ +#define PHY_BB_THERM_ADC_1_ADDRESS 0x0000a7e8 +#define PHY_BB_THERM_ADC_1_OFFSET 0x0000a7e8 +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MSB 7 +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_LSB 0 +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MASK 0x000000ff +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MSB 15 +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_LSB 8 +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MASK 0x0000ff00 +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MSB 23 +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_LSB 16 +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MASK 0x00ff0000 +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MSB 25 +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_LSB 24 +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MASK 0x03000000 +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_SET(x) (((x) << 24) & 0x03000000) +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MSB 26 +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB 26 +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK 0x04000000 +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MSB 27 +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB 27 +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK 0x08000000 +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_therm_adc_2 */ +#define PHY_BB_THERM_ADC_2_ADDRESS 0x0000a7ec +#define PHY_BB_THERM_ADC_2_OFFSET 0x0000a7ec +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MSB 11 +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_LSB 0 +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MASK 0x00000fff +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MSB 21 +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_LSB 12 +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MASK 0x003ff000 +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MSB 31 +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_LSB 22 +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MASK 0xffc00000 +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_GET(x) (((x) & 0xffc00000) >> 22) +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_SET(x) (((x) << 22) & 0xffc00000) + +/* macros for BB_therm_adc_3 */ +#define PHY_BB_THERM_ADC_3_ADDRESS 0x0000a7f0 +#define PHY_BB_THERM_ADC_3_OFFSET 0x0000a7f0 +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MSB 7 +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_LSB 0 +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MASK 0x000000ff +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MSB 16 +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_LSB 8 +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MASK 0x0001ff00 +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_GET(x) (((x) & 0x0001ff00) >> 8) +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_SET(x) (((x) << 8) & 0x0001ff00) +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MSB 29 +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_LSB 17 +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MASK 0x3ffe0000 +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_GET(x) (((x) & 0x3ffe0000) >> 17) +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_SET(x) (((x) << 17) & 0x3ffe0000) + +/* macros for BB_therm_adc_4 */ +#define PHY_BB_THERM_ADC_4_ADDRESS 0x0000a7f4 +#define PHY_BB_THERM_ADC_4_OFFSET 0x0000a7f4 +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MSB 7 +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_LSB 0 +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MASK 0x000000ff +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MSB 15 +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_LSB 8 +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MASK 0x0000ff00 +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MSB 23 +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_LSB 16 +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MASK 0x00ff0000 +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_GET(x) (((x) & 0x00ff0000) >> 16) + +/* macros for BB_tx_forced_gain */ +#define PHY_BB_TX_FORCED_GAIN_ADDRESS 0x0000a7f8 +#define PHY_BB_TX_FORCED_GAIN_OFFSET 0x0000a7f8 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MSB 0 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB 0 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK 0x00000001 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MSB 3 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB 1 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK 0x0000000e +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MSB 5 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB 4 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK 0x00000030 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_SET(x) (((x) << 4) & 0x00000030) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MSB 9 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB 6 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK 0x000003c0 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_GET(x) (((x) & 0x000003c0) >> 6) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_SET(x) (((x) << 6) & 0x000003c0) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MSB 13 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_LSB 10 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MASK 0x00003c00 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MSB 17 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_LSB 14 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MASK 0x0003c000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MSB 21 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_LSB 18 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MASK 0x003c0000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MSB 23 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_LSB 22 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MASK 0x00c00000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MSB 24 +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB 24 +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK 0x01000000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_SET(x) (((x) << 24) & 0x01000000) + +/* macros for BB_eco_ctrl */ +#define PHY_BB_ECO_CTRL_ADDRESS 0x0000a7fc +#define PHY_BB_ECO_CTRL_OFFSET 0x0000a7fc +#define PHY_BB_ECO_CTRL_ECO_CTRL_MSB 7 +#define PHY_BB_ECO_CTRL_ECO_CTRL_LSB 0 +#define PHY_BB_ECO_CTRL_ECO_CTRL_MASK 0x000000ff +#define PHY_BB_ECO_CTRL_ECO_CTRL_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_ECO_CTRL_ECO_CTRL_SET(x) (((x) << 0) & 0x000000ff) + +/* macros for BB_gain_force_max_gains_b1 */ +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_ADDRESS 0x0000a848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_OFFSET 0x0000a848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MSB 13 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_LSB 7 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MASK 0x00003f80 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MSB 20 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_LSB 14 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MASK 0x001fc000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_SET(x) (((x) << 14) & 0x001fc000) + +/* macros for BB_gains_min_offsets_b1 */ +#define PHY_BB_GAINS_MIN_OFFSETS_B1_ADDRESS 0x0000a84c +#define PHY_BB_GAINS_MIN_OFFSETS_B1_OFFSET 0x0000a84c +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MSB 24 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_LSB 17 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MASK 0x01fe0000 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_GET(x) (((x) & 0x01fe0000) >> 17) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_SET(x) (((x) << 17) & 0x01fe0000) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_LSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MASK 0x02000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_LSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MASK 0x04000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_SET(x) (((x) << 26) & 0x04000000) + +/* macros for BB_rx_ocgain2 */ +#define PHY_BB_RX_OCGAIN2_ADDRESS 0x0000aa00 +#define PHY_BB_RX_OCGAIN2_OFFSET 0x0000aa00 +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MSB 31 +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_LSB 0 +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MASK 0xffffffff +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_ext_atten_switch_ctl_b1 */ +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_ADDRESS 0x0000b20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_OFFSET 0x0000b20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MSB 5 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_LSB 0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MASK 0x0000003f +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MSB 11 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_LSB 6 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MASK 0x00000fc0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MSB 16 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_LSB 12 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MASK 0x0001f000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MSB 21 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_LSB 17 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MASK 0x003e0000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_SET(x) (((x) << 17) & 0x003e0000) + + +#ifndef __ASSEMBLER__ + +typedef struct bb_lc_reg_reg_s { + volatile char pad__0[0x9800]; /* 0x0 - 0x9800 */ + volatile unsigned int BB_test_controls; /* 0x9800 - 0x9804 */ + volatile unsigned int BB_gen_controls; /* 0x9804 - 0x9808 */ + volatile unsigned int BB_test_controls_status; /* 0x9808 - 0x980c */ + volatile unsigned int BB_timing_controls_1; /* 0x980c - 0x9810 */ + volatile unsigned int BB_timing_controls_2; /* 0x9810 - 0x9814 */ + volatile unsigned int BB_timing_controls_3; /* 0x9814 - 0x9818 */ + volatile unsigned int BB_D2_chip_id; /* 0x9818 - 0x981c */ + volatile unsigned int BB_active; /* 0x981c - 0x9820 */ + volatile unsigned int BB_tx_timing_1; /* 0x9820 - 0x9824 */ + volatile unsigned int BB_tx_timing_2; /* 0x9824 - 0x9828 */ + volatile unsigned int BB_tx_timing_3; /* 0x9828 - 0x982c */ + volatile unsigned int BB_addac_parallel_control; /* 0x982c - 0x9830 */ + volatile char pad__1[0x4]; /* 0x9830 - 0x9834 */ + volatile unsigned int BB_xpa_timing_control; /* 0x9834 - 0x9838 */ + volatile unsigned int BB_misc_pa_control; /* 0x9838 - 0x983c */ + volatile unsigned int BB_tstdac_constant; /* 0x983c - 0x9840 */ + volatile unsigned int BB_find_signal_low; /* 0x9840 - 0x9844 */ + volatile unsigned int BB_settling_time; /* 0x9844 - 0x9848 */ + volatile unsigned int BB_gain_force_max_gains_b0; /* 0x9848 - 0x984c */ + volatile unsigned int BB_gains_min_offsets_b0; /* 0x984c - 0x9850 */ + volatile unsigned int BB_desired_sigsize; /* 0x9850 - 0x9854 */ + volatile unsigned int BB_timing_control_3a; /* 0x9854 - 0x9858 */ + volatile unsigned int BB_find_signal; /* 0x9858 - 0x985c */ + volatile unsigned int BB_agc; /* 0x985c - 0x9860 */ + volatile unsigned int BB_agc_control; /* 0x9860 - 0x9864 */ + volatile unsigned int BB_cca_b0; /* 0x9864 - 0x9868 */ + volatile unsigned int BB_sfcorr; /* 0x9868 - 0x986c */ + volatile unsigned int BB_self_corr_low; /* 0x986c - 0x9870 */ + volatile char pad__2[0x4]; /* 0x9870 - 0x9874 */ + volatile unsigned int BB_synth_control; /* 0x9874 - 0x9878 */ + volatile unsigned int BB_addac_clk_select; /* 0x9878 - 0x987c */ + volatile unsigned int BB_pll_cntl; /* 0x987c - 0x9880 */ + volatile char pad__3[0x80]; /* 0x9880 - 0x9900 */ + volatile unsigned int BB_vit_spur_mask_A; /* 0x9900 - 0x9904 */ + volatile unsigned int BB_vit_spur_mask_B; /* 0x9904 - 0x9908 */ + volatile unsigned int BB_pilot_spur_mask; /* 0x9908 - 0x990c */ + volatile unsigned int BB_chan_spur_mask; /* 0x990c - 0x9910 */ + volatile unsigned int BB_spectral_scan; /* 0x9910 - 0x9914 */ + volatile unsigned int BB_analog_power_on_time; /* 0x9914 - 0x9918 */ + volatile unsigned int BB_search_start_delay; /* 0x9918 - 0x991c */ + volatile unsigned int BB_max_rx_length; /* 0x991c - 0x9920 */ + volatile unsigned int BB_timing_control_4; /* 0x9920 - 0x9924 */ + volatile unsigned int BB_timing_control_5; /* 0x9924 - 0x9928 */ + volatile unsigned int BB_phyonly_warm_reset; /* 0x9928 - 0x992c */ + volatile unsigned int BB_phyonly_control; /* 0x992c - 0x9930 */ + volatile char pad__4[0x4]; /* 0x9930 - 0x9934 */ + volatile unsigned int BB_powertx_rate1; /* 0x9934 - 0x9938 */ + volatile unsigned int BB_powertx_rate2; /* 0x9938 - 0x993c */ + volatile unsigned int BB_powertx_max; /* 0x993c - 0x9940 */ + volatile unsigned int BB_extension_radar; /* 0x9940 - 0x9944 */ + volatile unsigned int BB_frame_control; /* 0x9944 - 0x9948 */ + volatile unsigned int BB_timing_control_6; /* 0x9948 - 0x994c */ + volatile unsigned int BB_spur_mask_controls; /* 0x994c - 0x9950 */ + volatile unsigned int BB_rx_iq_corr_b0; /* 0x9950 - 0x9954 */ + volatile unsigned int BB_radar_detection; /* 0x9954 - 0x9958 */ + volatile unsigned int BB_radar_detection_2; /* 0x9958 - 0x995c */ + volatile unsigned int BB_tx_phase_ramp_b0; /* 0x995c - 0x9960 */ + volatile unsigned int BB_switch_table_chn_b0; /* 0x9960 - 0x9964 */ + volatile unsigned int BB_switch_table_com1; /* 0x9964 - 0x9968 */ + volatile unsigned int BB_cca_ctrl_2_b0; /* 0x9968 - 0x996c */ + volatile unsigned int BB_switch_table_com2; /* 0x996c - 0x9970 */ + volatile unsigned int BB_restart; /* 0x9970 - 0x9974 */ + volatile char pad__5[0x4]; /* 0x9974 - 0x9978 */ + volatile unsigned int BB_scrambler_seed; /* 0x9978 - 0x997c */ + volatile unsigned int BB_rfbus_request; /* 0x997c - 0x9980 */ + volatile char pad__6[0x20]; /* 0x9980 - 0x99a0 */ + volatile unsigned int BB_timing_control_11; /* 0x99a0 - 0x99a4 */ + volatile unsigned int BB_multichain_enable; /* 0x99a4 - 0x99a8 */ + volatile unsigned int BB_multichain_control; /* 0x99a8 - 0x99ac */ + volatile unsigned int BB_multichain_gain_ctrl; /* 0x99ac - 0x99b0 */ + volatile char pad__7[0x4]; /* 0x99b0 - 0x99b4 */ + volatile unsigned int BB_adc_gain_dc_corr_b0; /* 0x99b4 - 0x99b8 */ + volatile unsigned int BB_ext_chan_pwr_thr_1; /* 0x99b8 - 0x99bc */ + volatile unsigned int BB_ext_chan_pwr_thr_2_b0; /* 0x99bc - 0x99c0 */ + volatile unsigned int BB_ext_chan_scorr_thr; /* 0x99c0 - 0x99c4 */ + volatile unsigned int BB_ext_chan_detect_win; /* 0x99c4 - 0x99c8 */ + volatile unsigned int BB_pwr_thr_20_40_det; /* 0x99c8 - 0x99cc */ + volatile char pad__8[0x4]; /* 0x99cc - 0x99d0 */ + volatile unsigned int BB_short_gi_delta_slope; /* 0x99d0 - 0x99d4 */ + volatile char pad__9[0x8]; /* 0x99d4 - 0x99dc */ + volatile unsigned int BB_chaninfo_ctrl; /* 0x99dc - 0x99e0 */ + volatile unsigned int BB_heavy_clip_ctrl; /* 0x99e0 - 0x99e4 */ + volatile unsigned int BB_heavy_clip_20; /* 0x99e4 - 0x99e8 */ + volatile unsigned int BB_heavy_clip_40; /* 0x99e8 - 0x99ec */ + volatile unsigned int BB_rifs_srch; /* 0x99ec - 0x99f0 */ + volatile unsigned int BB_iq_adc_cal_mode; /* 0x99f0 - 0x99f4 */ + volatile char pad__10[0x8]; /* 0x99f4 - 0x99fc */ + volatile unsigned int BB_per_chain_csd; /* 0x99fc - 0x9a00 */ + volatile unsigned int BB_rx_ocgain[128]; /* 0x9a00 - 0x9c00 */ + volatile unsigned int BB_tx_crc; /* 0x9c00 - 0x9c04 */ + volatile char pad__11[0xc]; /* 0x9c04 - 0x9c10 */ + volatile unsigned int BB_iq_adc_meas_0_b0; /* 0x9c10 - 0x9c14 */ + volatile unsigned int BB_iq_adc_meas_1_b0; /* 0x9c14 - 0x9c18 */ + volatile unsigned int BB_iq_adc_meas_2_b0; /* 0x9c18 - 0x9c1c */ + volatile unsigned int BB_iq_adc_meas_3_b0; /* 0x9c1c - 0x9c20 */ + volatile unsigned int BB_rfbus_grant; /* 0x9c20 - 0x9c24 */ + volatile unsigned int BB_tstadc; /* 0x9c24 - 0x9c28 */ + volatile unsigned int BB_tstdac; /* 0x9c28 - 0x9c2c */ + volatile char pad__12[0x4]; /* 0x9c2c - 0x9c30 */ + volatile unsigned int BB_illegal_tx_rate; /* 0x9c30 - 0x9c34 */ + volatile unsigned int BB_spur_report_b0; /* 0x9c34 - 0x9c38 */ + volatile unsigned int BB_channel_status; /* 0x9c38 - 0x9c3c */ + volatile unsigned int BB_rssi_b0; /* 0x9c3c - 0x9c40 */ + volatile unsigned int BB_spur_est_cck_report_b0; /* 0x9c40 - 0x9c44 */ + volatile char pad__13[0x68]; /* 0x9c44 - 0x9cac */ + volatile unsigned int BB_chan_info_noise_pwr; /* 0x9cac - 0x9cb0 */ + volatile unsigned int BB_chan_info_gain_diff; /* 0x9cb0 - 0x9cb4 */ + volatile unsigned int BB_chan_info_fine_timing; /* 0x9cb4 - 0x9cb8 */ + volatile unsigned int BB_chan_info_gain_b0; /* 0x9cb8 - 0x9cbc */ + volatile unsigned int BB_chan_info_chan_tab_b0[60]; /* 0x9cbc - 0x9dac */ + volatile char pad__14[0x38]; /* 0x9dac - 0x9de4 */ + volatile unsigned int BB_paprd_am2am_mask; /* 0x9de4 - 0x9de8 */ + volatile unsigned int BB_paprd_am2pm_mask; /* 0x9de8 - 0x9dec */ + volatile unsigned int BB_paprd_ht40_mask; /* 0x9dec - 0x9df0 */ + volatile unsigned int BB_paprd_ctrl0; /* 0x9df0 - 0x9df4 */ + volatile unsigned int BB_paprd_ctrl1; /* 0x9df4 - 0x9df8 */ + volatile unsigned int BB_pa_gain123; /* 0x9df8 - 0x9dfc */ + volatile unsigned int BB_pa_gain45; /* 0x9dfc - 0x9e00 */ + volatile unsigned int BB_paprd_pre_post_scale_0; /* 0x9e00 - 0x9e04 */ + volatile unsigned int BB_paprd_pre_post_scale_1; /* 0x9e04 - 0x9e08 */ + volatile unsigned int BB_paprd_pre_post_scale_2; /* 0x9e08 - 0x9e0c */ + volatile unsigned int BB_paprd_pre_post_scale_3; /* 0x9e0c - 0x9e10 */ + volatile unsigned int BB_paprd_pre_post_scale_4; /* 0x9e10 - 0x9e14 */ + volatile unsigned int BB_paprd_pre_post_scale_5; /* 0x9e14 - 0x9e18 */ + volatile unsigned int BB_paprd_pre_post_scale_6; /* 0x9e18 - 0x9e1c */ + volatile unsigned int BB_paprd_pre_post_scale_7; /* 0x9e1c - 0x9e20 */ + volatile unsigned int BB_paprd_mem_tab[120]; /* 0x9e20 - 0xa000 */ + volatile unsigned int BB_peak_det_ctrl_1; /* 0xa000 - 0xa004 */ + volatile unsigned int BB_peak_det_ctrl_2; /* 0xa004 - 0xa008 */ + volatile unsigned int BB_rx_gain_bounds_1; /* 0xa008 - 0xa00c */ + volatile unsigned int BB_rx_gain_bounds_2; /* 0xa00c - 0xa010 */ + volatile unsigned int BB_peak_det_cal_ctrl; /* 0xa010 - 0xa014 */ + volatile unsigned int BB_agc_dig_dc_ctrl; /* 0xa014 - 0xa018 */ + volatile unsigned int BB_agc_dig_dc_status_i_b0; /* 0xa018 - 0xa01c */ + volatile unsigned int BB_agc_dig_dc_status_q_b0; /* 0xa01c - 0xa020 */ + volatile char pad__15[0x1d4]; /* 0xa020 - 0xa1f4 */ + volatile unsigned int BB_bbb_txfir_0; /* 0xa1f4 - 0xa1f8 */ + volatile unsigned int BB_bbb_txfir_1; /* 0xa1f8 - 0xa1fc */ + volatile unsigned int BB_bbb_txfir_2; /* 0xa1fc - 0xa200 */ + volatile unsigned int BB_modes_select; /* 0xa200 - 0xa204 */ + volatile unsigned int BB_bbb_tx_ctrl; /* 0xa204 - 0xa208 */ + volatile unsigned int BB_bbb_sig_detect; /* 0xa208 - 0xa20c */ + volatile unsigned int BB_ext_atten_switch_ctl_b0; /* 0xa20c - 0xa210 */ + volatile unsigned int BB_bbb_rx_ctrl_1; /* 0xa210 - 0xa214 */ + volatile unsigned int BB_bbb_rx_ctrl_2; /* 0xa214 - 0xa218 */ + volatile unsigned int BB_bbb_rx_ctrl_3; /* 0xa218 - 0xa21c */ + volatile unsigned int BB_bbb_rx_ctrl_4; /* 0xa21c - 0xa220 */ + volatile unsigned int BB_bbb_rx_ctrl_5; /* 0xa220 - 0xa224 */ + volatile unsigned int BB_bbb_rx_ctrl_6; /* 0xa224 - 0xa228 */ + volatile unsigned int BB_bbb_dagc_ctrl; /* 0xa228 - 0xa22c */ + volatile unsigned int BB_force_clken_cck; /* 0xa22c - 0xa230 */ + volatile unsigned int BB_rx_clear_delay; /* 0xa230 - 0xa234 */ + volatile unsigned int BB_powertx_rate3; /* 0xa234 - 0xa238 */ + volatile unsigned int BB_powertx_rate4; /* 0xa238 - 0xa23c */ + volatile char pad__16[0x4]; /* 0xa23c - 0xa240 */ + volatile unsigned int BB_cck_spur_mit; /* 0xa240 - 0xa244 */ + volatile unsigned int BB_panic_watchdog_status; /* 0xa244 - 0xa248 */ + volatile unsigned int BB_panic_watchdog_ctrl_1; /* 0xa248 - 0xa24c */ + volatile unsigned int BB_panic_watchdog_ctrl_2; /* 0xa24c - 0xa250 */ + volatile unsigned int BB_iqcorr_ctrl_cck; /* 0xa250 - 0xa254 */ + volatile unsigned int BB_bluetooth_cntl; /* 0xa254 - 0xa258 */ + volatile unsigned int BB_tpc_1; /* 0xa258 - 0xa25c */ + volatile unsigned int BB_tpc_2; /* 0xa25c - 0xa260 */ + volatile unsigned int BB_tpc_3; /* 0xa260 - 0xa264 */ + volatile unsigned int BB_tpc_4_b0; /* 0xa264 - 0xa268 */ + volatile unsigned int BB_analog_swap; /* 0xa268 - 0xa26c */ + volatile unsigned int BB_tpc_5_b0; /* 0xa26c - 0xa270 */ + volatile unsigned int BB_tpc_6_b0; /* 0xa270 - 0xa274 */ + volatile unsigned int BB_tpc_7; /* 0xa274 - 0xa278 */ + volatile unsigned int BB_tpc_8; /* 0xa278 - 0xa27c */ + volatile unsigned int BB_tpc_9; /* 0xa27c - 0xa280 */ + volatile unsigned int BB_pdadc_tab_b0[32]; /* 0xa280 - 0xa300 */ + volatile unsigned int BB_cl_tab_b0[16]; /* 0xa300 - 0xa340 */ + volatile unsigned int BB_cl_map_0_b0; /* 0xa340 - 0xa344 */ + volatile unsigned int BB_cl_map_1_b0; /* 0xa344 - 0xa348 */ + volatile unsigned int BB_cl_map_2_b0; /* 0xa348 - 0xa34c */ + volatile unsigned int BB_cl_map_3_b0; /* 0xa34c - 0xa350 */ + volatile char pad__17[0x8]; /* 0xa350 - 0xa358 */ + volatile unsigned int BB_cl_cal_ctrl; /* 0xa358 - 0xa35c */ + volatile unsigned int BB_cl_map_pal_0_b0; /* 0xa35c - 0xa360 */ + volatile unsigned int BB_cl_map_pal_1_b0; /* 0xa360 - 0xa364 */ + volatile unsigned int BB_cl_map_pal_2_b0; /* 0xa364 - 0xa368 */ + volatile unsigned int BB_cl_map_pal_3_b0; /* 0xa368 - 0xa36c */ + volatile char pad__18[0x1c]; /* 0xa36c - 0xa388 */ + volatile unsigned int BB_rifs; /* 0xa388 - 0xa38c */ + volatile unsigned int BB_powertx_rate5; /* 0xa38c - 0xa390 */ + volatile unsigned int BB_powertx_rate6; /* 0xa390 - 0xa394 */ + volatile unsigned int BB_tpc_10; /* 0xa394 - 0xa398 */ + volatile unsigned int BB_tpc_11_b0; /* 0xa398 - 0xa39c */ + volatile unsigned int BB_cal_chain_mask; /* 0xa39c - 0xa3a0 */ + volatile char pad__19[0x1c]; /* 0xa3a0 - 0xa3bc */ + volatile unsigned int BB_powertx_sub; /* 0xa3bc - 0xa3c0 */ + volatile unsigned int BB_powertx_rate7; /* 0xa3c0 - 0xa3c4 */ + volatile unsigned int BB_powertx_rate8; /* 0xa3c4 - 0xa3c8 */ + volatile unsigned int BB_powertx_rate9; /* 0xa3c8 - 0xa3cc */ + volatile unsigned int BB_powertx_rate10; /* 0xa3cc - 0xa3d0 */ + volatile unsigned int BB_powertx_rate11; /* 0xa3d0 - 0xa3d4 */ + volatile unsigned int BB_powertx_rate12; /* 0xa3d4 - 0xa3d8 */ + volatile unsigned int BB_force_analog; /* 0xa3d8 - 0xa3dc */ + volatile unsigned int BB_tpc_12; /* 0xa3dc - 0xa3e0 */ + volatile unsigned int BB_tpc_13; /* 0xa3e0 - 0xa3e4 */ + volatile unsigned int BB_tpc_14; /* 0xa3e4 - 0xa3e8 */ + volatile unsigned int BB_tpc_15; /* 0xa3e8 - 0xa3ec */ + volatile unsigned int BB_tpc_16; /* 0xa3ec - 0xa3f0 */ + volatile unsigned int BB_tpc_17; /* 0xa3f0 - 0xa3f4 */ + volatile unsigned int BB_tpc_18; /* 0xa3f4 - 0xa3f8 */ + volatile unsigned int BB_tpc_19; /* 0xa3f8 - 0xa3fc */ + volatile unsigned int BB_tpc_20; /* 0xa3fc - 0xa400 */ + volatile unsigned int BB_tx_gain_tab_1; /* 0xa400 - 0xa404 */ + volatile unsigned int BB_tx_gain_tab_2; /* 0xa404 - 0xa408 */ + volatile unsigned int BB_tx_gain_tab_3; /* 0xa408 - 0xa40c */ + volatile unsigned int BB_tx_gain_tab_4; /* 0xa40c - 0xa410 */ + volatile unsigned int BB_tx_gain_tab_5; /* 0xa410 - 0xa414 */ + volatile unsigned int BB_tx_gain_tab_6; /* 0xa414 - 0xa418 */ + volatile unsigned int BB_tx_gain_tab_7; /* 0xa418 - 0xa41c */ + volatile unsigned int BB_tx_gain_tab_8; /* 0xa41c - 0xa420 */ + volatile unsigned int BB_tx_gain_tab_9; /* 0xa420 - 0xa424 */ + volatile unsigned int BB_tx_gain_tab_10; /* 0xa424 - 0xa428 */ + volatile unsigned int BB_tx_gain_tab_11; /* 0xa428 - 0xa42c */ + volatile unsigned int BB_tx_gain_tab_12; /* 0xa42c - 0xa430 */ + volatile unsigned int BB_tx_gain_tab_13; /* 0xa430 - 0xa434 */ + volatile unsigned int BB_tx_gain_tab_14; /* 0xa434 - 0xa438 */ + volatile unsigned int BB_tx_gain_tab_15; /* 0xa438 - 0xa43c */ + volatile unsigned int BB_tx_gain_tab_16; /* 0xa43c - 0xa440 */ + volatile unsigned int BB_tx_gain_tab_17; /* 0xa440 - 0xa444 */ + volatile unsigned int BB_tx_gain_tab_18; /* 0xa444 - 0xa448 */ + volatile unsigned int BB_tx_gain_tab_19; /* 0xa448 - 0xa44c */ + volatile unsigned int BB_tx_gain_tab_20; /* 0xa44c - 0xa450 */ + volatile unsigned int BB_tx_gain_tab_21; /* 0xa450 - 0xa454 */ + volatile unsigned int BB_tx_gain_tab_22; /* 0xa454 - 0xa458 */ + volatile unsigned int BB_tx_gain_tab_23; /* 0xa458 - 0xa45c */ + volatile unsigned int BB_tx_gain_tab_24; /* 0xa45c - 0xa460 */ + volatile unsigned int BB_tx_gain_tab_25; /* 0xa460 - 0xa464 */ + volatile unsigned int BB_tx_gain_tab_26; /* 0xa464 - 0xa468 */ + volatile unsigned int BB_tx_gain_tab_27; /* 0xa468 - 0xa46c */ + volatile unsigned int BB_tx_gain_tab_28; /* 0xa46c - 0xa470 */ + volatile unsigned int BB_tx_gain_tab_29; /* 0xa470 - 0xa474 */ + volatile unsigned int BB_tx_gain_tab_30; /* 0xa474 - 0xa478 */ + volatile unsigned int BB_tx_gain_tab_31; /* 0xa478 - 0xa47c */ + volatile unsigned int BB_tx_gain_tab_32; /* 0xa47c - 0xa480 */ + volatile unsigned int BB_tx_gain_tab_pal_1; /* 0xa480 - 0xa484 */ + volatile unsigned int BB_tx_gain_tab_pal_2; /* 0xa484 - 0xa488 */ + volatile unsigned int BB_tx_gain_tab_pal_3; /* 0xa488 - 0xa48c */ + volatile unsigned int BB_tx_gain_tab_pal_4; /* 0xa48c - 0xa490 */ + volatile unsigned int BB_tx_gain_tab_pal_5; /* 0xa490 - 0xa494 */ + volatile unsigned int BB_tx_gain_tab_pal_6; /* 0xa494 - 0xa498 */ + volatile unsigned int BB_tx_gain_tab_pal_7; /* 0xa498 - 0xa49c */ + volatile unsigned int BB_tx_gain_tab_pal_8; /* 0xa49c - 0xa4a0 */ + volatile unsigned int BB_tx_gain_tab_pal_9; /* 0xa4a0 - 0xa4a4 */ + volatile unsigned int BB_tx_gain_tab_pal_10; /* 0xa4a4 - 0xa4a8 */ + volatile unsigned int BB_tx_gain_tab_pal_11; /* 0xa4a8 - 0xa4ac */ + volatile unsigned int BB_tx_gain_tab_pal_12; /* 0xa4ac - 0xa4b0 */ + volatile unsigned int BB_tx_gain_tab_pal_13; /* 0xa4b0 - 0xa4b4 */ + volatile unsigned int BB_tx_gain_tab_pal_14; /* 0xa4b4 - 0xa4b8 */ + volatile unsigned int BB_tx_gain_tab_pal_15; /* 0xa4b8 - 0xa4bc */ + volatile unsigned int BB_tx_gain_tab_pal_16; /* 0xa4bc - 0xa4c0 */ + volatile unsigned int BB_tx_gain_tab_pal_17; /* 0xa4c0 - 0xa4c4 */ + volatile unsigned int BB_tx_gain_tab_pal_18; /* 0xa4c4 - 0xa4c8 */ + volatile unsigned int BB_tx_gain_tab_pal_19; /* 0xa4c8 - 0xa4cc */ + volatile unsigned int BB_tx_gain_tab_pal_20; /* 0xa4cc - 0xa4d0 */ + volatile unsigned int BB_tx_gain_tab_pal_21; /* 0xa4d0 - 0xa4d4 */ + volatile unsigned int BB_tx_gain_tab_pal_22; /* 0xa4d4 - 0xa4d8 */ + volatile unsigned int BB_tx_gain_tab_pal_23; /* 0xa4d8 - 0xa4dc */ + volatile unsigned int BB_tx_gain_tab_pal_24; /* 0xa4dc - 0xa4e0 */ + volatile unsigned int BB_tx_gain_tab_pal_25; /* 0xa4e0 - 0xa4e4 */ + volatile unsigned int BB_tx_gain_tab_pal_26; /* 0xa4e4 - 0xa4e8 */ + volatile unsigned int BB_tx_gain_tab_pal_27; /* 0xa4e8 - 0xa4ec */ + volatile unsigned int BB_tx_gain_tab_pal_28; /* 0xa4ec - 0xa4f0 */ + volatile unsigned int BB_tx_gain_tab_pal_29; /* 0xa4f0 - 0xa4f4 */ + volatile unsigned int BB_tx_gain_tab_pal_30; /* 0xa4f4 - 0xa4f8 */ + volatile unsigned int BB_tx_gain_tab_pal_31; /* 0xa4f8 - 0xa4fc */ + volatile unsigned int BB_tx_gain_tab_pal_32; /* 0xa4fc - 0xa500 */ + volatile char pad__20[0x18]; /* 0xa500 - 0xa518 */ + volatile unsigned int BB_caltx_gain_set_0; /* 0xa518 - 0xa51c */ + volatile unsigned int BB_caltx_gain_set_2; /* 0xa51c - 0xa520 */ + volatile unsigned int BB_caltx_gain_set_4; /* 0xa520 - 0xa524 */ + volatile unsigned int BB_caltx_gain_set_6; /* 0xa524 - 0xa528 */ + volatile unsigned int BB_caltx_gain_set_8; /* 0xa528 - 0xa52c */ + volatile unsigned int BB_caltx_gain_set_10; /* 0xa52c - 0xa530 */ + volatile unsigned int BB_caltx_gain_set_12; /* 0xa530 - 0xa534 */ + volatile unsigned int BB_caltx_gain_set_14; /* 0xa534 - 0xa538 */ + volatile unsigned int BB_caltx_gain_set_16; /* 0xa538 - 0xa53c */ + volatile unsigned int BB_caltx_gain_set_18; /* 0xa53c - 0xa540 */ + volatile unsigned int BB_caltx_gain_set_20; /* 0xa540 - 0xa544 */ + volatile unsigned int BB_caltx_gain_set_22; /* 0xa544 - 0xa548 */ + volatile unsigned int BB_caltx_gain_set_24; /* 0xa548 - 0xa54c */ + volatile unsigned int BB_caltx_gain_set_26; /* 0xa54c - 0xa550 */ + volatile unsigned int BB_caltx_gain_set_28; /* 0xa550 - 0xa554 */ + volatile unsigned int BB_caltx_gain_set_30; /* 0xa554 - 0xa558 */ + volatile unsigned int BB_txiqcal_meas_b0[96]; /* 0xa558 - 0xa6d8 */ + volatile unsigned int BB_txiqcal_start; /* 0xa6d8 - 0xa6dc */ + volatile unsigned int BB_txiqcal_control_0; /* 0xa6dc - 0xa6e0 */ + volatile unsigned int BB_txiqcal_control_1; /* 0xa6e0 - 0xa6e4 */ + volatile unsigned int BB_txiqcal_control_2; /* 0xa6e4 - 0xa6e8 */ + volatile unsigned int BB_txiqcal_control_3; /* 0xa6e8 - 0xa6ec */ + volatile unsigned int BB_txiq_corr_coeff_01_b0; /* 0xa6ec - 0xa6f0 */ + volatile unsigned int BB_txiq_corr_coeff_23_b0; /* 0xa6f0 - 0xa6f4 */ + volatile unsigned int BB_txiq_corr_coeff_45_b0; /* 0xa6f4 - 0xa6f8 */ + volatile unsigned int BB_txiq_corr_coeff_67_b0; /* 0xa6f8 - 0xa6fc */ + volatile unsigned int BB_txiq_corr_coeff_89_b0; /* 0xa6fc - 0xa700 */ + volatile unsigned int BB_txiq_corr_coeff_ab_b0; /* 0xa700 - 0xa704 */ + volatile unsigned int BB_txiq_corr_coeff_cd_b0; /* 0xa704 - 0xa708 */ + volatile unsigned int BB_txiq_corr_coeff_ef_b0; /* 0xa708 - 0xa70c */ + volatile unsigned int BB_cal_rxbb_gain_tbl_0; /* 0xa70c - 0xa710 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_4; /* 0xa710 - 0xa714 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_8; /* 0xa714 - 0xa718 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_12; /* 0xa718 - 0xa71c */ + volatile unsigned int BB_cal_rxbb_gain_tbl_16; /* 0xa71c - 0xa720 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_20; /* 0xa720 - 0xa724 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_24; /* 0xa724 - 0xa728 */ + volatile unsigned int BB_txiqcal_status_b0; /* 0xa728 - 0xa72c */ + volatile unsigned int BB_paprd_trainer_cntl1; /* 0xa72c - 0xa730 */ + volatile unsigned int BB_paprd_trainer_cntl2; /* 0xa730 - 0xa734 */ + volatile unsigned int BB_paprd_trainer_cntl3; /* 0xa734 - 0xa738 */ + volatile unsigned int BB_paprd_trainer_cntl4; /* 0xa738 - 0xa73c */ + volatile unsigned int BB_paprd_trainer_stat1; /* 0xa73c - 0xa740 */ + volatile unsigned int BB_paprd_trainer_stat2; /* 0xa740 - 0xa744 */ + volatile unsigned int BB_paprd_trainer_stat3; /* 0xa744 - 0xa748 */ + volatile char pad__21[0x90]; /* 0xa748 - 0xa7d8 */ + volatile unsigned int BB_fcal_1; /* 0xa7d8 - 0xa7dc */ + volatile unsigned int BB_fcal_2_b0; /* 0xa7dc - 0xa7e0 */ + volatile unsigned int BB_radar_bw_filter; /* 0xa7e0 - 0xa7e4 */ + volatile unsigned int BB_dft_tone_ctrl_b0; /* 0xa7e4 - 0xa7e8 */ + volatile unsigned int BB_therm_adc_1; /* 0xa7e8 - 0xa7ec */ + volatile unsigned int BB_therm_adc_2; /* 0xa7ec - 0xa7f0 */ + volatile unsigned int BB_therm_adc_3; /* 0xa7f0 - 0xa7f4 */ + volatile unsigned int BB_therm_adc_4; /* 0xa7f4 - 0xa7f8 */ + volatile unsigned int BB_tx_forced_gain; /* 0xa7f8 - 0xa7fc */ + volatile unsigned int BB_eco_ctrl; /* 0xa7fc - 0xa800 */ + volatile char pad__22[0x48]; /* 0xa800 - 0xa848 */ + volatile unsigned int BB_gain_force_max_gains_b1; /* 0xa848 - 0xa84c */ + volatile unsigned int BB_gains_min_offsets_b1; /* 0xa84c - 0xa850 */ + volatile char pad__23[0x1b0]; /* 0xa850 - 0xaa00 */ + volatile unsigned int BB_rx_ocgain2[128]; /* 0xaa00 - 0xac00 */ + volatile char pad__24[0x60c]; /* 0xac00 - 0xb20c */ + volatile unsigned int BB_ext_atten_switch_ctl_b1; /* 0xb20c - 0xb210 */ +} bb_lc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _BB_LC_REG_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h new file mode 100644 index 000000000000..12cadb337482 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h @@ -0,0 +1,108 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _EFUSE_REG_REG_H_ +#define _EFUSE_REG_REG_H_ + +#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000 +#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000 +#define EFUSE_WR_ENABLE_REG_V_MSB 0 +#define EFUSE_WR_ENABLE_REG_V_LSB 0 +#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001 +#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB) +#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK) + +#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004 +#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004 +#define EFUSE_INT_ENABLE_REG_V_MSB 0 +#define EFUSE_INT_ENABLE_REG_V_LSB 0 +#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001 +#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB) +#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK) + +#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008 +#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008 +#define EFUSE_INT_STATUS_REG_V_MSB 0 +#define EFUSE_INT_STATUS_REG_V_LSB 0 +#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001 +#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB) +#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK) + +#define BITMASK_WR_REG_ADDRESS 0x0000000c +#define BITMASK_WR_REG_OFFSET 0x0000000c +#define BITMASK_WR_REG_V_MSB 31 +#define BITMASK_WR_REG_V_LSB 0 +#define BITMASK_WR_REG_V_MASK 0xffffffff +#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB) +#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK) + +#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010 +#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010 +#define VDDQ_SETTLE_TIME_REG_V_MSB 31 +#define VDDQ_SETTLE_TIME_REG_V_LSB 0 +#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff +#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB) +#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK) + +#define RD_STROBE_PW_REG_ADDRESS 0x00000014 +#define RD_STROBE_PW_REG_OFFSET 0x00000014 +#define RD_STROBE_PW_REG_V_MSB 31 +#define RD_STROBE_PW_REG_V_LSB 0 +#define RD_STROBE_PW_REG_V_MASK 0xffffffff +#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB) +#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK) + +#define PG_STROBE_PW_REG_ADDRESS 0x00000018 +#define PG_STROBE_PW_REG_OFFSET 0x00000018 +#define PG_STROBE_PW_REG_V_MSB 31 +#define PG_STROBE_PW_REG_V_LSB 0 +#define PG_STROBE_PW_REG_V_MASK 0xffffffff +#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB) +#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK) + +#define EFUSE_INTF_ADDRESS 0x00000800 +#define EFUSE_INTF_OFFSET 0x00000800 +#define EFUSE_INTF_R_MSB 31 +#define EFUSE_INTF_R_LSB 0 +#define EFUSE_INTF_R_MASK 0xffffffff +#define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB) +#define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct efuse_reg_reg_s { + volatile unsigned int efuse_wr_enable_reg; + volatile unsigned int efuse_int_enable_reg; + volatile unsigned int efuse_int_status_reg; + volatile unsigned int bitmask_wr_reg; + volatile unsigned int vddq_settle_time_reg; + volatile unsigned int rd_strobe_pw_reg; + volatile unsigned int pg_strobe_pw_reg; + unsigned char pad0[2020]; /* pad to 0x800 */ + volatile unsigned int efuse_intf[512]; +} efuse_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _EFUSE_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h new file mode 100644 index 000000000000..1adee707de7c --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h @@ -0,0 +1,1253 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _GPIO_ATHR_WLAN_REG_REG_H_ +#define _GPIO_ATHR_WLAN_REG_REG_H_ + +#define WLAN_GPIO_OUT_ADDRESS 0x00000000 +#define WLAN_GPIO_OUT_OFFSET 0x00000000 +#define WLAN_GPIO_OUT_DATA_MSB 25 +#define WLAN_GPIO_OUT_DATA_LSB 0 +#define WLAN_GPIO_OUT_DATA_MASK 0x03ffffff +#define WLAN_GPIO_OUT_DATA_GET(x) (((x) & WLAN_GPIO_OUT_DATA_MASK) >> WLAN_GPIO_OUT_DATA_LSB) +#define WLAN_GPIO_OUT_DATA_SET(x) (((x) << WLAN_GPIO_OUT_DATA_LSB) & WLAN_GPIO_OUT_DATA_MASK) + +#define WLAN_GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define WLAN_GPIO_OUT_W1TS_OFFSET 0x00000004 +#define WLAN_GPIO_OUT_W1TS_DATA_MSB 25 +#define WLAN_GPIO_OUT_W1TS_DATA_LSB 0 +#define WLAN_GPIO_OUT_W1TS_DATA_MASK 0x03ffffff +#define WLAN_GPIO_OUT_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TS_DATA_MASK) >> WLAN_GPIO_OUT_W1TS_DATA_LSB) +#define WLAN_GPIO_OUT_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TS_DATA_LSB) & WLAN_GPIO_OUT_W1TS_DATA_MASK) + +#define WLAN_GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define WLAN_GPIO_OUT_W1TC_OFFSET 0x00000008 +#define WLAN_GPIO_OUT_W1TC_DATA_MSB 25 +#define WLAN_GPIO_OUT_W1TC_DATA_LSB 0 +#define WLAN_GPIO_OUT_W1TC_DATA_MASK 0x03ffffff +#define WLAN_GPIO_OUT_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TC_DATA_MASK) >> WLAN_GPIO_OUT_W1TC_DATA_LSB) +#define WLAN_GPIO_OUT_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TC_DATA_LSB) & WLAN_GPIO_OUT_W1TC_DATA_MASK) + +#define WLAN_GPIO_ENABLE_ADDRESS 0x0000000c +#define WLAN_GPIO_ENABLE_OFFSET 0x0000000c +#define WLAN_GPIO_ENABLE_DATA_MSB 25 +#define WLAN_GPIO_ENABLE_DATA_LSB 0 +#define WLAN_GPIO_ENABLE_DATA_MASK 0x03ffffff +#define WLAN_GPIO_ENABLE_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_DATA_MASK) >> WLAN_GPIO_ENABLE_DATA_LSB) +#define WLAN_GPIO_ENABLE_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_DATA_LSB) & WLAN_GPIO_ENABLE_DATA_MASK) + +#define WLAN_GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define WLAN_GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define WLAN_GPIO_ENABLE_W1TS_DATA_MSB 25 +#define WLAN_GPIO_ENABLE_W1TS_DATA_LSB 0 +#define WLAN_GPIO_ENABLE_W1TS_DATA_MASK 0x03ffffff +#define WLAN_GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TS_DATA_LSB) +#define WLAN_GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TS_DATA_LSB) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) + +#define WLAN_GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define WLAN_GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define WLAN_GPIO_ENABLE_W1TC_DATA_MSB 25 +#define WLAN_GPIO_ENABLE_W1TC_DATA_LSB 0 +#define WLAN_GPIO_ENABLE_W1TC_DATA_MASK 0x03ffffff +#define WLAN_GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TC_DATA_LSB) +#define WLAN_GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TC_DATA_LSB) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) + +#define WLAN_GPIO_IN_ADDRESS 0x00000018 +#define WLAN_GPIO_IN_OFFSET 0x00000018 +#define WLAN_GPIO_IN_DATA_MSB 25 +#define WLAN_GPIO_IN_DATA_LSB 0 +#define WLAN_GPIO_IN_DATA_MASK 0x03ffffff +#define WLAN_GPIO_IN_DATA_GET(x) (((x) & WLAN_GPIO_IN_DATA_MASK) >> WLAN_GPIO_IN_DATA_LSB) +#define WLAN_GPIO_IN_DATA_SET(x) (((x) << WLAN_GPIO_IN_DATA_LSB) & WLAN_GPIO_IN_DATA_MASK) + +#define WLAN_GPIO_STATUS_ADDRESS 0x0000001c +#define WLAN_GPIO_STATUS_OFFSET 0x0000001c +#define WLAN_GPIO_STATUS_INTERRUPT_MSB 25 +#define WLAN_GPIO_STATUS_INTERRUPT_LSB 0 +#define WLAN_GPIO_STATUS_INTERRUPT_MASK 0x03ffffff +#define WLAN_GPIO_STATUS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_INTERRUPT_LSB) +#define WLAN_GPIO_STATUS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_INTERRUPT_MASK) + +#define WLAN_GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define WLAN_GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB 25 +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK 0x03ffffff +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define WLAN_GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define WLAN_GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB 25 +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK 0x03ffffff +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define WLAN_GPIO_PIN0_ADDRESS 0x00000028 +#define WLAN_GPIO_PIN0_OFFSET 0x00000028 +#define WLAN_GPIO_PIN0_CONFIG_MSB 13 +#define WLAN_GPIO_PIN0_CONFIG_LSB 11 +#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN0_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN0_CONFIG_MASK) >> WLAN_GPIO_PIN0_CONFIG_LSB) +#define WLAN_GPIO_PIN0_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN0_CONFIG_LSB) & WLAN_GPIO_PIN0_CONFIG_MASK) +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN0_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN0_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN0_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN0_INT_TYPE_MASK) >> WLAN_GPIO_PIN0_INT_TYPE_LSB) +#define WLAN_GPIO_PIN0_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN0_INT_TYPE_LSB) & WLAN_GPIO_PIN0_INT_TYPE_MASK) +#define WLAN_GPIO_PIN0_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN0_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_PULL_MASK) >> WLAN_GPIO_PIN0_PAD_PULL_LSB) +#define WLAN_GPIO_PIN0_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_PULL_LSB) & WLAN_GPIO_PIN0_PAD_PULL_MASK) +#define WLAN_GPIO_PIN0_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN0_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN0_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN0_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN0_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN0_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_DRIVER_LSB) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN0_SOURCE_MSB 0 +#define WLAN_GPIO_PIN0_SOURCE_LSB 0 +#define WLAN_GPIO_PIN0_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN0_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN0_SOURCE_MASK) >> WLAN_GPIO_PIN0_SOURCE_LSB) +#define WLAN_GPIO_PIN0_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN0_SOURCE_LSB) & WLAN_GPIO_PIN0_SOURCE_MASK) + +#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c +#define WLAN_GPIO_PIN1_OFFSET 0x0000002c +#define WLAN_GPIO_PIN1_CONFIG_MSB 13 +#define WLAN_GPIO_PIN1_CONFIG_LSB 11 +#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN1_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN1_CONFIG_MASK) >> WLAN_GPIO_PIN1_CONFIG_LSB) +#define WLAN_GPIO_PIN1_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN1_CONFIG_LSB) & WLAN_GPIO_PIN1_CONFIG_MASK) +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN1_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN1_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN1_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN1_INT_TYPE_MASK) >> WLAN_GPIO_PIN1_INT_TYPE_LSB) +#define WLAN_GPIO_PIN1_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN1_INT_TYPE_LSB) & WLAN_GPIO_PIN1_INT_TYPE_MASK) +#define WLAN_GPIO_PIN1_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN1_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN1_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN1_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_PULL_MASK) >> WLAN_GPIO_PIN1_PAD_PULL_LSB) +#define WLAN_GPIO_PIN1_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_PULL_LSB) & WLAN_GPIO_PIN1_PAD_PULL_MASK) +#define WLAN_GPIO_PIN1_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN1_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN1_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN1_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN1_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN1_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_DRIVER_LSB) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN1_SOURCE_MSB 0 +#define WLAN_GPIO_PIN1_SOURCE_LSB 0 +#define WLAN_GPIO_PIN1_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN1_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN1_SOURCE_MASK) >> WLAN_GPIO_PIN1_SOURCE_LSB) +#define WLAN_GPIO_PIN1_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN1_SOURCE_LSB) & WLAN_GPIO_PIN1_SOURCE_MASK) + +#define WLAN_GPIO_PIN2_ADDRESS 0x00000030 +#define WLAN_GPIO_PIN2_OFFSET 0x00000030 +#define WLAN_GPIO_PIN2_CONFIG_MSB 13 +#define WLAN_GPIO_PIN2_CONFIG_LSB 11 +#define WLAN_GPIO_PIN2_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN2_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN2_CONFIG_MASK) >> WLAN_GPIO_PIN2_CONFIG_LSB) +#define WLAN_GPIO_PIN2_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN2_CONFIG_LSB) & WLAN_GPIO_PIN2_CONFIG_MASK) +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN2_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN2_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN2_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN2_INT_TYPE_MASK) >> WLAN_GPIO_PIN2_INT_TYPE_LSB) +#define WLAN_GPIO_PIN2_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN2_INT_TYPE_LSB) & WLAN_GPIO_PIN2_INT_TYPE_MASK) +#define WLAN_GPIO_PIN2_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN2_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN2_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN2_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_PULL_MASK) >> WLAN_GPIO_PIN2_PAD_PULL_LSB) +#define WLAN_GPIO_PIN2_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_PULL_LSB) & WLAN_GPIO_PIN2_PAD_PULL_MASK) +#define WLAN_GPIO_PIN2_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN2_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN2_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN2_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN2_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN2_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_DRIVER_LSB) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN2_SOURCE_MSB 0 +#define WLAN_GPIO_PIN2_SOURCE_LSB 0 +#define WLAN_GPIO_PIN2_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN2_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN2_SOURCE_MASK) >> WLAN_GPIO_PIN2_SOURCE_LSB) +#define WLAN_GPIO_PIN2_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN2_SOURCE_LSB) & WLAN_GPIO_PIN2_SOURCE_MASK) + +#define WLAN_GPIO_PIN3_ADDRESS 0x00000034 +#define WLAN_GPIO_PIN3_OFFSET 0x00000034 +#define WLAN_GPIO_PIN3_CONFIG_MSB 13 +#define WLAN_GPIO_PIN3_CONFIG_LSB 11 +#define WLAN_GPIO_PIN3_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN3_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN3_CONFIG_MASK) >> WLAN_GPIO_PIN3_CONFIG_LSB) +#define WLAN_GPIO_PIN3_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN3_CONFIG_LSB) & WLAN_GPIO_PIN3_CONFIG_MASK) +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN3_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN3_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN3_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN3_INT_TYPE_MASK) >> WLAN_GPIO_PIN3_INT_TYPE_LSB) +#define WLAN_GPIO_PIN3_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN3_INT_TYPE_LSB) & WLAN_GPIO_PIN3_INT_TYPE_MASK) +#define WLAN_GPIO_PIN3_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN3_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN3_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN3_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_PULL_MASK) >> WLAN_GPIO_PIN3_PAD_PULL_LSB) +#define WLAN_GPIO_PIN3_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_PULL_LSB) & WLAN_GPIO_PIN3_PAD_PULL_MASK) +#define WLAN_GPIO_PIN3_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN3_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN3_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN3_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN3_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN3_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_DRIVER_LSB) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN3_SOURCE_MSB 0 +#define WLAN_GPIO_PIN3_SOURCE_LSB 0 +#define WLAN_GPIO_PIN3_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN3_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN3_SOURCE_MASK) >> WLAN_GPIO_PIN3_SOURCE_LSB) +#define WLAN_GPIO_PIN3_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN3_SOURCE_LSB) & WLAN_GPIO_PIN3_SOURCE_MASK) + +#define WLAN_GPIO_PIN4_ADDRESS 0x00000038 +#define WLAN_GPIO_PIN4_OFFSET 0x00000038 +#define WLAN_GPIO_PIN4_CONFIG_MSB 13 +#define WLAN_GPIO_PIN4_CONFIG_LSB 11 +#define WLAN_GPIO_PIN4_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN4_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN4_CONFIG_MASK) >> WLAN_GPIO_PIN4_CONFIG_LSB) +#define WLAN_GPIO_PIN4_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN4_CONFIG_LSB) & WLAN_GPIO_PIN4_CONFIG_MASK) +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN4_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN4_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN4_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN4_INT_TYPE_MASK) >> WLAN_GPIO_PIN4_INT_TYPE_LSB) +#define WLAN_GPIO_PIN4_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN4_INT_TYPE_LSB) & WLAN_GPIO_PIN4_INT_TYPE_MASK) +#define WLAN_GPIO_PIN4_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN4_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN4_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN4_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_PULL_MASK) >> WLAN_GPIO_PIN4_PAD_PULL_LSB) +#define WLAN_GPIO_PIN4_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_PULL_LSB) & WLAN_GPIO_PIN4_PAD_PULL_MASK) +#define WLAN_GPIO_PIN4_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN4_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN4_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN4_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN4_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN4_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_DRIVER_LSB) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN4_SOURCE_MSB 0 +#define WLAN_GPIO_PIN4_SOURCE_LSB 0 +#define WLAN_GPIO_PIN4_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN4_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN4_SOURCE_MASK) >> WLAN_GPIO_PIN4_SOURCE_LSB) +#define WLAN_GPIO_PIN4_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN4_SOURCE_LSB) & WLAN_GPIO_PIN4_SOURCE_MASK) + +#define WLAN_GPIO_PIN5_ADDRESS 0x0000003c +#define WLAN_GPIO_PIN5_OFFSET 0x0000003c +#define WLAN_GPIO_PIN5_CONFIG_MSB 13 +#define WLAN_GPIO_PIN5_CONFIG_LSB 11 +#define WLAN_GPIO_PIN5_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN5_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN5_CONFIG_MASK) >> WLAN_GPIO_PIN5_CONFIG_LSB) +#define WLAN_GPIO_PIN5_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN5_CONFIG_LSB) & WLAN_GPIO_PIN5_CONFIG_MASK) +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN5_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN5_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN5_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN5_INT_TYPE_MASK) >> WLAN_GPIO_PIN5_INT_TYPE_LSB) +#define WLAN_GPIO_PIN5_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN5_INT_TYPE_LSB) & WLAN_GPIO_PIN5_INT_TYPE_MASK) +#define WLAN_GPIO_PIN5_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN5_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN5_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN5_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_PULL_MASK) >> WLAN_GPIO_PIN5_PAD_PULL_LSB) +#define WLAN_GPIO_PIN5_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_PULL_LSB) & WLAN_GPIO_PIN5_PAD_PULL_MASK) +#define WLAN_GPIO_PIN5_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN5_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN5_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN5_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN5_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN5_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_DRIVER_LSB) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN5_SOURCE_MSB 0 +#define WLAN_GPIO_PIN5_SOURCE_LSB 0 +#define WLAN_GPIO_PIN5_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN5_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN5_SOURCE_MASK) >> WLAN_GPIO_PIN5_SOURCE_LSB) +#define WLAN_GPIO_PIN5_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN5_SOURCE_LSB) & WLAN_GPIO_PIN5_SOURCE_MASK) + +#define WLAN_GPIO_PIN6_ADDRESS 0x00000040 +#define WLAN_GPIO_PIN6_OFFSET 0x00000040 +#define WLAN_GPIO_PIN6_CONFIG_MSB 13 +#define WLAN_GPIO_PIN6_CONFIG_LSB 11 +#define WLAN_GPIO_PIN6_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN6_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN6_CONFIG_MASK) >> WLAN_GPIO_PIN6_CONFIG_LSB) +#define WLAN_GPIO_PIN6_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN6_CONFIG_LSB) & WLAN_GPIO_PIN6_CONFIG_MASK) +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN6_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN6_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN6_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN6_INT_TYPE_MASK) >> WLAN_GPIO_PIN6_INT_TYPE_LSB) +#define WLAN_GPIO_PIN6_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN6_INT_TYPE_LSB) & WLAN_GPIO_PIN6_INT_TYPE_MASK) +#define WLAN_GPIO_PIN6_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN6_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN6_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN6_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_PULL_MASK) >> WLAN_GPIO_PIN6_PAD_PULL_LSB) +#define WLAN_GPIO_PIN6_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_PULL_LSB) & WLAN_GPIO_PIN6_PAD_PULL_MASK) +#define WLAN_GPIO_PIN6_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN6_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN6_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN6_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN6_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN6_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_DRIVER_LSB) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN6_SOURCE_MSB 0 +#define WLAN_GPIO_PIN6_SOURCE_LSB 0 +#define WLAN_GPIO_PIN6_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN6_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN6_SOURCE_MASK) >> WLAN_GPIO_PIN6_SOURCE_LSB) +#define WLAN_GPIO_PIN6_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN6_SOURCE_LSB) & WLAN_GPIO_PIN6_SOURCE_MASK) + +#define WLAN_GPIO_PIN7_ADDRESS 0x00000044 +#define WLAN_GPIO_PIN7_OFFSET 0x00000044 +#define WLAN_GPIO_PIN7_CONFIG_MSB 13 +#define WLAN_GPIO_PIN7_CONFIG_LSB 11 +#define WLAN_GPIO_PIN7_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN7_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN7_CONFIG_MASK) >> WLAN_GPIO_PIN7_CONFIG_LSB) +#define WLAN_GPIO_PIN7_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN7_CONFIG_LSB) & WLAN_GPIO_PIN7_CONFIG_MASK) +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN7_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN7_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN7_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN7_INT_TYPE_MASK) >> WLAN_GPIO_PIN7_INT_TYPE_LSB) +#define WLAN_GPIO_PIN7_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN7_INT_TYPE_LSB) & WLAN_GPIO_PIN7_INT_TYPE_MASK) +#define WLAN_GPIO_PIN7_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN7_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN7_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN7_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_PULL_MASK) >> WLAN_GPIO_PIN7_PAD_PULL_LSB) +#define WLAN_GPIO_PIN7_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_PULL_LSB) & WLAN_GPIO_PIN7_PAD_PULL_MASK) +#define WLAN_GPIO_PIN7_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN7_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN7_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN7_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN7_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN7_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_DRIVER_LSB) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN7_SOURCE_MSB 0 +#define WLAN_GPIO_PIN7_SOURCE_LSB 0 +#define WLAN_GPIO_PIN7_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN7_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN7_SOURCE_MASK) >> WLAN_GPIO_PIN7_SOURCE_LSB) +#define WLAN_GPIO_PIN7_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN7_SOURCE_LSB) & WLAN_GPIO_PIN7_SOURCE_MASK) + +#define WLAN_GPIO_PIN8_ADDRESS 0x00000048 +#define WLAN_GPIO_PIN8_OFFSET 0x00000048 +#define WLAN_GPIO_PIN8_CONFIG_MSB 13 +#define WLAN_GPIO_PIN8_CONFIG_LSB 11 +#define WLAN_GPIO_PIN8_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN8_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN8_CONFIG_MASK) >> WLAN_GPIO_PIN8_CONFIG_LSB) +#define WLAN_GPIO_PIN8_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN8_CONFIG_LSB) & WLAN_GPIO_PIN8_CONFIG_MASK) +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN8_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN8_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN8_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN8_INT_TYPE_MASK) >> WLAN_GPIO_PIN8_INT_TYPE_LSB) +#define WLAN_GPIO_PIN8_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN8_INT_TYPE_LSB) & WLAN_GPIO_PIN8_INT_TYPE_MASK) +#define WLAN_GPIO_PIN8_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN8_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN8_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN8_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_PULL_MASK) >> WLAN_GPIO_PIN8_PAD_PULL_LSB) +#define WLAN_GPIO_PIN8_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_PULL_LSB) & WLAN_GPIO_PIN8_PAD_PULL_MASK) +#define WLAN_GPIO_PIN8_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN8_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN8_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN8_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN8_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN8_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_DRIVER_LSB) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN8_SOURCE_MSB 0 +#define WLAN_GPIO_PIN8_SOURCE_LSB 0 +#define WLAN_GPIO_PIN8_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN8_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN8_SOURCE_MASK) >> WLAN_GPIO_PIN8_SOURCE_LSB) +#define WLAN_GPIO_PIN8_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN8_SOURCE_LSB) & WLAN_GPIO_PIN8_SOURCE_MASK) + +#define WLAN_GPIO_PIN9_ADDRESS 0x0000004c +#define WLAN_GPIO_PIN9_OFFSET 0x0000004c +#define WLAN_GPIO_PIN9_CONFIG_MSB 13 +#define WLAN_GPIO_PIN9_CONFIG_LSB 11 +#define WLAN_GPIO_PIN9_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN9_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN9_CONFIG_MASK) >> WLAN_GPIO_PIN9_CONFIG_LSB) +#define WLAN_GPIO_PIN9_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN9_CONFIG_LSB) & WLAN_GPIO_PIN9_CONFIG_MASK) +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN9_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN9_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN9_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN9_INT_TYPE_MASK) >> WLAN_GPIO_PIN9_INT_TYPE_LSB) +#define WLAN_GPIO_PIN9_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN9_INT_TYPE_LSB) & WLAN_GPIO_PIN9_INT_TYPE_MASK) +#define WLAN_GPIO_PIN9_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN9_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN9_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN9_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_PULL_MASK) >> WLAN_GPIO_PIN9_PAD_PULL_LSB) +#define WLAN_GPIO_PIN9_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_PULL_LSB) & WLAN_GPIO_PIN9_PAD_PULL_MASK) +#define WLAN_GPIO_PIN9_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN9_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN9_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN9_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN9_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN9_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_DRIVER_LSB) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN9_SOURCE_MSB 0 +#define WLAN_GPIO_PIN9_SOURCE_LSB 0 +#define WLAN_GPIO_PIN9_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN9_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN9_SOURCE_MASK) >> WLAN_GPIO_PIN9_SOURCE_LSB) +#define WLAN_GPIO_PIN9_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN9_SOURCE_LSB) & WLAN_GPIO_PIN9_SOURCE_MASK) + +#define WLAN_GPIO_PIN10_ADDRESS 0x00000050 +#define WLAN_GPIO_PIN10_OFFSET 0x00000050 +#define WLAN_GPIO_PIN10_CONFIG_MSB 13 +#define WLAN_GPIO_PIN10_CONFIG_LSB 11 +#define WLAN_GPIO_PIN10_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN10_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN10_CONFIG_MASK) >> WLAN_GPIO_PIN10_CONFIG_LSB) +#define WLAN_GPIO_PIN10_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN10_CONFIG_LSB) & WLAN_GPIO_PIN10_CONFIG_MASK) +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN10_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN10_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN10_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN10_INT_TYPE_MASK) >> WLAN_GPIO_PIN10_INT_TYPE_LSB) +#define WLAN_GPIO_PIN10_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN10_INT_TYPE_LSB) & WLAN_GPIO_PIN10_INT_TYPE_MASK) +#define WLAN_GPIO_PIN10_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN10_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN10_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN10_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_PULL_MASK) >> WLAN_GPIO_PIN10_PAD_PULL_LSB) +#define WLAN_GPIO_PIN10_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_PULL_LSB) & WLAN_GPIO_PIN10_PAD_PULL_MASK) +#define WLAN_GPIO_PIN10_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN10_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN10_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN10_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN10_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN10_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_DRIVER_LSB) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN10_SOURCE_MSB 0 +#define WLAN_GPIO_PIN10_SOURCE_LSB 0 +#define WLAN_GPIO_PIN10_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN10_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN10_SOURCE_MASK) >> WLAN_GPIO_PIN10_SOURCE_LSB) +#define WLAN_GPIO_PIN10_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN10_SOURCE_LSB) & WLAN_GPIO_PIN10_SOURCE_MASK) + +#define WLAN_GPIO_PIN11_ADDRESS 0x00000054 +#define WLAN_GPIO_PIN11_OFFSET 0x00000054 +#define WLAN_GPIO_PIN11_CONFIG_MSB 13 +#define WLAN_GPIO_PIN11_CONFIG_LSB 11 +#define WLAN_GPIO_PIN11_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN11_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN11_CONFIG_MASK) >> WLAN_GPIO_PIN11_CONFIG_LSB) +#define WLAN_GPIO_PIN11_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN11_CONFIG_LSB) & WLAN_GPIO_PIN11_CONFIG_MASK) +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN11_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN11_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN11_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN11_INT_TYPE_MASK) >> WLAN_GPIO_PIN11_INT_TYPE_LSB) +#define WLAN_GPIO_PIN11_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN11_INT_TYPE_LSB) & WLAN_GPIO_PIN11_INT_TYPE_MASK) +#define WLAN_GPIO_PIN11_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN11_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN11_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN11_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_PULL_MASK) >> WLAN_GPIO_PIN11_PAD_PULL_LSB) +#define WLAN_GPIO_PIN11_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_PULL_LSB) & WLAN_GPIO_PIN11_PAD_PULL_MASK) +#define WLAN_GPIO_PIN11_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN11_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN11_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN11_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN11_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN11_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_DRIVER_LSB) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN11_SOURCE_MSB 0 +#define WLAN_GPIO_PIN11_SOURCE_LSB 0 +#define WLAN_GPIO_PIN11_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN11_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN11_SOURCE_MASK) >> WLAN_GPIO_PIN11_SOURCE_LSB) +#define WLAN_GPIO_PIN11_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN11_SOURCE_LSB) & WLAN_GPIO_PIN11_SOURCE_MASK) + +#define WLAN_GPIO_PIN12_ADDRESS 0x00000058 +#define WLAN_GPIO_PIN12_OFFSET 0x00000058 +#define WLAN_GPIO_PIN12_CONFIG_MSB 13 +#define WLAN_GPIO_PIN12_CONFIG_LSB 11 +#define WLAN_GPIO_PIN12_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN12_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN12_CONFIG_MASK) >> WLAN_GPIO_PIN12_CONFIG_LSB) +#define WLAN_GPIO_PIN12_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN12_CONFIG_LSB) & WLAN_GPIO_PIN12_CONFIG_MASK) +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN12_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN12_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN12_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN12_INT_TYPE_MASK) >> WLAN_GPIO_PIN12_INT_TYPE_LSB) +#define WLAN_GPIO_PIN12_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN12_INT_TYPE_LSB) & WLAN_GPIO_PIN12_INT_TYPE_MASK) +#define WLAN_GPIO_PIN12_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN12_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN12_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN12_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_PULL_MASK) >> WLAN_GPIO_PIN12_PAD_PULL_LSB) +#define WLAN_GPIO_PIN12_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_PULL_LSB) & WLAN_GPIO_PIN12_PAD_PULL_MASK) +#define WLAN_GPIO_PIN12_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN12_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN12_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN12_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN12_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN12_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_DRIVER_LSB) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN12_SOURCE_MSB 0 +#define WLAN_GPIO_PIN12_SOURCE_LSB 0 +#define WLAN_GPIO_PIN12_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN12_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN12_SOURCE_MASK) >> WLAN_GPIO_PIN12_SOURCE_LSB) +#define WLAN_GPIO_PIN12_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN12_SOURCE_LSB) & WLAN_GPIO_PIN12_SOURCE_MASK) + +#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c +#define WLAN_GPIO_PIN13_OFFSET 0x0000005c +#define WLAN_GPIO_PIN13_CONFIG_MSB 13 +#define WLAN_GPIO_PIN13_CONFIG_LSB 11 +#define WLAN_GPIO_PIN13_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN13_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN13_CONFIG_MASK) >> WLAN_GPIO_PIN13_CONFIG_LSB) +#define WLAN_GPIO_PIN13_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN13_CONFIG_LSB) & WLAN_GPIO_PIN13_CONFIG_MASK) +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN13_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN13_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN13_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN13_INT_TYPE_MASK) >> WLAN_GPIO_PIN13_INT_TYPE_LSB) +#define WLAN_GPIO_PIN13_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN13_INT_TYPE_LSB) & WLAN_GPIO_PIN13_INT_TYPE_MASK) +#define WLAN_GPIO_PIN13_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN13_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN13_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN13_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_PULL_MASK) >> WLAN_GPIO_PIN13_PAD_PULL_LSB) +#define WLAN_GPIO_PIN13_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_PULL_LSB) & WLAN_GPIO_PIN13_PAD_PULL_MASK) +#define WLAN_GPIO_PIN13_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN13_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN13_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN13_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN13_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN13_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_DRIVER_LSB) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN13_SOURCE_MSB 0 +#define WLAN_GPIO_PIN13_SOURCE_LSB 0 +#define WLAN_GPIO_PIN13_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN13_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN13_SOURCE_MASK) >> WLAN_GPIO_PIN13_SOURCE_LSB) +#define WLAN_GPIO_PIN13_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN13_SOURCE_LSB) & WLAN_GPIO_PIN13_SOURCE_MASK) + +#define WLAN_GPIO_PIN14_ADDRESS 0x00000060 +#define WLAN_GPIO_PIN14_OFFSET 0x00000060 +#define WLAN_GPIO_PIN14_CONFIG_MSB 13 +#define WLAN_GPIO_PIN14_CONFIG_LSB 11 +#define WLAN_GPIO_PIN14_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN14_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN14_CONFIG_MASK) >> WLAN_GPIO_PIN14_CONFIG_LSB) +#define WLAN_GPIO_PIN14_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN14_CONFIG_LSB) & WLAN_GPIO_PIN14_CONFIG_MASK) +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN14_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN14_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN14_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN14_INT_TYPE_MASK) >> WLAN_GPIO_PIN14_INT_TYPE_LSB) +#define WLAN_GPIO_PIN14_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN14_INT_TYPE_LSB) & WLAN_GPIO_PIN14_INT_TYPE_MASK) +#define WLAN_GPIO_PIN14_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN14_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN14_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN14_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_PULL_MASK) >> WLAN_GPIO_PIN14_PAD_PULL_LSB) +#define WLAN_GPIO_PIN14_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_PULL_LSB) & WLAN_GPIO_PIN14_PAD_PULL_MASK) +#define WLAN_GPIO_PIN14_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN14_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN14_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN14_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN14_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN14_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_DRIVER_LSB) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN14_SOURCE_MSB 0 +#define WLAN_GPIO_PIN14_SOURCE_LSB 0 +#define WLAN_GPIO_PIN14_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN14_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN14_SOURCE_MASK) >> WLAN_GPIO_PIN14_SOURCE_LSB) +#define WLAN_GPIO_PIN14_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN14_SOURCE_LSB) & WLAN_GPIO_PIN14_SOURCE_MASK) + +#define WLAN_GPIO_PIN15_ADDRESS 0x00000064 +#define WLAN_GPIO_PIN15_OFFSET 0x00000064 +#define WLAN_GPIO_PIN15_CONFIG_MSB 13 +#define WLAN_GPIO_PIN15_CONFIG_LSB 11 +#define WLAN_GPIO_PIN15_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN15_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN15_CONFIG_MASK) >> WLAN_GPIO_PIN15_CONFIG_LSB) +#define WLAN_GPIO_PIN15_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN15_CONFIG_LSB) & WLAN_GPIO_PIN15_CONFIG_MASK) +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN15_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN15_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN15_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN15_INT_TYPE_MASK) >> WLAN_GPIO_PIN15_INT_TYPE_LSB) +#define WLAN_GPIO_PIN15_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN15_INT_TYPE_LSB) & WLAN_GPIO_PIN15_INT_TYPE_MASK) +#define WLAN_GPIO_PIN15_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN15_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN15_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN15_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_PULL_MASK) >> WLAN_GPIO_PIN15_PAD_PULL_LSB) +#define WLAN_GPIO_PIN15_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_PULL_LSB) & WLAN_GPIO_PIN15_PAD_PULL_MASK) +#define WLAN_GPIO_PIN15_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN15_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN15_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN15_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN15_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN15_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_DRIVER_LSB) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN15_SOURCE_MSB 0 +#define WLAN_GPIO_PIN15_SOURCE_LSB 0 +#define WLAN_GPIO_PIN15_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN15_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN15_SOURCE_MASK) >> WLAN_GPIO_PIN15_SOURCE_LSB) +#define WLAN_GPIO_PIN15_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN15_SOURCE_LSB) & WLAN_GPIO_PIN15_SOURCE_MASK) + +#define WLAN_GPIO_PIN16_ADDRESS 0x00000068 +#define WLAN_GPIO_PIN16_OFFSET 0x00000068 +#define WLAN_GPIO_PIN16_CONFIG_MSB 13 +#define WLAN_GPIO_PIN16_CONFIG_LSB 11 +#define WLAN_GPIO_PIN16_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN16_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN16_CONFIG_MASK) >> WLAN_GPIO_PIN16_CONFIG_LSB) +#define WLAN_GPIO_PIN16_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN16_CONFIG_LSB) & WLAN_GPIO_PIN16_CONFIG_MASK) +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN16_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN16_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN16_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN16_INT_TYPE_MASK) >> WLAN_GPIO_PIN16_INT_TYPE_LSB) +#define WLAN_GPIO_PIN16_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN16_INT_TYPE_LSB) & WLAN_GPIO_PIN16_INT_TYPE_MASK) +#define WLAN_GPIO_PIN16_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN16_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN16_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN16_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_PULL_MASK) >> WLAN_GPIO_PIN16_PAD_PULL_LSB) +#define WLAN_GPIO_PIN16_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_PULL_LSB) & WLAN_GPIO_PIN16_PAD_PULL_MASK) +#define WLAN_GPIO_PIN16_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN16_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN16_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN16_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN16_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN16_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_DRIVER_LSB) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN16_SOURCE_MSB 0 +#define WLAN_GPIO_PIN16_SOURCE_LSB 0 +#define WLAN_GPIO_PIN16_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN16_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN16_SOURCE_MASK) >> WLAN_GPIO_PIN16_SOURCE_LSB) +#define WLAN_GPIO_PIN16_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN16_SOURCE_LSB) & WLAN_GPIO_PIN16_SOURCE_MASK) + +#define WLAN_GPIO_PIN17_ADDRESS 0x0000006c +#define WLAN_GPIO_PIN17_OFFSET 0x0000006c +#define WLAN_GPIO_PIN17_CONFIG_MSB 13 +#define WLAN_GPIO_PIN17_CONFIG_LSB 11 +#define WLAN_GPIO_PIN17_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN17_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN17_CONFIG_MASK) >> WLAN_GPIO_PIN17_CONFIG_LSB) +#define WLAN_GPIO_PIN17_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN17_CONFIG_LSB) & WLAN_GPIO_PIN17_CONFIG_MASK) +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN17_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN17_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN17_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN17_INT_TYPE_MASK) >> WLAN_GPIO_PIN17_INT_TYPE_LSB) +#define WLAN_GPIO_PIN17_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN17_INT_TYPE_LSB) & WLAN_GPIO_PIN17_INT_TYPE_MASK) +#define WLAN_GPIO_PIN17_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN17_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN17_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN17_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_PULL_MASK) >> WLAN_GPIO_PIN17_PAD_PULL_LSB) +#define WLAN_GPIO_PIN17_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_PULL_LSB) & WLAN_GPIO_PIN17_PAD_PULL_MASK) +#define WLAN_GPIO_PIN17_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN17_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN17_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN17_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN17_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN17_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_DRIVER_LSB) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN17_SOURCE_MSB 0 +#define WLAN_GPIO_PIN17_SOURCE_LSB 0 +#define WLAN_GPIO_PIN17_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN17_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN17_SOURCE_MASK) >> WLAN_GPIO_PIN17_SOURCE_LSB) +#define WLAN_GPIO_PIN17_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN17_SOURCE_LSB) & WLAN_GPIO_PIN17_SOURCE_MASK) + +#define WLAN_GPIO_PIN18_ADDRESS 0x00000070 +#define WLAN_GPIO_PIN18_OFFSET 0x00000070 +#define WLAN_GPIO_PIN18_CONFIG_MSB 13 +#define WLAN_GPIO_PIN18_CONFIG_LSB 11 +#define WLAN_GPIO_PIN18_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN18_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN18_CONFIG_MASK) >> WLAN_GPIO_PIN18_CONFIG_LSB) +#define WLAN_GPIO_PIN18_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN18_CONFIG_LSB) & WLAN_GPIO_PIN18_CONFIG_MASK) +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN18_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN18_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN18_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN18_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN18_INT_TYPE_MASK) >> WLAN_GPIO_PIN18_INT_TYPE_LSB) +#define WLAN_GPIO_PIN18_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN18_INT_TYPE_LSB) & WLAN_GPIO_PIN18_INT_TYPE_MASK) +#define WLAN_GPIO_PIN18_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN18_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN18_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN18_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_PULL_MASK) >> WLAN_GPIO_PIN18_PAD_PULL_LSB) +#define WLAN_GPIO_PIN18_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_PULL_LSB) & WLAN_GPIO_PIN18_PAD_PULL_MASK) +#define WLAN_GPIO_PIN18_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN18_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN18_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN18_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN18_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN18_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN18_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN18_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN18_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_DRIVER_LSB) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN18_SOURCE_MSB 0 +#define WLAN_GPIO_PIN18_SOURCE_LSB 0 +#define WLAN_GPIO_PIN18_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN18_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN18_SOURCE_MASK) >> WLAN_GPIO_PIN18_SOURCE_LSB) +#define WLAN_GPIO_PIN18_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN18_SOURCE_LSB) & WLAN_GPIO_PIN18_SOURCE_MASK) + +#define WLAN_GPIO_PIN19_ADDRESS 0x00000074 +#define WLAN_GPIO_PIN19_OFFSET 0x00000074 +#define WLAN_GPIO_PIN19_CONFIG_MSB 13 +#define WLAN_GPIO_PIN19_CONFIG_LSB 11 +#define WLAN_GPIO_PIN19_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN19_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN19_CONFIG_MASK) >> WLAN_GPIO_PIN19_CONFIG_LSB) +#define WLAN_GPIO_PIN19_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN19_CONFIG_LSB) & WLAN_GPIO_PIN19_CONFIG_MASK) +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN19_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN19_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN19_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN19_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN19_INT_TYPE_MASK) >> WLAN_GPIO_PIN19_INT_TYPE_LSB) +#define WLAN_GPIO_PIN19_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN19_INT_TYPE_LSB) & WLAN_GPIO_PIN19_INT_TYPE_MASK) +#define WLAN_GPIO_PIN19_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN19_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN19_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN19_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_PULL_MASK) >> WLAN_GPIO_PIN19_PAD_PULL_LSB) +#define WLAN_GPIO_PIN19_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_PULL_LSB) & WLAN_GPIO_PIN19_PAD_PULL_MASK) +#define WLAN_GPIO_PIN19_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN19_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN19_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN19_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN19_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN19_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN19_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN19_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN19_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_DRIVER_LSB) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN19_SOURCE_MSB 0 +#define WLAN_GPIO_PIN19_SOURCE_LSB 0 +#define WLAN_GPIO_PIN19_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN19_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN19_SOURCE_MASK) >> WLAN_GPIO_PIN19_SOURCE_LSB) +#define WLAN_GPIO_PIN19_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN19_SOURCE_LSB) & WLAN_GPIO_PIN19_SOURCE_MASK) + +#define WLAN_GPIO_PIN20_ADDRESS 0x00000078 +#define WLAN_GPIO_PIN20_OFFSET 0x00000078 +#define WLAN_GPIO_PIN20_CONFIG_MSB 13 +#define WLAN_GPIO_PIN20_CONFIG_LSB 11 +#define WLAN_GPIO_PIN20_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN20_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN20_CONFIG_MASK) >> WLAN_GPIO_PIN20_CONFIG_LSB) +#define WLAN_GPIO_PIN20_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN20_CONFIG_LSB) & WLAN_GPIO_PIN20_CONFIG_MASK) +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN20_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN20_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN20_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN20_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN20_INT_TYPE_MASK) >> WLAN_GPIO_PIN20_INT_TYPE_LSB) +#define WLAN_GPIO_PIN20_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN20_INT_TYPE_LSB) & WLAN_GPIO_PIN20_INT_TYPE_MASK) +#define WLAN_GPIO_PIN20_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN20_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN20_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN20_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_PULL_MASK) >> WLAN_GPIO_PIN20_PAD_PULL_LSB) +#define WLAN_GPIO_PIN20_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_PULL_LSB) & WLAN_GPIO_PIN20_PAD_PULL_MASK) +#define WLAN_GPIO_PIN20_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN20_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN20_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN20_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN20_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN20_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN20_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN20_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN20_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_DRIVER_LSB) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN20_SOURCE_MSB 0 +#define WLAN_GPIO_PIN20_SOURCE_LSB 0 +#define WLAN_GPIO_PIN20_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN20_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN20_SOURCE_MASK) >> WLAN_GPIO_PIN20_SOURCE_LSB) +#define WLAN_GPIO_PIN20_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN20_SOURCE_LSB) & WLAN_GPIO_PIN20_SOURCE_MASK) + +#define WLAN_GPIO_PIN21_ADDRESS 0x0000007c +#define WLAN_GPIO_PIN21_OFFSET 0x0000007c +#define WLAN_GPIO_PIN21_CONFIG_MSB 13 +#define WLAN_GPIO_PIN21_CONFIG_LSB 11 +#define WLAN_GPIO_PIN21_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN21_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN21_CONFIG_MASK) >> WLAN_GPIO_PIN21_CONFIG_LSB) +#define WLAN_GPIO_PIN21_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN21_CONFIG_LSB) & WLAN_GPIO_PIN21_CONFIG_MASK) +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN21_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN21_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN21_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN21_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN21_INT_TYPE_MASK) >> WLAN_GPIO_PIN21_INT_TYPE_LSB) +#define WLAN_GPIO_PIN21_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN21_INT_TYPE_LSB) & WLAN_GPIO_PIN21_INT_TYPE_MASK) +#define WLAN_GPIO_PIN21_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN21_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN21_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN21_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_PULL_MASK) >> WLAN_GPIO_PIN21_PAD_PULL_LSB) +#define WLAN_GPIO_PIN21_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_PULL_LSB) & WLAN_GPIO_PIN21_PAD_PULL_MASK) +#define WLAN_GPIO_PIN21_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN21_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN21_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN21_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN21_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN21_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN21_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN21_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN21_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_DRIVER_LSB) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN21_SOURCE_MSB 0 +#define WLAN_GPIO_PIN21_SOURCE_LSB 0 +#define WLAN_GPIO_PIN21_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN21_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN21_SOURCE_MASK) >> WLAN_GPIO_PIN21_SOURCE_LSB) +#define WLAN_GPIO_PIN21_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN21_SOURCE_LSB) & WLAN_GPIO_PIN21_SOURCE_MASK) + +#define WLAN_GPIO_PIN22_ADDRESS 0x00000080 +#define WLAN_GPIO_PIN22_OFFSET 0x00000080 +#define WLAN_GPIO_PIN22_CONFIG_MSB 13 +#define WLAN_GPIO_PIN22_CONFIG_LSB 11 +#define WLAN_GPIO_PIN22_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN22_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN22_CONFIG_MASK) >> WLAN_GPIO_PIN22_CONFIG_LSB) +#define WLAN_GPIO_PIN22_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN22_CONFIG_LSB) & WLAN_GPIO_PIN22_CONFIG_MASK) +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN22_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN22_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN22_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN22_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN22_INT_TYPE_MASK) >> WLAN_GPIO_PIN22_INT_TYPE_LSB) +#define WLAN_GPIO_PIN22_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN22_INT_TYPE_LSB) & WLAN_GPIO_PIN22_INT_TYPE_MASK) +#define WLAN_GPIO_PIN22_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN22_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN22_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN22_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_PULL_MASK) >> WLAN_GPIO_PIN22_PAD_PULL_LSB) +#define WLAN_GPIO_PIN22_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_PULL_LSB) & WLAN_GPIO_PIN22_PAD_PULL_MASK) +#define WLAN_GPIO_PIN22_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN22_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN22_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN22_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN22_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN22_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN22_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN22_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN22_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_DRIVER_LSB) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN22_SOURCE_MSB 0 +#define WLAN_GPIO_PIN22_SOURCE_LSB 0 +#define WLAN_GPIO_PIN22_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN22_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN22_SOURCE_MASK) >> WLAN_GPIO_PIN22_SOURCE_LSB) +#define WLAN_GPIO_PIN22_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN22_SOURCE_LSB) & WLAN_GPIO_PIN22_SOURCE_MASK) + +#define WLAN_GPIO_PIN23_ADDRESS 0x00000084 +#define WLAN_GPIO_PIN23_OFFSET 0x00000084 +#define WLAN_GPIO_PIN23_CONFIG_MSB 13 +#define WLAN_GPIO_PIN23_CONFIG_LSB 11 +#define WLAN_GPIO_PIN23_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN23_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN23_CONFIG_MASK) >> WLAN_GPIO_PIN23_CONFIG_LSB) +#define WLAN_GPIO_PIN23_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN23_CONFIG_LSB) & WLAN_GPIO_PIN23_CONFIG_MASK) +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN23_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN23_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN23_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN23_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN23_INT_TYPE_MASK) >> WLAN_GPIO_PIN23_INT_TYPE_LSB) +#define WLAN_GPIO_PIN23_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN23_INT_TYPE_LSB) & WLAN_GPIO_PIN23_INT_TYPE_MASK) +#define WLAN_GPIO_PIN23_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN23_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN23_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN23_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN23_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN23_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN23_PAD_DRIVER_LSB) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN23_SOURCE_MSB 0 +#define WLAN_GPIO_PIN23_SOURCE_LSB 0 +#define WLAN_GPIO_PIN23_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN23_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN23_SOURCE_MASK) >> WLAN_GPIO_PIN23_SOURCE_LSB) +#define WLAN_GPIO_PIN23_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN23_SOURCE_LSB) & WLAN_GPIO_PIN23_SOURCE_MASK) + +#define WLAN_GPIO_PIN24_ADDRESS 0x00000088 +#define WLAN_GPIO_PIN24_OFFSET 0x00000088 +#define WLAN_GPIO_PIN24_CONFIG_MSB 13 +#define WLAN_GPIO_PIN24_CONFIG_LSB 11 +#define WLAN_GPIO_PIN24_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN24_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN24_CONFIG_MASK) >> WLAN_GPIO_PIN24_CONFIG_LSB) +#define WLAN_GPIO_PIN24_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN24_CONFIG_LSB) & WLAN_GPIO_PIN24_CONFIG_MASK) +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN24_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN24_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN24_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN24_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN24_INT_TYPE_MASK) >> WLAN_GPIO_PIN24_INT_TYPE_LSB) +#define WLAN_GPIO_PIN24_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN24_INT_TYPE_LSB) & WLAN_GPIO_PIN24_INT_TYPE_MASK) +#define WLAN_GPIO_PIN24_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN24_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN24_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN24_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN24_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN24_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN24_PAD_DRIVER_LSB) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN24_SOURCE_MSB 0 +#define WLAN_GPIO_PIN24_SOURCE_LSB 0 +#define WLAN_GPIO_PIN24_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN24_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN24_SOURCE_MASK) >> WLAN_GPIO_PIN24_SOURCE_LSB) +#define WLAN_GPIO_PIN24_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN24_SOURCE_LSB) & WLAN_GPIO_PIN24_SOURCE_MASK) + +#define WLAN_GPIO_PIN25_ADDRESS 0x0000008c +#define WLAN_GPIO_PIN25_OFFSET 0x0000008c +#define WLAN_GPIO_PIN25_CONFIG_MSB 13 +#define WLAN_GPIO_PIN25_CONFIG_LSB 11 +#define WLAN_GPIO_PIN25_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN25_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN25_CONFIG_MASK) >> WLAN_GPIO_PIN25_CONFIG_LSB) +#define WLAN_GPIO_PIN25_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN25_CONFIG_LSB) & WLAN_GPIO_PIN25_CONFIG_MASK) +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN25_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN25_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN25_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN25_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN25_INT_TYPE_MASK) >> WLAN_GPIO_PIN25_INT_TYPE_LSB) +#define WLAN_GPIO_PIN25_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN25_INT_TYPE_LSB) & WLAN_GPIO_PIN25_INT_TYPE_MASK) +#define WLAN_GPIO_PIN25_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN25_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN25_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN25_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN25_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN25_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN25_PAD_DRIVER_LSB) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN25_SOURCE_MSB 0 +#define WLAN_GPIO_PIN25_SOURCE_LSB 0 +#define WLAN_GPIO_PIN25_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN25_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN25_SOURCE_MASK) >> WLAN_GPIO_PIN25_SOURCE_LSB) +#define WLAN_GPIO_PIN25_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN25_SOURCE_LSB) & WLAN_GPIO_PIN25_SOURCE_MASK) + +#define SDIO_ADDRESS 0x00000090 +#define SDIO_OFFSET 0x00000090 +#define SDIO_PINS_EN_MSB 0 +#define SDIO_PINS_EN_LSB 0 +#define SDIO_PINS_EN_MASK 0x00000001 +#define SDIO_PINS_EN_GET(x) (((x) & SDIO_PINS_EN_MASK) >> SDIO_PINS_EN_LSB) +#define SDIO_PINS_EN_SET(x) (((x) << SDIO_PINS_EN_LSB) & SDIO_PINS_EN_MASK) + +#define FUNC_BUS_ADDRESS 0x00000094 +#define FUNC_BUS_OFFSET 0x00000094 +#define FUNC_BUS_GPIO_MODE_MSB 22 +#define FUNC_BUS_GPIO_MODE_LSB 22 +#define FUNC_BUS_GPIO_MODE_MASK 0x00400000 +#define FUNC_BUS_GPIO_MODE_GET(x) (((x) & FUNC_BUS_GPIO_MODE_MASK) >> FUNC_BUS_GPIO_MODE_LSB) +#define FUNC_BUS_GPIO_MODE_SET(x) (((x) << FUNC_BUS_GPIO_MODE_LSB) & FUNC_BUS_GPIO_MODE_MASK) +#define FUNC_BUS_OE_L_MSB 21 +#define FUNC_BUS_OE_L_LSB 0 +#define FUNC_BUS_OE_L_MASK 0x003fffff +#define FUNC_BUS_OE_L_GET(x) (((x) & FUNC_BUS_OE_L_MASK) >> FUNC_BUS_OE_L_LSB) +#define FUNC_BUS_OE_L_SET(x) (((x) << FUNC_BUS_OE_L_LSB) & FUNC_BUS_OE_L_MASK) + +#define WL_SOC_APB_ADDRESS 0x00000098 +#define WL_SOC_APB_OFFSET 0x00000098 +#define WL_SOC_APB_TOGGLE_MSB 0 +#define WL_SOC_APB_TOGGLE_LSB 0 +#define WL_SOC_APB_TOGGLE_MASK 0x00000001 +#define WL_SOC_APB_TOGGLE_GET(x) (((x) & WL_SOC_APB_TOGGLE_MASK) >> WL_SOC_APB_TOGGLE_LSB) +#define WL_SOC_APB_TOGGLE_SET(x) (((x) << WL_SOC_APB_TOGGLE_LSB) & WL_SOC_APB_TOGGLE_MASK) + +#define WLAN_SIGMA_DELTA_ADDRESS 0x0000009c +#define WLAN_SIGMA_DELTA_OFFSET 0x0000009c +#define WLAN_SIGMA_DELTA_ENABLE_MSB 16 +#define WLAN_SIGMA_DELTA_ENABLE_LSB 16 +#define WLAN_SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define WLAN_SIGMA_DELTA_ENABLE_GET(x) (((x) & WLAN_SIGMA_DELTA_ENABLE_MASK) >> WLAN_SIGMA_DELTA_ENABLE_LSB) +#define WLAN_SIGMA_DELTA_ENABLE_SET(x) (((x) << WLAN_SIGMA_DELTA_ENABLE_LSB) & WLAN_SIGMA_DELTA_ENABLE_MASK) +#define WLAN_SIGMA_DELTA_PRESCALAR_MSB 15 +#define WLAN_SIGMA_DELTA_PRESCALAR_LSB 8 +#define WLAN_SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define WLAN_SIGMA_DELTA_PRESCALAR_GET(x) (((x) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) >> WLAN_SIGMA_DELTA_PRESCALAR_LSB) +#define WLAN_SIGMA_DELTA_PRESCALAR_SET(x) (((x) << WLAN_SIGMA_DELTA_PRESCALAR_LSB) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) +#define WLAN_SIGMA_DELTA_TARGET_MSB 7 +#define WLAN_SIGMA_DELTA_TARGET_LSB 0 +#define WLAN_SIGMA_DELTA_TARGET_MASK 0x000000ff +#define WLAN_SIGMA_DELTA_TARGET_GET(x) (((x) & WLAN_SIGMA_DELTA_TARGET_MASK) >> WLAN_SIGMA_DELTA_TARGET_LSB) +#define WLAN_SIGMA_DELTA_TARGET_SET(x) (((x) << WLAN_SIGMA_DELTA_TARGET_LSB) & WLAN_SIGMA_DELTA_TARGET_MASK) + +#define WL_BOOTSTRAP_ADDRESS 0x000000a0 +#define WL_BOOTSTRAP_OFFSET 0x000000a0 +#define WL_BOOTSTRAP_STATUS_MSB 22 +#define WL_BOOTSTRAP_STATUS_LSB 0 +#define WL_BOOTSTRAP_STATUS_MASK 0x007fffff +#define WL_BOOTSTRAP_STATUS_GET(x) (((x) & WL_BOOTSTRAP_STATUS_MASK) >> WL_BOOTSTRAP_STATUS_LSB) +#define WL_BOOTSTRAP_STATUS_SET(x) (((x) << WL_BOOTSTRAP_STATUS_LSB) & WL_BOOTSTRAP_STATUS_MASK) + +#define CLOCK_GPIO_ADDRESS 0x000000a4 +#define CLOCK_GPIO_OFFSET 0x000000a4 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_MSB 2 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_LSB 2 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_MASK 0x00000004 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_GET(x) (((x) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) >> CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) +#define CLOCK_GPIO_CLK_REQ_OUT_EN_SET(x) (((x) << CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) +#define CLOCK_GPIO_BT_CLK_REQ_EN_MSB 1 +#define CLOCK_GPIO_BT_CLK_REQ_EN_LSB 1 +#define CLOCK_GPIO_BT_CLK_REQ_EN_MASK 0x00000002 +#define CLOCK_GPIO_BT_CLK_REQ_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) >> CLOCK_GPIO_BT_CLK_REQ_EN_LSB) +#define CLOCK_GPIO_BT_CLK_REQ_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_REQ_EN_LSB) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) +#define CLOCK_GPIO_BT_CLK_OUT_EN_MSB 0 +#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 +#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0x00000001 +#define CLOCK_GPIO_BT_CLK_OUT_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) >> CLOCK_GPIO_BT_CLK_OUT_EN_LSB) +#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) + +#define WLAN_DEBUG_CONTROL_ADDRESS 0x000000a8 +#define WLAN_DEBUG_CONTROL_OFFSET 0x000000a8 +#define WLAN_DEBUG_CONTROL_ENABLE_MSB 0 +#define WLAN_DEBUG_CONTROL_ENABLE_LSB 0 +#define WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> WLAN_DEBUG_CONTROL_ENABLE_LSB) +#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & WLAN_DEBUG_CONTROL_ENABLE_MASK) + +#define WLAN_DEBUG_INPUT_SEL_ADDRESS 0x000000ac +#define WLAN_DEBUG_INPUT_SEL_OFFSET 0x000000ac +#define WLAN_DEBUG_INPUT_SEL_SHIFT_MSB 5 +#define WLAN_DEBUG_INPUT_SEL_SHIFT_LSB 4 +#define WLAN_DEBUG_INPUT_SEL_SHIFT_MASK 0x00000030 +#define WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) >> WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) +#define WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) +#define WLAN_DEBUG_INPUT_SEL_SRC_MSB 3 +#define WLAN_DEBUG_INPUT_SEL_SRC_LSB 0 +#define WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> WLAN_DEBUG_INPUT_SEL_SRC_LSB) +#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) + +#define WLAN_DEBUG_OUT_ADDRESS 0x000000b0 +#define WLAN_DEBUG_OUT_OFFSET 0x000000b0 +#define WLAN_DEBUG_OUT_DATA_MSB 17 +#define WLAN_DEBUG_OUT_DATA_LSB 0 +#define WLAN_DEBUG_OUT_DATA_MASK 0x0003ffff +#define WLAN_DEBUG_OUT_DATA_GET(x) (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) +#define WLAN_DEBUG_OUT_DATA_SET(x) (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) + +#define WLAN_RESET_TUPLE_STATUS_ADDRESS 0x000000b4 +#define WLAN_RESET_TUPLE_STATUS_OFFSET 0x000000b4 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + +#define ANTENNA_SLEEP_CONTROL_ADDRESS 0x000000b8 +#define ANTENNA_SLEEP_CONTROL_OFFSET 0x000000b8 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MSB 14 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB 10 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK 0x00007c00 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) >> ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) +#define ANTENNA_SLEEP_CONTROL_VALUE_MSB 9 +#define ANTENNA_SLEEP_CONTROL_VALUE_LSB 5 +#define ANTENNA_SLEEP_CONTROL_VALUE_MASK 0x000003e0 +#define ANTENNA_SLEEP_CONTROL_VALUE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) >> ANTENNA_SLEEP_CONTROL_VALUE_LSB) +#define ANTENNA_SLEEP_CONTROL_VALUE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_VALUE_LSB) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) +#define ANTENNA_SLEEP_CONTROL_ENABLE_MSB 4 +#define ANTENNA_SLEEP_CONTROL_ENABLE_LSB 0 +#define ANTENNA_SLEEP_CONTROL_ENABLE_MASK 0x0000001f +#define ANTENNA_SLEEP_CONTROL_ENABLE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) >> ANTENNA_SLEEP_CONTROL_ENABLE_LSB) +#define ANTENNA_SLEEP_CONTROL_ENABLE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_ENABLE_LSB) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct gpio_athr_wlan_reg_reg_s { + volatile unsigned int wlan_gpio_out; + volatile unsigned int wlan_gpio_out_w1ts; + volatile unsigned int wlan_gpio_out_w1tc; + volatile unsigned int wlan_gpio_enable; + volatile unsigned int wlan_gpio_enable_w1ts; + volatile unsigned int wlan_gpio_enable_w1tc; + volatile unsigned int wlan_gpio_in; + volatile unsigned int wlan_gpio_status; + volatile unsigned int wlan_gpio_status_w1ts; + volatile unsigned int wlan_gpio_status_w1tc; + volatile unsigned int wlan_gpio_pin0; + volatile unsigned int wlan_gpio_pin1; + volatile unsigned int wlan_gpio_pin2; + volatile unsigned int wlan_gpio_pin3; + volatile unsigned int wlan_gpio_pin4; + volatile unsigned int wlan_gpio_pin5; + volatile unsigned int wlan_gpio_pin6; + volatile unsigned int wlan_gpio_pin7; + volatile unsigned int wlan_gpio_pin8; + volatile unsigned int wlan_gpio_pin9; + volatile unsigned int wlan_gpio_pin10; + volatile unsigned int wlan_gpio_pin11; + volatile unsigned int wlan_gpio_pin12; + volatile unsigned int wlan_gpio_pin13; + volatile unsigned int wlan_gpio_pin14; + volatile unsigned int wlan_gpio_pin15; + volatile unsigned int wlan_gpio_pin16; + volatile unsigned int wlan_gpio_pin17; + volatile unsigned int wlan_gpio_pin18; + volatile unsigned int wlan_gpio_pin19; + volatile unsigned int wlan_gpio_pin20; + volatile unsigned int wlan_gpio_pin21; + volatile unsigned int wlan_gpio_pin22; + volatile unsigned int wlan_gpio_pin23; + volatile unsigned int wlan_gpio_pin24; + volatile unsigned int wlan_gpio_pin25; + volatile unsigned int sdio; + volatile unsigned int func_bus; + volatile unsigned int wl_soc_apb; + volatile unsigned int wlan_sigma_delta; + volatile unsigned int wl_bootstrap; + volatile unsigned int clock_gpio; + volatile unsigned int wlan_debug_control; + volatile unsigned int wlan_debug_input_sel; + volatile unsigned int wlan_debug_out; + volatile unsigned int wlan_reset_tuple_status; + volatile unsigned int antenna_sleep_control; +} gpio_athr_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_ATHR_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h new file mode 100644 index 000000000000..b3e7126e26a2 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h @@ -0,0 +1,1094 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "gpio_athr_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define GPIO_OUT_ADDRESS WLAN_GPIO_OUT_ADDRESS +#define GPIO_OUT_OFFSET WLAN_GPIO_OUT_OFFSET +#define GPIO_OUT_DATA_MSB WLAN_GPIO_OUT_DATA_MSB +#define GPIO_OUT_DATA_LSB WLAN_GPIO_OUT_DATA_LSB +#define GPIO_OUT_DATA_MASK WLAN_GPIO_OUT_DATA_MASK +#define GPIO_OUT_DATA_GET(x) WLAN_GPIO_OUT_DATA_GET(x) +#define GPIO_OUT_DATA_SET(x) WLAN_GPIO_OUT_DATA_SET(x) +#define GPIO_OUT_W1TS_ADDRESS WLAN_GPIO_OUT_W1TS_ADDRESS +#define GPIO_OUT_W1TS_OFFSET WLAN_GPIO_OUT_W1TS_OFFSET +#define GPIO_OUT_W1TS_DATA_MSB WLAN_GPIO_OUT_W1TS_DATA_MSB +#define GPIO_OUT_W1TS_DATA_LSB WLAN_GPIO_OUT_W1TS_DATA_LSB +#define GPIO_OUT_W1TS_DATA_MASK WLAN_GPIO_OUT_W1TS_DATA_MASK +#define GPIO_OUT_W1TS_DATA_GET(x) WLAN_GPIO_OUT_W1TS_DATA_GET(x) +#define GPIO_OUT_W1TS_DATA_SET(x) WLAN_GPIO_OUT_W1TS_DATA_SET(x) +#define GPIO_OUT_W1TC_ADDRESS WLAN_GPIO_OUT_W1TC_ADDRESS +#define GPIO_OUT_W1TC_OFFSET WLAN_GPIO_OUT_W1TC_OFFSET +#define GPIO_OUT_W1TC_DATA_MSB WLAN_GPIO_OUT_W1TC_DATA_MSB +#define GPIO_OUT_W1TC_DATA_LSB WLAN_GPIO_OUT_W1TC_DATA_LSB +#define GPIO_OUT_W1TC_DATA_MASK WLAN_GPIO_OUT_W1TC_DATA_MASK +#define GPIO_OUT_W1TC_DATA_GET(x) WLAN_GPIO_OUT_W1TC_DATA_GET(x) +#define GPIO_OUT_W1TC_DATA_SET(x) WLAN_GPIO_OUT_W1TC_DATA_SET(x) +#define GPIO_ENABLE_ADDRESS WLAN_GPIO_ENABLE_ADDRESS +#define GPIO_ENABLE_OFFSET WLAN_GPIO_ENABLE_OFFSET +#define GPIO_ENABLE_DATA_MSB WLAN_GPIO_ENABLE_DATA_MSB +#define GPIO_ENABLE_DATA_LSB WLAN_GPIO_ENABLE_DATA_LSB +#define GPIO_ENABLE_DATA_MASK WLAN_GPIO_ENABLE_DATA_MASK +#define GPIO_ENABLE_DATA_GET(x) WLAN_GPIO_ENABLE_DATA_GET(x) +#define GPIO_ENABLE_DATA_SET(x) WLAN_GPIO_ENABLE_DATA_SET(x) +#define GPIO_ENABLE_W1TS_ADDRESS WLAN_GPIO_ENABLE_W1TS_ADDRESS +#define GPIO_ENABLE_W1TS_OFFSET WLAN_GPIO_ENABLE_W1TS_OFFSET +#define GPIO_ENABLE_W1TS_DATA_MSB WLAN_GPIO_ENABLE_W1TS_DATA_MSB +#define GPIO_ENABLE_W1TS_DATA_LSB WLAN_GPIO_ENABLE_W1TS_DATA_LSB +#define GPIO_ENABLE_W1TS_DATA_MASK WLAN_GPIO_ENABLE_W1TS_DATA_MASK +#define GPIO_ENABLE_W1TS_DATA_GET(x) WLAN_GPIO_ENABLE_W1TS_DATA_GET(x) +#define GPIO_ENABLE_W1TS_DATA_SET(x) WLAN_GPIO_ENABLE_W1TS_DATA_SET(x) +#define GPIO_ENABLE_W1TC_ADDRESS WLAN_GPIO_ENABLE_W1TC_ADDRESS +#define GPIO_ENABLE_W1TC_OFFSET WLAN_GPIO_ENABLE_W1TC_OFFSET +#define GPIO_ENABLE_W1TC_DATA_MSB WLAN_GPIO_ENABLE_W1TC_DATA_MSB +#define GPIO_ENABLE_W1TC_DATA_LSB WLAN_GPIO_ENABLE_W1TC_DATA_LSB +#define GPIO_ENABLE_W1TC_DATA_MASK WLAN_GPIO_ENABLE_W1TC_DATA_MASK +#define GPIO_ENABLE_W1TC_DATA_GET(x) WLAN_GPIO_ENABLE_W1TC_DATA_GET(x) +#define GPIO_ENABLE_W1TC_DATA_SET(x) WLAN_GPIO_ENABLE_W1TC_DATA_SET(x) +#define GPIO_IN_ADDRESS WLAN_GPIO_IN_ADDRESS +#define GPIO_IN_OFFSET WLAN_GPIO_IN_OFFSET +#define GPIO_IN_DATA_MSB WLAN_GPIO_IN_DATA_MSB +#define GPIO_IN_DATA_LSB WLAN_GPIO_IN_DATA_LSB +#define GPIO_IN_DATA_MASK WLAN_GPIO_IN_DATA_MASK +#define GPIO_IN_DATA_GET(x) WLAN_GPIO_IN_DATA_GET(x) +#define GPIO_IN_DATA_SET(x) WLAN_GPIO_IN_DATA_SET(x) +#define GPIO_STATUS_ADDRESS WLAN_GPIO_STATUS_ADDRESS +#define GPIO_STATUS_OFFSET WLAN_GPIO_STATUS_OFFSET +#define GPIO_STATUS_INTERRUPT_MSB WLAN_GPIO_STATUS_INTERRUPT_MSB +#define GPIO_STATUS_INTERRUPT_LSB WLAN_GPIO_STATUS_INTERRUPT_LSB +#define GPIO_STATUS_INTERRUPT_MASK WLAN_GPIO_STATUS_INTERRUPT_MASK +#define GPIO_STATUS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_INTERRUPT_GET(x) +#define GPIO_STATUS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_INTERRUPT_SET(x) +#define GPIO_STATUS_W1TS_ADDRESS WLAN_GPIO_STATUS_W1TS_ADDRESS +#define GPIO_STATUS_W1TS_OFFSET WLAN_GPIO_STATUS_W1TS_OFFSET +#define GPIO_STATUS_W1TS_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB +#define GPIO_STATUS_W1TS_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB +#define GPIO_STATUS_W1TS_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x) +#define GPIO_STATUS_W1TC_ADDRESS WLAN_GPIO_STATUS_W1TC_ADDRESS +#define GPIO_STATUS_W1TC_OFFSET WLAN_GPIO_STATUS_W1TC_OFFSET +#define GPIO_STATUS_W1TC_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB +#define GPIO_STATUS_W1TC_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB +#define GPIO_STATUS_W1TC_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x) +#define GPIO_PIN0_ADDRESS WLAN_GPIO_PIN0_ADDRESS +#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_OFFSET +#define GPIO_PIN0_CONFIG_MSB WLAN_GPIO_PIN0_CONFIG_MSB +#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB +#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK +#define GPIO_PIN0_CONFIG_GET(x) WLAN_GPIO_PIN0_CONFIG_GET(x) +#define GPIO_PIN0_CONFIG_SET(x) WLAN_GPIO_PIN0_CONFIG_SET(x) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB +#define GPIO_PIN0_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB +#define GPIO_PIN0_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN0_INT_TYPE_MSB WLAN_GPIO_PIN0_INT_TYPE_MSB +#define GPIO_PIN0_INT_TYPE_LSB WLAN_GPIO_PIN0_INT_TYPE_LSB +#define GPIO_PIN0_INT_TYPE_MASK WLAN_GPIO_PIN0_INT_TYPE_MASK +#define GPIO_PIN0_INT_TYPE_GET(x) WLAN_GPIO_PIN0_INT_TYPE_GET(x) +#define GPIO_PIN0_INT_TYPE_SET(x) WLAN_GPIO_PIN0_INT_TYPE_SET(x) +#define GPIO_PIN0_PAD_PULL_MSB WLAN_GPIO_PIN0_PAD_PULL_MSB +#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB +#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK +#define GPIO_PIN0_PAD_PULL_GET(x) WLAN_GPIO_PIN0_PAD_PULL_GET(x) +#define GPIO_PIN0_PAD_PULL_SET(x) WLAN_GPIO_PIN0_PAD_PULL_SET(x) +#define GPIO_PIN0_PAD_STRENGTH_MSB WLAN_GPIO_PIN0_PAD_STRENGTH_MSB +#define GPIO_PIN0_PAD_STRENGTH_LSB WLAN_GPIO_PIN0_PAD_STRENGTH_LSB +#define GPIO_PIN0_PAD_STRENGTH_MASK WLAN_GPIO_PIN0_PAD_STRENGTH_MASK +#define GPIO_PIN0_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x) +#define GPIO_PIN0_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x) +#define GPIO_PIN0_PAD_DRIVER_MSB WLAN_GPIO_PIN0_PAD_DRIVER_MSB +#define GPIO_PIN0_PAD_DRIVER_LSB WLAN_GPIO_PIN0_PAD_DRIVER_LSB +#define GPIO_PIN0_PAD_DRIVER_MASK WLAN_GPIO_PIN0_PAD_DRIVER_MASK +#define GPIO_PIN0_PAD_DRIVER_GET(x) WLAN_GPIO_PIN0_PAD_DRIVER_GET(x) +#define GPIO_PIN0_PAD_DRIVER_SET(x) WLAN_GPIO_PIN0_PAD_DRIVER_SET(x) +#define GPIO_PIN0_SOURCE_MSB WLAN_GPIO_PIN0_SOURCE_MSB +#define GPIO_PIN0_SOURCE_LSB WLAN_GPIO_PIN0_SOURCE_LSB +#define GPIO_PIN0_SOURCE_MASK WLAN_GPIO_PIN0_SOURCE_MASK +#define GPIO_PIN0_SOURCE_GET(x) WLAN_GPIO_PIN0_SOURCE_GET(x) +#define GPIO_PIN0_SOURCE_SET(x) WLAN_GPIO_PIN0_SOURCE_SET(x) +#define GPIO_PIN1_ADDRESS WLAN_GPIO_PIN1_ADDRESS +#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_OFFSET +#define GPIO_PIN1_CONFIG_MSB WLAN_GPIO_PIN1_CONFIG_MSB +#define GPIO_PIN1_CONFIG_LSB WLAN_GPIO_PIN1_CONFIG_LSB +#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK +#define GPIO_PIN1_CONFIG_GET(x) WLAN_GPIO_PIN1_CONFIG_GET(x) +#define GPIO_PIN1_CONFIG_SET(x) WLAN_GPIO_PIN1_CONFIG_SET(x) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB +#define GPIO_PIN1_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB +#define GPIO_PIN1_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN1_INT_TYPE_MSB WLAN_GPIO_PIN1_INT_TYPE_MSB +#define GPIO_PIN1_INT_TYPE_LSB WLAN_GPIO_PIN1_INT_TYPE_LSB +#define GPIO_PIN1_INT_TYPE_MASK WLAN_GPIO_PIN1_INT_TYPE_MASK +#define GPIO_PIN1_INT_TYPE_GET(x) WLAN_GPIO_PIN1_INT_TYPE_GET(x) +#define GPIO_PIN1_INT_TYPE_SET(x) WLAN_GPIO_PIN1_INT_TYPE_SET(x) +#define GPIO_PIN1_PAD_PULL_MSB WLAN_GPIO_PIN1_PAD_PULL_MSB +#define GPIO_PIN1_PAD_PULL_LSB WLAN_GPIO_PIN1_PAD_PULL_LSB +#define GPIO_PIN1_PAD_PULL_MASK WLAN_GPIO_PIN1_PAD_PULL_MASK +#define GPIO_PIN1_PAD_PULL_GET(x) WLAN_GPIO_PIN1_PAD_PULL_GET(x) +#define GPIO_PIN1_PAD_PULL_SET(x) WLAN_GPIO_PIN1_PAD_PULL_SET(x) +#define GPIO_PIN1_PAD_STRENGTH_MSB WLAN_GPIO_PIN1_PAD_STRENGTH_MSB +#define GPIO_PIN1_PAD_STRENGTH_LSB WLAN_GPIO_PIN1_PAD_STRENGTH_LSB +#define GPIO_PIN1_PAD_STRENGTH_MASK WLAN_GPIO_PIN1_PAD_STRENGTH_MASK +#define GPIO_PIN1_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x) +#define GPIO_PIN1_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x) +#define GPIO_PIN1_PAD_DRIVER_MSB WLAN_GPIO_PIN1_PAD_DRIVER_MSB +#define GPIO_PIN1_PAD_DRIVER_LSB WLAN_GPIO_PIN1_PAD_DRIVER_LSB +#define GPIO_PIN1_PAD_DRIVER_MASK WLAN_GPIO_PIN1_PAD_DRIVER_MASK +#define GPIO_PIN1_PAD_DRIVER_GET(x) WLAN_GPIO_PIN1_PAD_DRIVER_GET(x) +#define GPIO_PIN1_PAD_DRIVER_SET(x) WLAN_GPIO_PIN1_PAD_DRIVER_SET(x) +#define GPIO_PIN1_SOURCE_MSB WLAN_GPIO_PIN1_SOURCE_MSB +#define GPIO_PIN1_SOURCE_LSB WLAN_GPIO_PIN1_SOURCE_LSB +#define GPIO_PIN1_SOURCE_MASK WLAN_GPIO_PIN1_SOURCE_MASK +#define GPIO_PIN1_SOURCE_GET(x) WLAN_GPIO_PIN1_SOURCE_GET(x) +#define GPIO_PIN1_SOURCE_SET(x) WLAN_GPIO_PIN1_SOURCE_SET(x) +#define GPIO_PIN2_ADDRESS WLAN_GPIO_PIN2_ADDRESS +#define GPIO_PIN2_OFFSET WLAN_GPIO_PIN2_OFFSET +#define GPIO_PIN2_CONFIG_MSB WLAN_GPIO_PIN2_CONFIG_MSB +#define GPIO_PIN2_CONFIG_LSB WLAN_GPIO_PIN2_CONFIG_LSB +#define GPIO_PIN2_CONFIG_MASK WLAN_GPIO_PIN2_CONFIG_MASK +#define GPIO_PIN2_CONFIG_GET(x) WLAN_GPIO_PIN2_CONFIG_GET(x) +#define GPIO_PIN2_CONFIG_SET(x) WLAN_GPIO_PIN2_CONFIG_SET(x) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB +#define GPIO_PIN2_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB +#define GPIO_PIN2_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN2_INT_TYPE_MSB WLAN_GPIO_PIN2_INT_TYPE_MSB +#define GPIO_PIN2_INT_TYPE_LSB WLAN_GPIO_PIN2_INT_TYPE_LSB +#define GPIO_PIN2_INT_TYPE_MASK WLAN_GPIO_PIN2_INT_TYPE_MASK +#define GPIO_PIN2_INT_TYPE_GET(x) WLAN_GPIO_PIN2_INT_TYPE_GET(x) +#define GPIO_PIN2_INT_TYPE_SET(x) WLAN_GPIO_PIN2_INT_TYPE_SET(x) +#define GPIO_PIN2_PAD_PULL_MSB WLAN_GPIO_PIN2_PAD_PULL_MSB +#define GPIO_PIN2_PAD_PULL_LSB WLAN_GPIO_PIN2_PAD_PULL_LSB +#define GPIO_PIN2_PAD_PULL_MASK WLAN_GPIO_PIN2_PAD_PULL_MASK +#define GPIO_PIN2_PAD_PULL_GET(x) WLAN_GPIO_PIN2_PAD_PULL_GET(x) +#define GPIO_PIN2_PAD_PULL_SET(x) WLAN_GPIO_PIN2_PAD_PULL_SET(x) +#define GPIO_PIN2_PAD_STRENGTH_MSB WLAN_GPIO_PIN2_PAD_STRENGTH_MSB +#define GPIO_PIN2_PAD_STRENGTH_LSB WLAN_GPIO_PIN2_PAD_STRENGTH_LSB +#define GPIO_PIN2_PAD_STRENGTH_MASK WLAN_GPIO_PIN2_PAD_STRENGTH_MASK +#define GPIO_PIN2_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x) +#define GPIO_PIN2_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x) +#define GPIO_PIN2_PAD_DRIVER_MSB WLAN_GPIO_PIN2_PAD_DRIVER_MSB +#define GPIO_PIN2_PAD_DRIVER_LSB WLAN_GPIO_PIN2_PAD_DRIVER_LSB +#define GPIO_PIN2_PAD_DRIVER_MASK WLAN_GPIO_PIN2_PAD_DRIVER_MASK +#define GPIO_PIN2_PAD_DRIVER_GET(x) WLAN_GPIO_PIN2_PAD_DRIVER_GET(x) +#define GPIO_PIN2_PAD_DRIVER_SET(x) WLAN_GPIO_PIN2_PAD_DRIVER_SET(x) +#define GPIO_PIN2_SOURCE_MSB WLAN_GPIO_PIN2_SOURCE_MSB +#define GPIO_PIN2_SOURCE_LSB WLAN_GPIO_PIN2_SOURCE_LSB +#define GPIO_PIN2_SOURCE_MASK WLAN_GPIO_PIN2_SOURCE_MASK +#define GPIO_PIN2_SOURCE_GET(x) WLAN_GPIO_PIN2_SOURCE_GET(x) +#define GPIO_PIN2_SOURCE_SET(x) WLAN_GPIO_PIN2_SOURCE_SET(x) +#define GPIO_PIN3_ADDRESS WLAN_GPIO_PIN3_ADDRESS +#define GPIO_PIN3_OFFSET WLAN_GPIO_PIN3_OFFSET +#define GPIO_PIN3_CONFIG_MSB WLAN_GPIO_PIN3_CONFIG_MSB +#define GPIO_PIN3_CONFIG_LSB WLAN_GPIO_PIN3_CONFIG_LSB +#define GPIO_PIN3_CONFIG_MASK WLAN_GPIO_PIN3_CONFIG_MASK +#define GPIO_PIN3_CONFIG_GET(x) WLAN_GPIO_PIN3_CONFIG_GET(x) +#define GPIO_PIN3_CONFIG_SET(x) WLAN_GPIO_PIN3_CONFIG_SET(x) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB +#define GPIO_PIN3_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB +#define GPIO_PIN3_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN3_INT_TYPE_MSB WLAN_GPIO_PIN3_INT_TYPE_MSB +#define GPIO_PIN3_INT_TYPE_LSB WLAN_GPIO_PIN3_INT_TYPE_LSB +#define GPIO_PIN3_INT_TYPE_MASK WLAN_GPIO_PIN3_INT_TYPE_MASK +#define GPIO_PIN3_INT_TYPE_GET(x) WLAN_GPIO_PIN3_INT_TYPE_GET(x) +#define GPIO_PIN3_INT_TYPE_SET(x) WLAN_GPIO_PIN3_INT_TYPE_SET(x) +#define GPIO_PIN3_PAD_PULL_MSB WLAN_GPIO_PIN3_PAD_PULL_MSB +#define GPIO_PIN3_PAD_PULL_LSB WLAN_GPIO_PIN3_PAD_PULL_LSB +#define GPIO_PIN3_PAD_PULL_MASK WLAN_GPIO_PIN3_PAD_PULL_MASK +#define GPIO_PIN3_PAD_PULL_GET(x) WLAN_GPIO_PIN3_PAD_PULL_GET(x) +#define GPIO_PIN3_PAD_PULL_SET(x) WLAN_GPIO_PIN3_PAD_PULL_SET(x) +#define GPIO_PIN3_PAD_STRENGTH_MSB WLAN_GPIO_PIN3_PAD_STRENGTH_MSB +#define GPIO_PIN3_PAD_STRENGTH_LSB WLAN_GPIO_PIN3_PAD_STRENGTH_LSB +#define GPIO_PIN3_PAD_STRENGTH_MASK WLAN_GPIO_PIN3_PAD_STRENGTH_MASK +#define GPIO_PIN3_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x) +#define GPIO_PIN3_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x) +#define GPIO_PIN3_PAD_DRIVER_MSB WLAN_GPIO_PIN3_PAD_DRIVER_MSB +#define GPIO_PIN3_PAD_DRIVER_LSB WLAN_GPIO_PIN3_PAD_DRIVER_LSB +#define GPIO_PIN3_PAD_DRIVER_MASK WLAN_GPIO_PIN3_PAD_DRIVER_MASK +#define GPIO_PIN3_PAD_DRIVER_GET(x) WLAN_GPIO_PIN3_PAD_DRIVER_GET(x) +#define GPIO_PIN3_PAD_DRIVER_SET(x) WLAN_GPIO_PIN3_PAD_DRIVER_SET(x) +#define GPIO_PIN3_SOURCE_MSB WLAN_GPIO_PIN3_SOURCE_MSB +#define GPIO_PIN3_SOURCE_LSB WLAN_GPIO_PIN3_SOURCE_LSB +#define GPIO_PIN3_SOURCE_MASK WLAN_GPIO_PIN3_SOURCE_MASK +#define GPIO_PIN3_SOURCE_GET(x) WLAN_GPIO_PIN3_SOURCE_GET(x) +#define GPIO_PIN3_SOURCE_SET(x) WLAN_GPIO_PIN3_SOURCE_SET(x) +#define GPIO_PIN4_ADDRESS WLAN_GPIO_PIN4_ADDRESS +#define GPIO_PIN4_OFFSET WLAN_GPIO_PIN4_OFFSET +#define GPIO_PIN4_CONFIG_MSB WLAN_GPIO_PIN4_CONFIG_MSB +#define GPIO_PIN4_CONFIG_LSB WLAN_GPIO_PIN4_CONFIG_LSB +#define GPIO_PIN4_CONFIG_MASK WLAN_GPIO_PIN4_CONFIG_MASK +#define GPIO_PIN4_CONFIG_GET(x) WLAN_GPIO_PIN4_CONFIG_GET(x) +#define GPIO_PIN4_CONFIG_SET(x) WLAN_GPIO_PIN4_CONFIG_SET(x) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB +#define GPIO_PIN4_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB +#define GPIO_PIN4_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN4_INT_TYPE_MSB WLAN_GPIO_PIN4_INT_TYPE_MSB +#define GPIO_PIN4_INT_TYPE_LSB WLAN_GPIO_PIN4_INT_TYPE_LSB +#define GPIO_PIN4_INT_TYPE_MASK WLAN_GPIO_PIN4_INT_TYPE_MASK +#define GPIO_PIN4_INT_TYPE_GET(x) WLAN_GPIO_PIN4_INT_TYPE_GET(x) +#define GPIO_PIN4_INT_TYPE_SET(x) WLAN_GPIO_PIN4_INT_TYPE_SET(x) +#define GPIO_PIN4_PAD_PULL_MSB WLAN_GPIO_PIN4_PAD_PULL_MSB +#define GPIO_PIN4_PAD_PULL_LSB WLAN_GPIO_PIN4_PAD_PULL_LSB +#define GPIO_PIN4_PAD_PULL_MASK WLAN_GPIO_PIN4_PAD_PULL_MASK +#define GPIO_PIN4_PAD_PULL_GET(x) WLAN_GPIO_PIN4_PAD_PULL_GET(x) +#define GPIO_PIN4_PAD_PULL_SET(x) WLAN_GPIO_PIN4_PAD_PULL_SET(x) +#define GPIO_PIN4_PAD_STRENGTH_MSB WLAN_GPIO_PIN4_PAD_STRENGTH_MSB +#define GPIO_PIN4_PAD_STRENGTH_LSB WLAN_GPIO_PIN4_PAD_STRENGTH_LSB +#define GPIO_PIN4_PAD_STRENGTH_MASK WLAN_GPIO_PIN4_PAD_STRENGTH_MASK +#define GPIO_PIN4_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x) +#define GPIO_PIN4_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x) +#define GPIO_PIN4_PAD_DRIVER_MSB WLAN_GPIO_PIN4_PAD_DRIVER_MSB +#define GPIO_PIN4_PAD_DRIVER_LSB WLAN_GPIO_PIN4_PAD_DRIVER_LSB +#define GPIO_PIN4_PAD_DRIVER_MASK WLAN_GPIO_PIN4_PAD_DRIVER_MASK +#define GPIO_PIN4_PAD_DRIVER_GET(x) WLAN_GPIO_PIN4_PAD_DRIVER_GET(x) +#define GPIO_PIN4_PAD_DRIVER_SET(x) WLAN_GPIO_PIN4_PAD_DRIVER_SET(x) +#define GPIO_PIN4_SOURCE_MSB WLAN_GPIO_PIN4_SOURCE_MSB +#define GPIO_PIN4_SOURCE_LSB WLAN_GPIO_PIN4_SOURCE_LSB +#define GPIO_PIN4_SOURCE_MASK WLAN_GPIO_PIN4_SOURCE_MASK +#define GPIO_PIN4_SOURCE_GET(x) WLAN_GPIO_PIN4_SOURCE_GET(x) +#define GPIO_PIN4_SOURCE_SET(x) WLAN_GPIO_PIN4_SOURCE_SET(x) +#define GPIO_PIN5_ADDRESS WLAN_GPIO_PIN5_ADDRESS +#define GPIO_PIN5_OFFSET WLAN_GPIO_PIN5_OFFSET +#define GPIO_PIN5_CONFIG_MSB WLAN_GPIO_PIN5_CONFIG_MSB +#define GPIO_PIN5_CONFIG_LSB WLAN_GPIO_PIN5_CONFIG_LSB +#define GPIO_PIN5_CONFIG_MASK WLAN_GPIO_PIN5_CONFIG_MASK +#define GPIO_PIN5_CONFIG_GET(x) WLAN_GPIO_PIN5_CONFIG_GET(x) +#define GPIO_PIN5_CONFIG_SET(x) WLAN_GPIO_PIN5_CONFIG_SET(x) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB +#define GPIO_PIN5_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB +#define GPIO_PIN5_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN5_INT_TYPE_MSB WLAN_GPIO_PIN5_INT_TYPE_MSB +#define GPIO_PIN5_INT_TYPE_LSB WLAN_GPIO_PIN5_INT_TYPE_LSB +#define GPIO_PIN5_INT_TYPE_MASK WLAN_GPIO_PIN5_INT_TYPE_MASK +#define GPIO_PIN5_INT_TYPE_GET(x) WLAN_GPIO_PIN5_INT_TYPE_GET(x) +#define GPIO_PIN5_INT_TYPE_SET(x) WLAN_GPIO_PIN5_INT_TYPE_SET(x) +#define GPIO_PIN5_PAD_PULL_MSB WLAN_GPIO_PIN5_PAD_PULL_MSB +#define GPIO_PIN5_PAD_PULL_LSB WLAN_GPIO_PIN5_PAD_PULL_LSB +#define GPIO_PIN5_PAD_PULL_MASK WLAN_GPIO_PIN5_PAD_PULL_MASK +#define GPIO_PIN5_PAD_PULL_GET(x) WLAN_GPIO_PIN5_PAD_PULL_GET(x) +#define GPIO_PIN5_PAD_PULL_SET(x) WLAN_GPIO_PIN5_PAD_PULL_SET(x) +#define GPIO_PIN5_PAD_STRENGTH_MSB WLAN_GPIO_PIN5_PAD_STRENGTH_MSB +#define GPIO_PIN5_PAD_STRENGTH_LSB WLAN_GPIO_PIN5_PAD_STRENGTH_LSB +#define GPIO_PIN5_PAD_STRENGTH_MASK WLAN_GPIO_PIN5_PAD_STRENGTH_MASK +#define GPIO_PIN5_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x) +#define GPIO_PIN5_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x) +#define GPIO_PIN5_PAD_DRIVER_MSB WLAN_GPIO_PIN5_PAD_DRIVER_MSB +#define GPIO_PIN5_PAD_DRIVER_LSB WLAN_GPIO_PIN5_PAD_DRIVER_LSB +#define GPIO_PIN5_PAD_DRIVER_MASK WLAN_GPIO_PIN5_PAD_DRIVER_MASK +#define GPIO_PIN5_PAD_DRIVER_GET(x) WLAN_GPIO_PIN5_PAD_DRIVER_GET(x) +#define GPIO_PIN5_PAD_DRIVER_SET(x) WLAN_GPIO_PIN5_PAD_DRIVER_SET(x) +#define GPIO_PIN5_SOURCE_MSB WLAN_GPIO_PIN5_SOURCE_MSB +#define GPIO_PIN5_SOURCE_LSB WLAN_GPIO_PIN5_SOURCE_LSB +#define GPIO_PIN5_SOURCE_MASK WLAN_GPIO_PIN5_SOURCE_MASK +#define GPIO_PIN5_SOURCE_GET(x) WLAN_GPIO_PIN5_SOURCE_GET(x) +#define GPIO_PIN5_SOURCE_SET(x) WLAN_GPIO_PIN5_SOURCE_SET(x) +#define GPIO_PIN6_ADDRESS WLAN_GPIO_PIN6_ADDRESS +#define GPIO_PIN6_OFFSET WLAN_GPIO_PIN6_OFFSET +#define GPIO_PIN6_CONFIG_MSB WLAN_GPIO_PIN6_CONFIG_MSB +#define GPIO_PIN6_CONFIG_LSB WLAN_GPIO_PIN6_CONFIG_LSB +#define GPIO_PIN6_CONFIG_MASK WLAN_GPIO_PIN6_CONFIG_MASK +#define GPIO_PIN6_CONFIG_GET(x) WLAN_GPIO_PIN6_CONFIG_GET(x) +#define GPIO_PIN6_CONFIG_SET(x) WLAN_GPIO_PIN6_CONFIG_SET(x) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB +#define GPIO_PIN6_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB +#define GPIO_PIN6_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN6_INT_TYPE_MSB WLAN_GPIO_PIN6_INT_TYPE_MSB +#define GPIO_PIN6_INT_TYPE_LSB WLAN_GPIO_PIN6_INT_TYPE_LSB +#define GPIO_PIN6_INT_TYPE_MASK WLAN_GPIO_PIN6_INT_TYPE_MASK +#define GPIO_PIN6_INT_TYPE_GET(x) WLAN_GPIO_PIN6_INT_TYPE_GET(x) +#define GPIO_PIN6_INT_TYPE_SET(x) WLAN_GPIO_PIN6_INT_TYPE_SET(x) +#define GPIO_PIN6_PAD_PULL_MSB WLAN_GPIO_PIN6_PAD_PULL_MSB +#define GPIO_PIN6_PAD_PULL_LSB WLAN_GPIO_PIN6_PAD_PULL_LSB +#define GPIO_PIN6_PAD_PULL_MASK WLAN_GPIO_PIN6_PAD_PULL_MASK +#define GPIO_PIN6_PAD_PULL_GET(x) WLAN_GPIO_PIN6_PAD_PULL_GET(x) +#define GPIO_PIN6_PAD_PULL_SET(x) WLAN_GPIO_PIN6_PAD_PULL_SET(x) +#define GPIO_PIN6_PAD_STRENGTH_MSB WLAN_GPIO_PIN6_PAD_STRENGTH_MSB +#define GPIO_PIN6_PAD_STRENGTH_LSB WLAN_GPIO_PIN6_PAD_STRENGTH_LSB +#define GPIO_PIN6_PAD_STRENGTH_MASK WLAN_GPIO_PIN6_PAD_STRENGTH_MASK +#define GPIO_PIN6_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x) +#define GPIO_PIN6_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x) +#define GPIO_PIN6_PAD_DRIVER_MSB WLAN_GPIO_PIN6_PAD_DRIVER_MSB +#define GPIO_PIN6_PAD_DRIVER_LSB WLAN_GPIO_PIN6_PAD_DRIVER_LSB +#define GPIO_PIN6_PAD_DRIVER_MASK WLAN_GPIO_PIN6_PAD_DRIVER_MASK +#define GPIO_PIN6_PAD_DRIVER_GET(x) WLAN_GPIO_PIN6_PAD_DRIVER_GET(x) +#define GPIO_PIN6_PAD_DRIVER_SET(x) WLAN_GPIO_PIN6_PAD_DRIVER_SET(x) +#define GPIO_PIN6_SOURCE_MSB WLAN_GPIO_PIN6_SOURCE_MSB +#define GPIO_PIN6_SOURCE_LSB WLAN_GPIO_PIN6_SOURCE_LSB +#define GPIO_PIN6_SOURCE_MASK WLAN_GPIO_PIN6_SOURCE_MASK +#define GPIO_PIN6_SOURCE_GET(x) WLAN_GPIO_PIN6_SOURCE_GET(x) +#define GPIO_PIN6_SOURCE_SET(x) WLAN_GPIO_PIN6_SOURCE_SET(x) +#define GPIO_PIN7_ADDRESS WLAN_GPIO_PIN7_ADDRESS +#define GPIO_PIN7_OFFSET WLAN_GPIO_PIN7_OFFSET +#define GPIO_PIN7_CONFIG_MSB WLAN_GPIO_PIN7_CONFIG_MSB +#define GPIO_PIN7_CONFIG_LSB WLAN_GPIO_PIN7_CONFIG_LSB +#define GPIO_PIN7_CONFIG_MASK WLAN_GPIO_PIN7_CONFIG_MASK +#define GPIO_PIN7_CONFIG_GET(x) WLAN_GPIO_PIN7_CONFIG_GET(x) +#define GPIO_PIN7_CONFIG_SET(x) WLAN_GPIO_PIN7_CONFIG_SET(x) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB +#define GPIO_PIN7_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB +#define GPIO_PIN7_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN7_INT_TYPE_MSB WLAN_GPIO_PIN7_INT_TYPE_MSB +#define GPIO_PIN7_INT_TYPE_LSB WLAN_GPIO_PIN7_INT_TYPE_LSB +#define GPIO_PIN7_INT_TYPE_MASK WLAN_GPIO_PIN7_INT_TYPE_MASK +#define GPIO_PIN7_INT_TYPE_GET(x) WLAN_GPIO_PIN7_INT_TYPE_GET(x) +#define GPIO_PIN7_INT_TYPE_SET(x) WLAN_GPIO_PIN7_INT_TYPE_SET(x) +#define GPIO_PIN7_PAD_PULL_MSB WLAN_GPIO_PIN7_PAD_PULL_MSB +#define GPIO_PIN7_PAD_PULL_LSB WLAN_GPIO_PIN7_PAD_PULL_LSB +#define GPIO_PIN7_PAD_PULL_MASK WLAN_GPIO_PIN7_PAD_PULL_MASK +#define GPIO_PIN7_PAD_PULL_GET(x) WLAN_GPIO_PIN7_PAD_PULL_GET(x) +#define GPIO_PIN7_PAD_PULL_SET(x) WLAN_GPIO_PIN7_PAD_PULL_SET(x) +#define GPIO_PIN7_PAD_STRENGTH_MSB WLAN_GPIO_PIN7_PAD_STRENGTH_MSB +#define GPIO_PIN7_PAD_STRENGTH_LSB WLAN_GPIO_PIN7_PAD_STRENGTH_LSB +#define GPIO_PIN7_PAD_STRENGTH_MASK WLAN_GPIO_PIN7_PAD_STRENGTH_MASK +#define GPIO_PIN7_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x) +#define GPIO_PIN7_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x) +#define GPIO_PIN7_PAD_DRIVER_MSB WLAN_GPIO_PIN7_PAD_DRIVER_MSB +#define GPIO_PIN7_PAD_DRIVER_LSB WLAN_GPIO_PIN7_PAD_DRIVER_LSB +#define GPIO_PIN7_PAD_DRIVER_MASK WLAN_GPIO_PIN7_PAD_DRIVER_MASK +#define GPIO_PIN7_PAD_DRIVER_GET(x) WLAN_GPIO_PIN7_PAD_DRIVER_GET(x) +#define GPIO_PIN7_PAD_DRIVER_SET(x) WLAN_GPIO_PIN7_PAD_DRIVER_SET(x) +#define GPIO_PIN7_SOURCE_MSB WLAN_GPIO_PIN7_SOURCE_MSB +#define GPIO_PIN7_SOURCE_LSB WLAN_GPIO_PIN7_SOURCE_LSB +#define GPIO_PIN7_SOURCE_MASK WLAN_GPIO_PIN7_SOURCE_MASK +#define GPIO_PIN7_SOURCE_GET(x) WLAN_GPIO_PIN7_SOURCE_GET(x) +#define GPIO_PIN7_SOURCE_SET(x) WLAN_GPIO_PIN7_SOURCE_SET(x) +#define GPIO_PIN8_ADDRESS WLAN_GPIO_PIN8_ADDRESS +#define GPIO_PIN8_OFFSET WLAN_GPIO_PIN8_OFFSET +#define GPIO_PIN8_CONFIG_MSB WLAN_GPIO_PIN8_CONFIG_MSB +#define GPIO_PIN8_CONFIG_LSB WLAN_GPIO_PIN8_CONFIG_LSB +#define GPIO_PIN8_CONFIG_MASK WLAN_GPIO_PIN8_CONFIG_MASK +#define GPIO_PIN8_CONFIG_GET(x) WLAN_GPIO_PIN8_CONFIG_GET(x) +#define GPIO_PIN8_CONFIG_SET(x) WLAN_GPIO_PIN8_CONFIG_SET(x) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB +#define GPIO_PIN8_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB +#define GPIO_PIN8_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN8_INT_TYPE_MSB WLAN_GPIO_PIN8_INT_TYPE_MSB +#define GPIO_PIN8_INT_TYPE_LSB WLAN_GPIO_PIN8_INT_TYPE_LSB +#define GPIO_PIN8_INT_TYPE_MASK WLAN_GPIO_PIN8_INT_TYPE_MASK +#define GPIO_PIN8_INT_TYPE_GET(x) WLAN_GPIO_PIN8_INT_TYPE_GET(x) +#define GPIO_PIN8_INT_TYPE_SET(x) WLAN_GPIO_PIN8_INT_TYPE_SET(x) +#define GPIO_PIN8_PAD_PULL_MSB WLAN_GPIO_PIN8_PAD_PULL_MSB +#define GPIO_PIN8_PAD_PULL_LSB WLAN_GPIO_PIN8_PAD_PULL_LSB +#define GPIO_PIN8_PAD_PULL_MASK WLAN_GPIO_PIN8_PAD_PULL_MASK +#define GPIO_PIN8_PAD_PULL_GET(x) WLAN_GPIO_PIN8_PAD_PULL_GET(x) +#define GPIO_PIN8_PAD_PULL_SET(x) WLAN_GPIO_PIN8_PAD_PULL_SET(x) +#define GPIO_PIN8_PAD_STRENGTH_MSB WLAN_GPIO_PIN8_PAD_STRENGTH_MSB +#define GPIO_PIN8_PAD_STRENGTH_LSB WLAN_GPIO_PIN8_PAD_STRENGTH_LSB +#define GPIO_PIN8_PAD_STRENGTH_MASK WLAN_GPIO_PIN8_PAD_STRENGTH_MASK +#define GPIO_PIN8_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x) +#define GPIO_PIN8_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x) +#define GPIO_PIN8_PAD_DRIVER_MSB WLAN_GPIO_PIN8_PAD_DRIVER_MSB +#define GPIO_PIN8_PAD_DRIVER_LSB WLAN_GPIO_PIN8_PAD_DRIVER_LSB +#define GPIO_PIN8_PAD_DRIVER_MASK WLAN_GPIO_PIN8_PAD_DRIVER_MASK +#define GPIO_PIN8_PAD_DRIVER_GET(x) WLAN_GPIO_PIN8_PAD_DRIVER_GET(x) +#define GPIO_PIN8_PAD_DRIVER_SET(x) WLAN_GPIO_PIN8_PAD_DRIVER_SET(x) +#define GPIO_PIN8_SOURCE_MSB WLAN_GPIO_PIN8_SOURCE_MSB +#define GPIO_PIN8_SOURCE_LSB WLAN_GPIO_PIN8_SOURCE_LSB +#define GPIO_PIN8_SOURCE_MASK WLAN_GPIO_PIN8_SOURCE_MASK +#define GPIO_PIN8_SOURCE_GET(x) WLAN_GPIO_PIN8_SOURCE_GET(x) +#define GPIO_PIN8_SOURCE_SET(x) WLAN_GPIO_PIN8_SOURCE_SET(x) +#define GPIO_PIN9_ADDRESS WLAN_GPIO_PIN9_ADDRESS +#define GPIO_PIN9_OFFSET WLAN_GPIO_PIN9_OFFSET +#define GPIO_PIN9_CONFIG_MSB WLAN_GPIO_PIN9_CONFIG_MSB +#define GPIO_PIN9_CONFIG_LSB WLAN_GPIO_PIN9_CONFIG_LSB +#define GPIO_PIN9_CONFIG_MASK WLAN_GPIO_PIN9_CONFIG_MASK +#define GPIO_PIN9_CONFIG_GET(x) WLAN_GPIO_PIN9_CONFIG_GET(x) +#define GPIO_PIN9_CONFIG_SET(x) WLAN_GPIO_PIN9_CONFIG_SET(x) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB +#define GPIO_PIN9_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB +#define GPIO_PIN9_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN9_INT_TYPE_MSB WLAN_GPIO_PIN9_INT_TYPE_MSB +#define GPIO_PIN9_INT_TYPE_LSB WLAN_GPIO_PIN9_INT_TYPE_LSB +#define GPIO_PIN9_INT_TYPE_MASK WLAN_GPIO_PIN9_INT_TYPE_MASK +#define GPIO_PIN9_INT_TYPE_GET(x) WLAN_GPIO_PIN9_INT_TYPE_GET(x) +#define GPIO_PIN9_INT_TYPE_SET(x) WLAN_GPIO_PIN9_INT_TYPE_SET(x) +#define GPIO_PIN9_PAD_PULL_MSB WLAN_GPIO_PIN9_PAD_PULL_MSB +#define GPIO_PIN9_PAD_PULL_LSB WLAN_GPIO_PIN9_PAD_PULL_LSB +#define GPIO_PIN9_PAD_PULL_MASK WLAN_GPIO_PIN9_PAD_PULL_MASK +#define GPIO_PIN9_PAD_PULL_GET(x) WLAN_GPIO_PIN9_PAD_PULL_GET(x) +#define GPIO_PIN9_PAD_PULL_SET(x) WLAN_GPIO_PIN9_PAD_PULL_SET(x) +#define GPIO_PIN9_PAD_STRENGTH_MSB WLAN_GPIO_PIN9_PAD_STRENGTH_MSB +#define GPIO_PIN9_PAD_STRENGTH_LSB WLAN_GPIO_PIN9_PAD_STRENGTH_LSB +#define GPIO_PIN9_PAD_STRENGTH_MASK WLAN_GPIO_PIN9_PAD_STRENGTH_MASK +#define GPIO_PIN9_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x) +#define GPIO_PIN9_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x) +#define GPIO_PIN9_PAD_DRIVER_MSB WLAN_GPIO_PIN9_PAD_DRIVER_MSB +#define GPIO_PIN9_PAD_DRIVER_LSB WLAN_GPIO_PIN9_PAD_DRIVER_LSB +#define GPIO_PIN9_PAD_DRIVER_MASK WLAN_GPIO_PIN9_PAD_DRIVER_MASK +#define GPIO_PIN9_PAD_DRIVER_GET(x) WLAN_GPIO_PIN9_PAD_DRIVER_GET(x) +#define GPIO_PIN9_PAD_DRIVER_SET(x) WLAN_GPIO_PIN9_PAD_DRIVER_SET(x) +#define GPIO_PIN9_SOURCE_MSB WLAN_GPIO_PIN9_SOURCE_MSB +#define GPIO_PIN9_SOURCE_LSB WLAN_GPIO_PIN9_SOURCE_LSB +#define GPIO_PIN9_SOURCE_MASK WLAN_GPIO_PIN9_SOURCE_MASK +#define GPIO_PIN9_SOURCE_GET(x) WLAN_GPIO_PIN9_SOURCE_GET(x) +#define GPIO_PIN9_SOURCE_SET(x) WLAN_GPIO_PIN9_SOURCE_SET(x) +#define GPIO_PIN10_ADDRESS WLAN_GPIO_PIN10_ADDRESS +#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_OFFSET +#define GPIO_PIN10_CONFIG_MSB WLAN_GPIO_PIN10_CONFIG_MSB +#define GPIO_PIN10_CONFIG_LSB WLAN_GPIO_PIN10_CONFIG_LSB +#define GPIO_PIN10_CONFIG_MASK WLAN_GPIO_PIN10_CONFIG_MASK +#define GPIO_PIN10_CONFIG_GET(x) WLAN_GPIO_PIN10_CONFIG_GET(x) +#define GPIO_PIN10_CONFIG_SET(x) WLAN_GPIO_PIN10_CONFIG_SET(x) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB +#define GPIO_PIN10_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB +#define GPIO_PIN10_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN10_INT_TYPE_MSB WLAN_GPIO_PIN10_INT_TYPE_MSB +#define GPIO_PIN10_INT_TYPE_LSB WLAN_GPIO_PIN10_INT_TYPE_LSB +#define GPIO_PIN10_INT_TYPE_MASK WLAN_GPIO_PIN10_INT_TYPE_MASK +#define GPIO_PIN10_INT_TYPE_GET(x) WLAN_GPIO_PIN10_INT_TYPE_GET(x) +#define GPIO_PIN10_INT_TYPE_SET(x) WLAN_GPIO_PIN10_INT_TYPE_SET(x) +#define GPIO_PIN10_PAD_PULL_MSB WLAN_GPIO_PIN10_PAD_PULL_MSB +#define GPIO_PIN10_PAD_PULL_LSB WLAN_GPIO_PIN10_PAD_PULL_LSB +#define GPIO_PIN10_PAD_PULL_MASK WLAN_GPIO_PIN10_PAD_PULL_MASK +#define GPIO_PIN10_PAD_PULL_GET(x) WLAN_GPIO_PIN10_PAD_PULL_GET(x) +#define GPIO_PIN10_PAD_PULL_SET(x) WLAN_GPIO_PIN10_PAD_PULL_SET(x) +#define GPIO_PIN10_PAD_STRENGTH_MSB WLAN_GPIO_PIN10_PAD_STRENGTH_MSB +#define GPIO_PIN10_PAD_STRENGTH_LSB WLAN_GPIO_PIN10_PAD_STRENGTH_LSB +#define GPIO_PIN10_PAD_STRENGTH_MASK WLAN_GPIO_PIN10_PAD_STRENGTH_MASK +#define GPIO_PIN10_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x) +#define GPIO_PIN10_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x) +#define GPIO_PIN10_PAD_DRIVER_MSB WLAN_GPIO_PIN10_PAD_DRIVER_MSB +#define GPIO_PIN10_PAD_DRIVER_LSB WLAN_GPIO_PIN10_PAD_DRIVER_LSB +#define GPIO_PIN10_PAD_DRIVER_MASK WLAN_GPIO_PIN10_PAD_DRIVER_MASK +#define GPIO_PIN10_PAD_DRIVER_GET(x) WLAN_GPIO_PIN10_PAD_DRIVER_GET(x) +#define GPIO_PIN10_PAD_DRIVER_SET(x) WLAN_GPIO_PIN10_PAD_DRIVER_SET(x) +#define GPIO_PIN10_SOURCE_MSB WLAN_GPIO_PIN10_SOURCE_MSB +#define GPIO_PIN10_SOURCE_LSB WLAN_GPIO_PIN10_SOURCE_LSB +#define GPIO_PIN10_SOURCE_MASK WLAN_GPIO_PIN10_SOURCE_MASK +#define GPIO_PIN10_SOURCE_GET(x) WLAN_GPIO_PIN10_SOURCE_GET(x) +#define GPIO_PIN10_SOURCE_SET(x) WLAN_GPIO_PIN10_SOURCE_SET(x) +#define GPIO_PIN11_ADDRESS WLAN_GPIO_PIN11_ADDRESS +#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_OFFSET +#define GPIO_PIN11_CONFIG_MSB WLAN_GPIO_PIN11_CONFIG_MSB +#define GPIO_PIN11_CONFIG_LSB WLAN_GPIO_PIN11_CONFIG_LSB +#define GPIO_PIN11_CONFIG_MASK WLAN_GPIO_PIN11_CONFIG_MASK +#define GPIO_PIN11_CONFIG_GET(x) WLAN_GPIO_PIN11_CONFIG_GET(x) +#define GPIO_PIN11_CONFIG_SET(x) WLAN_GPIO_PIN11_CONFIG_SET(x) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB +#define GPIO_PIN11_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB +#define GPIO_PIN11_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN11_INT_TYPE_MSB WLAN_GPIO_PIN11_INT_TYPE_MSB +#define GPIO_PIN11_INT_TYPE_LSB WLAN_GPIO_PIN11_INT_TYPE_LSB +#define GPIO_PIN11_INT_TYPE_MASK WLAN_GPIO_PIN11_INT_TYPE_MASK +#define GPIO_PIN11_INT_TYPE_GET(x) WLAN_GPIO_PIN11_INT_TYPE_GET(x) +#define GPIO_PIN11_INT_TYPE_SET(x) WLAN_GPIO_PIN11_INT_TYPE_SET(x) +#define GPIO_PIN11_PAD_PULL_MSB WLAN_GPIO_PIN11_PAD_PULL_MSB +#define GPIO_PIN11_PAD_PULL_LSB WLAN_GPIO_PIN11_PAD_PULL_LSB +#define GPIO_PIN11_PAD_PULL_MASK WLAN_GPIO_PIN11_PAD_PULL_MASK +#define GPIO_PIN11_PAD_PULL_GET(x) WLAN_GPIO_PIN11_PAD_PULL_GET(x) +#define GPIO_PIN11_PAD_PULL_SET(x) WLAN_GPIO_PIN11_PAD_PULL_SET(x) +#define GPIO_PIN11_PAD_STRENGTH_MSB WLAN_GPIO_PIN11_PAD_STRENGTH_MSB +#define GPIO_PIN11_PAD_STRENGTH_LSB WLAN_GPIO_PIN11_PAD_STRENGTH_LSB +#define GPIO_PIN11_PAD_STRENGTH_MASK WLAN_GPIO_PIN11_PAD_STRENGTH_MASK +#define GPIO_PIN11_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x) +#define GPIO_PIN11_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x) +#define GPIO_PIN11_PAD_DRIVER_MSB WLAN_GPIO_PIN11_PAD_DRIVER_MSB +#define GPIO_PIN11_PAD_DRIVER_LSB WLAN_GPIO_PIN11_PAD_DRIVER_LSB +#define GPIO_PIN11_PAD_DRIVER_MASK WLAN_GPIO_PIN11_PAD_DRIVER_MASK +#define GPIO_PIN11_PAD_DRIVER_GET(x) WLAN_GPIO_PIN11_PAD_DRIVER_GET(x) +#define GPIO_PIN11_PAD_DRIVER_SET(x) WLAN_GPIO_PIN11_PAD_DRIVER_SET(x) +#define GPIO_PIN11_SOURCE_MSB WLAN_GPIO_PIN11_SOURCE_MSB +#define GPIO_PIN11_SOURCE_LSB WLAN_GPIO_PIN11_SOURCE_LSB +#define GPIO_PIN11_SOURCE_MASK WLAN_GPIO_PIN11_SOURCE_MASK +#define GPIO_PIN11_SOURCE_GET(x) WLAN_GPIO_PIN11_SOURCE_GET(x) +#define GPIO_PIN11_SOURCE_SET(x) WLAN_GPIO_PIN11_SOURCE_SET(x) +#define GPIO_PIN12_ADDRESS WLAN_GPIO_PIN12_ADDRESS +#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_OFFSET +#define GPIO_PIN12_CONFIG_MSB WLAN_GPIO_PIN12_CONFIG_MSB +#define GPIO_PIN12_CONFIG_LSB WLAN_GPIO_PIN12_CONFIG_LSB +#define GPIO_PIN12_CONFIG_MASK WLAN_GPIO_PIN12_CONFIG_MASK +#define GPIO_PIN12_CONFIG_GET(x) WLAN_GPIO_PIN12_CONFIG_GET(x) +#define GPIO_PIN12_CONFIG_SET(x) WLAN_GPIO_PIN12_CONFIG_SET(x) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB +#define GPIO_PIN12_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB +#define GPIO_PIN12_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN12_INT_TYPE_MSB WLAN_GPIO_PIN12_INT_TYPE_MSB +#define GPIO_PIN12_INT_TYPE_LSB WLAN_GPIO_PIN12_INT_TYPE_LSB +#define GPIO_PIN12_INT_TYPE_MASK WLAN_GPIO_PIN12_INT_TYPE_MASK +#define GPIO_PIN12_INT_TYPE_GET(x) WLAN_GPIO_PIN12_INT_TYPE_GET(x) +#define GPIO_PIN12_INT_TYPE_SET(x) WLAN_GPIO_PIN12_INT_TYPE_SET(x) +#define GPIO_PIN12_PAD_PULL_MSB WLAN_GPIO_PIN12_PAD_PULL_MSB +#define GPIO_PIN12_PAD_PULL_LSB WLAN_GPIO_PIN12_PAD_PULL_LSB +#define GPIO_PIN12_PAD_PULL_MASK WLAN_GPIO_PIN12_PAD_PULL_MASK +#define GPIO_PIN12_PAD_PULL_GET(x) WLAN_GPIO_PIN12_PAD_PULL_GET(x) +#define GPIO_PIN12_PAD_PULL_SET(x) WLAN_GPIO_PIN12_PAD_PULL_SET(x) +#define GPIO_PIN12_PAD_STRENGTH_MSB WLAN_GPIO_PIN12_PAD_STRENGTH_MSB +#define GPIO_PIN12_PAD_STRENGTH_LSB WLAN_GPIO_PIN12_PAD_STRENGTH_LSB +#define GPIO_PIN12_PAD_STRENGTH_MASK WLAN_GPIO_PIN12_PAD_STRENGTH_MASK +#define GPIO_PIN12_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x) +#define GPIO_PIN12_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x) +#define GPIO_PIN12_PAD_DRIVER_MSB WLAN_GPIO_PIN12_PAD_DRIVER_MSB +#define GPIO_PIN12_PAD_DRIVER_LSB WLAN_GPIO_PIN12_PAD_DRIVER_LSB +#define GPIO_PIN12_PAD_DRIVER_MASK WLAN_GPIO_PIN12_PAD_DRIVER_MASK +#define GPIO_PIN12_PAD_DRIVER_GET(x) WLAN_GPIO_PIN12_PAD_DRIVER_GET(x) +#define GPIO_PIN12_PAD_DRIVER_SET(x) WLAN_GPIO_PIN12_PAD_DRIVER_SET(x) +#define GPIO_PIN12_SOURCE_MSB WLAN_GPIO_PIN12_SOURCE_MSB +#define GPIO_PIN12_SOURCE_LSB WLAN_GPIO_PIN12_SOURCE_LSB +#define GPIO_PIN12_SOURCE_MASK WLAN_GPIO_PIN12_SOURCE_MASK +#define GPIO_PIN12_SOURCE_GET(x) WLAN_GPIO_PIN12_SOURCE_GET(x) +#define GPIO_PIN12_SOURCE_SET(x) WLAN_GPIO_PIN12_SOURCE_SET(x) +#define GPIO_PIN13_ADDRESS WLAN_GPIO_PIN13_ADDRESS +#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_OFFSET +#define GPIO_PIN13_CONFIG_MSB WLAN_GPIO_PIN13_CONFIG_MSB +#define GPIO_PIN13_CONFIG_LSB WLAN_GPIO_PIN13_CONFIG_LSB +#define GPIO_PIN13_CONFIG_MASK WLAN_GPIO_PIN13_CONFIG_MASK +#define GPIO_PIN13_CONFIG_GET(x) WLAN_GPIO_PIN13_CONFIG_GET(x) +#define GPIO_PIN13_CONFIG_SET(x) WLAN_GPIO_PIN13_CONFIG_SET(x) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB +#define GPIO_PIN13_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB +#define GPIO_PIN13_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN13_INT_TYPE_MSB WLAN_GPIO_PIN13_INT_TYPE_MSB +#define GPIO_PIN13_INT_TYPE_LSB WLAN_GPIO_PIN13_INT_TYPE_LSB +#define GPIO_PIN13_INT_TYPE_MASK WLAN_GPIO_PIN13_INT_TYPE_MASK +#define GPIO_PIN13_INT_TYPE_GET(x) WLAN_GPIO_PIN13_INT_TYPE_GET(x) +#define GPIO_PIN13_INT_TYPE_SET(x) WLAN_GPIO_PIN13_INT_TYPE_SET(x) +#define GPIO_PIN13_PAD_PULL_MSB WLAN_GPIO_PIN13_PAD_PULL_MSB +#define GPIO_PIN13_PAD_PULL_LSB WLAN_GPIO_PIN13_PAD_PULL_LSB +#define GPIO_PIN13_PAD_PULL_MASK WLAN_GPIO_PIN13_PAD_PULL_MASK +#define GPIO_PIN13_PAD_PULL_GET(x) WLAN_GPIO_PIN13_PAD_PULL_GET(x) +#define GPIO_PIN13_PAD_PULL_SET(x) WLAN_GPIO_PIN13_PAD_PULL_SET(x) +#define GPIO_PIN13_PAD_STRENGTH_MSB WLAN_GPIO_PIN13_PAD_STRENGTH_MSB +#define GPIO_PIN13_PAD_STRENGTH_LSB WLAN_GPIO_PIN13_PAD_STRENGTH_LSB +#define GPIO_PIN13_PAD_STRENGTH_MASK WLAN_GPIO_PIN13_PAD_STRENGTH_MASK +#define GPIO_PIN13_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x) +#define GPIO_PIN13_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x) +#define GPIO_PIN13_PAD_DRIVER_MSB WLAN_GPIO_PIN13_PAD_DRIVER_MSB +#define GPIO_PIN13_PAD_DRIVER_LSB WLAN_GPIO_PIN13_PAD_DRIVER_LSB +#define GPIO_PIN13_PAD_DRIVER_MASK WLAN_GPIO_PIN13_PAD_DRIVER_MASK +#define GPIO_PIN13_PAD_DRIVER_GET(x) WLAN_GPIO_PIN13_PAD_DRIVER_GET(x) +#define GPIO_PIN13_PAD_DRIVER_SET(x) WLAN_GPIO_PIN13_PAD_DRIVER_SET(x) +#define GPIO_PIN13_SOURCE_MSB WLAN_GPIO_PIN13_SOURCE_MSB +#define GPIO_PIN13_SOURCE_LSB WLAN_GPIO_PIN13_SOURCE_LSB +#define GPIO_PIN13_SOURCE_MASK WLAN_GPIO_PIN13_SOURCE_MASK +#define GPIO_PIN13_SOURCE_GET(x) WLAN_GPIO_PIN13_SOURCE_GET(x) +#define GPIO_PIN13_SOURCE_SET(x) WLAN_GPIO_PIN13_SOURCE_SET(x) +#define GPIO_PIN14_ADDRESS WLAN_GPIO_PIN14_ADDRESS +#define GPIO_PIN14_OFFSET WLAN_GPIO_PIN14_OFFSET +#define GPIO_PIN14_CONFIG_MSB WLAN_GPIO_PIN14_CONFIG_MSB +#define GPIO_PIN14_CONFIG_LSB WLAN_GPIO_PIN14_CONFIG_LSB +#define GPIO_PIN14_CONFIG_MASK WLAN_GPIO_PIN14_CONFIG_MASK +#define GPIO_PIN14_CONFIG_GET(x) WLAN_GPIO_PIN14_CONFIG_GET(x) +#define GPIO_PIN14_CONFIG_SET(x) WLAN_GPIO_PIN14_CONFIG_SET(x) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB +#define GPIO_PIN14_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB +#define GPIO_PIN14_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN14_INT_TYPE_MSB WLAN_GPIO_PIN14_INT_TYPE_MSB +#define GPIO_PIN14_INT_TYPE_LSB WLAN_GPIO_PIN14_INT_TYPE_LSB +#define GPIO_PIN14_INT_TYPE_MASK WLAN_GPIO_PIN14_INT_TYPE_MASK +#define GPIO_PIN14_INT_TYPE_GET(x) WLAN_GPIO_PIN14_INT_TYPE_GET(x) +#define GPIO_PIN14_INT_TYPE_SET(x) WLAN_GPIO_PIN14_INT_TYPE_SET(x) +#define GPIO_PIN14_PAD_PULL_MSB WLAN_GPIO_PIN14_PAD_PULL_MSB +#define GPIO_PIN14_PAD_PULL_LSB WLAN_GPIO_PIN14_PAD_PULL_LSB +#define GPIO_PIN14_PAD_PULL_MASK WLAN_GPIO_PIN14_PAD_PULL_MASK +#define GPIO_PIN14_PAD_PULL_GET(x) WLAN_GPIO_PIN14_PAD_PULL_GET(x) +#define GPIO_PIN14_PAD_PULL_SET(x) WLAN_GPIO_PIN14_PAD_PULL_SET(x) +#define GPIO_PIN14_PAD_STRENGTH_MSB WLAN_GPIO_PIN14_PAD_STRENGTH_MSB +#define GPIO_PIN14_PAD_STRENGTH_LSB WLAN_GPIO_PIN14_PAD_STRENGTH_LSB +#define GPIO_PIN14_PAD_STRENGTH_MASK WLAN_GPIO_PIN14_PAD_STRENGTH_MASK +#define GPIO_PIN14_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x) +#define GPIO_PIN14_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x) +#define GPIO_PIN14_PAD_DRIVER_MSB WLAN_GPIO_PIN14_PAD_DRIVER_MSB +#define GPIO_PIN14_PAD_DRIVER_LSB WLAN_GPIO_PIN14_PAD_DRIVER_LSB +#define GPIO_PIN14_PAD_DRIVER_MASK WLAN_GPIO_PIN14_PAD_DRIVER_MASK +#define GPIO_PIN14_PAD_DRIVER_GET(x) WLAN_GPIO_PIN14_PAD_DRIVER_GET(x) +#define GPIO_PIN14_PAD_DRIVER_SET(x) WLAN_GPIO_PIN14_PAD_DRIVER_SET(x) +#define GPIO_PIN14_SOURCE_MSB WLAN_GPIO_PIN14_SOURCE_MSB +#define GPIO_PIN14_SOURCE_LSB WLAN_GPIO_PIN14_SOURCE_LSB +#define GPIO_PIN14_SOURCE_MASK WLAN_GPIO_PIN14_SOURCE_MASK +#define GPIO_PIN14_SOURCE_GET(x) WLAN_GPIO_PIN14_SOURCE_GET(x) +#define GPIO_PIN14_SOURCE_SET(x) WLAN_GPIO_PIN14_SOURCE_SET(x) +#define GPIO_PIN15_ADDRESS WLAN_GPIO_PIN15_ADDRESS +#define GPIO_PIN15_OFFSET WLAN_GPIO_PIN15_OFFSET +#define GPIO_PIN15_CONFIG_MSB WLAN_GPIO_PIN15_CONFIG_MSB +#define GPIO_PIN15_CONFIG_LSB WLAN_GPIO_PIN15_CONFIG_LSB +#define GPIO_PIN15_CONFIG_MASK WLAN_GPIO_PIN15_CONFIG_MASK +#define GPIO_PIN15_CONFIG_GET(x) WLAN_GPIO_PIN15_CONFIG_GET(x) +#define GPIO_PIN15_CONFIG_SET(x) WLAN_GPIO_PIN15_CONFIG_SET(x) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB +#define GPIO_PIN15_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB +#define GPIO_PIN15_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN15_INT_TYPE_MSB WLAN_GPIO_PIN15_INT_TYPE_MSB +#define GPIO_PIN15_INT_TYPE_LSB WLAN_GPIO_PIN15_INT_TYPE_LSB +#define GPIO_PIN15_INT_TYPE_MASK WLAN_GPIO_PIN15_INT_TYPE_MASK +#define GPIO_PIN15_INT_TYPE_GET(x) WLAN_GPIO_PIN15_INT_TYPE_GET(x) +#define GPIO_PIN15_INT_TYPE_SET(x) WLAN_GPIO_PIN15_INT_TYPE_SET(x) +#define GPIO_PIN15_PAD_PULL_MSB WLAN_GPIO_PIN15_PAD_PULL_MSB +#define GPIO_PIN15_PAD_PULL_LSB WLAN_GPIO_PIN15_PAD_PULL_LSB +#define GPIO_PIN15_PAD_PULL_MASK WLAN_GPIO_PIN15_PAD_PULL_MASK +#define GPIO_PIN15_PAD_PULL_GET(x) WLAN_GPIO_PIN15_PAD_PULL_GET(x) +#define GPIO_PIN15_PAD_PULL_SET(x) WLAN_GPIO_PIN15_PAD_PULL_SET(x) +#define GPIO_PIN15_PAD_STRENGTH_MSB WLAN_GPIO_PIN15_PAD_STRENGTH_MSB +#define GPIO_PIN15_PAD_STRENGTH_LSB WLAN_GPIO_PIN15_PAD_STRENGTH_LSB +#define GPIO_PIN15_PAD_STRENGTH_MASK WLAN_GPIO_PIN15_PAD_STRENGTH_MASK +#define GPIO_PIN15_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x) +#define GPIO_PIN15_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x) +#define GPIO_PIN15_PAD_DRIVER_MSB WLAN_GPIO_PIN15_PAD_DRIVER_MSB +#define GPIO_PIN15_PAD_DRIVER_LSB WLAN_GPIO_PIN15_PAD_DRIVER_LSB +#define GPIO_PIN15_PAD_DRIVER_MASK WLAN_GPIO_PIN15_PAD_DRIVER_MASK +#define GPIO_PIN15_PAD_DRIVER_GET(x) WLAN_GPIO_PIN15_PAD_DRIVER_GET(x) +#define GPIO_PIN15_PAD_DRIVER_SET(x) WLAN_GPIO_PIN15_PAD_DRIVER_SET(x) +#define GPIO_PIN15_SOURCE_MSB WLAN_GPIO_PIN15_SOURCE_MSB +#define GPIO_PIN15_SOURCE_LSB WLAN_GPIO_PIN15_SOURCE_LSB +#define GPIO_PIN15_SOURCE_MASK WLAN_GPIO_PIN15_SOURCE_MASK +#define GPIO_PIN15_SOURCE_GET(x) WLAN_GPIO_PIN15_SOURCE_GET(x) +#define GPIO_PIN15_SOURCE_SET(x) WLAN_GPIO_PIN15_SOURCE_SET(x) +#define GPIO_PIN16_ADDRESS WLAN_GPIO_PIN16_ADDRESS +#define GPIO_PIN16_OFFSET WLAN_GPIO_PIN16_OFFSET +#define GPIO_PIN16_CONFIG_MSB WLAN_GPIO_PIN16_CONFIG_MSB +#define GPIO_PIN16_CONFIG_LSB WLAN_GPIO_PIN16_CONFIG_LSB +#define GPIO_PIN16_CONFIG_MASK WLAN_GPIO_PIN16_CONFIG_MASK +#define GPIO_PIN16_CONFIG_GET(x) WLAN_GPIO_PIN16_CONFIG_GET(x) +#define GPIO_PIN16_CONFIG_SET(x) WLAN_GPIO_PIN16_CONFIG_SET(x) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB +#define GPIO_PIN16_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB +#define GPIO_PIN16_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN16_INT_TYPE_MSB WLAN_GPIO_PIN16_INT_TYPE_MSB +#define GPIO_PIN16_INT_TYPE_LSB WLAN_GPIO_PIN16_INT_TYPE_LSB +#define GPIO_PIN16_INT_TYPE_MASK WLAN_GPIO_PIN16_INT_TYPE_MASK +#define GPIO_PIN16_INT_TYPE_GET(x) WLAN_GPIO_PIN16_INT_TYPE_GET(x) +#define GPIO_PIN16_INT_TYPE_SET(x) WLAN_GPIO_PIN16_INT_TYPE_SET(x) +#define GPIO_PIN16_PAD_PULL_MSB WLAN_GPIO_PIN16_PAD_PULL_MSB +#define GPIO_PIN16_PAD_PULL_LSB WLAN_GPIO_PIN16_PAD_PULL_LSB +#define GPIO_PIN16_PAD_PULL_MASK WLAN_GPIO_PIN16_PAD_PULL_MASK +#define GPIO_PIN16_PAD_PULL_GET(x) WLAN_GPIO_PIN16_PAD_PULL_GET(x) +#define GPIO_PIN16_PAD_PULL_SET(x) WLAN_GPIO_PIN16_PAD_PULL_SET(x) +#define GPIO_PIN16_PAD_STRENGTH_MSB WLAN_GPIO_PIN16_PAD_STRENGTH_MSB +#define GPIO_PIN16_PAD_STRENGTH_LSB WLAN_GPIO_PIN16_PAD_STRENGTH_LSB +#define GPIO_PIN16_PAD_STRENGTH_MASK WLAN_GPIO_PIN16_PAD_STRENGTH_MASK +#define GPIO_PIN16_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x) +#define GPIO_PIN16_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x) +#define GPIO_PIN16_PAD_DRIVER_MSB WLAN_GPIO_PIN16_PAD_DRIVER_MSB +#define GPIO_PIN16_PAD_DRIVER_LSB WLAN_GPIO_PIN16_PAD_DRIVER_LSB +#define GPIO_PIN16_PAD_DRIVER_MASK WLAN_GPIO_PIN16_PAD_DRIVER_MASK +#define GPIO_PIN16_PAD_DRIVER_GET(x) WLAN_GPIO_PIN16_PAD_DRIVER_GET(x) +#define GPIO_PIN16_PAD_DRIVER_SET(x) WLAN_GPIO_PIN16_PAD_DRIVER_SET(x) +#define GPIO_PIN16_SOURCE_MSB WLAN_GPIO_PIN16_SOURCE_MSB +#define GPIO_PIN16_SOURCE_LSB WLAN_GPIO_PIN16_SOURCE_LSB +#define GPIO_PIN16_SOURCE_MASK WLAN_GPIO_PIN16_SOURCE_MASK +#define GPIO_PIN16_SOURCE_GET(x) WLAN_GPIO_PIN16_SOURCE_GET(x) +#define GPIO_PIN16_SOURCE_SET(x) WLAN_GPIO_PIN16_SOURCE_SET(x) +#define GPIO_PIN17_ADDRESS WLAN_GPIO_PIN17_ADDRESS +#define GPIO_PIN17_OFFSET WLAN_GPIO_PIN17_OFFSET +#define GPIO_PIN17_CONFIG_MSB WLAN_GPIO_PIN17_CONFIG_MSB +#define GPIO_PIN17_CONFIG_LSB WLAN_GPIO_PIN17_CONFIG_LSB +#define GPIO_PIN17_CONFIG_MASK WLAN_GPIO_PIN17_CONFIG_MASK +#define GPIO_PIN17_CONFIG_GET(x) WLAN_GPIO_PIN17_CONFIG_GET(x) +#define GPIO_PIN17_CONFIG_SET(x) WLAN_GPIO_PIN17_CONFIG_SET(x) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB +#define GPIO_PIN17_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB +#define GPIO_PIN17_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN17_INT_TYPE_MSB WLAN_GPIO_PIN17_INT_TYPE_MSB +#define GPIO_PIN17_INT_TYPE_LSB WLAN_GPIO_PIN17_INT_TYPE_LSB +#define GPIO_PIN17_INT_TYPE_MASK WLAN_GPIO_PIN17_INT_TYPE_MASK +#define GPIO_PIN17_INT_TYPE_GET(x) WLAN_GPIO_PIN17_INT_TYPE_GET(x) +#define GPIO_PIN17_INT_TYPE_SET(x) WLAN_GPIO_PIN17_INT_TYPE_SET(x) +#define GPIO_PIN17_PAD_PULL_MSB WLAN_GPIO_PIN17_PAD_PULL_MSB +#define GPIO_PIN17_PAD_PULL_LSB WLAN_GPIO_PIN17_PAD_PULL_LSB +#define GPIO_PIN17_PAD_PULL_MASK WLAN_GPIO_PIN17_PAD_PULL_MASK +#define GPIO_PIN17_PAD_PULL_GET(x) WLAN_GPIO_PIN17_PAD_PULL_GET(x) +#define GPIO_PIN17_PAD_PULL_SET(x) WLAN_GPIO_PIN17_PAD_PULL_SET(x) +#define GPIO_PIN17_PAD_STRENGTH_MSB WLAN_GPIO_PIN17_PAD_STRENGTH_MSB +#define GPIO_PIN17_PAD_STRENGTH_LSB WLAN_GPIO_PIN17_PAD_STRENGTH_LSB +#define GPIO_PIN17_PAD_STRENGTH_MASK WLAN_GPIO_PIN17_PAD_STRENGTH_MASK +#define GPIO_PIN17_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x) +#define GPIO_PIN17_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x) +#define GPIO_PIN17_PAD_DRIVER_MSB WLAN_GPIO_PIN17_PAD_DRIVER_MSB +#define GPIO_PIN17_PAD_DRIVER_LSB WLAN_GPIO_PIN17_PAD_DRIVER_LSB +#define GPIO_PIN17_PAD_DRIVER_MASK WLAN_GPIO_PIN17_PAD_DRIVER_MASK +#define GPIO_PIN17_PAD_DRIVER_GET(x) WLAN_GPIO_PIN17_PAD_DRIVER_GET(x) +#define GPIO_PIN17_PAD_DRIVER_SET(x) WLAN_GPIO_PIN17_PAD_DRIVER_SET(x) +#define GPIO_PIN17_SOURCE_MSB WLAN_GPIO_PIN17_SOURCE_MSB +#define GPIO_PIN17_SOURCE_LSB WLAN_GPIO_PIN17_SOURCE_LSB +#define GPIO_PIN17_SOURCE_MASK WLAN_GPIO_PIN17_SOURCE_MASK +#define GPIO_PIN17_SOURCE_GET(x) WLAN_GPIO_PIN17_SOURCE_GET(x) +#define GPIO_PIN17_SOURCE_SET(x) WLAN_GPIO_PIN17_SOURCE_SET(x) +#define GPIO_PIN18_ADDRESS WLAN_GPIO_PIN18_ADDRESS +#define GPIO_PIN18_OFFSET WLAN_GPIO_PIN18_OFFSET +#define GPIO_PIN18_CONFIG_MSB WLAN_GPIO_PIN18_CONFIG_MSB +#define GPIO_PIN18_CONFIG_LSB WLAN_GPIO_PIN18_CONFIG_LSB +#define GPIO_PIN18_CONFIG_MASK WLAN_GPIO_PIN18_CONFIG_MASK +#define GPIO_PIN18_CONFIG_GET(x) WLAN_GPIO_PIN18_CONFIG_GET(x) +#define GPIO_PIN18_CONFIG_SET(x) WLAN_GPIO_PIN18_CONFIG_SET(x) +#define GPIO_PIN18_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB +#define GPIO_PIN18_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB +#define GPIO_PIN18_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK +#define GPIO_PIN18_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN18_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN18_INT_TYPE_MSB WLAN_GPIO_PIN18_INT_TYPE_MSB +#define GPIO_PIN18_INT_TYPE_LSB WLAN_GPIO_PIN18_INT_TYPE_LSB +#define GPIO_PIN18_INT_TYPE_MASK WLAN_GPIO_PIN18_INT_TYPE_MASK +#define GPIO_PIN18_INT_TYPE_GET(x) WLAN_GPIO_PIN18_INT_TYPE_GET(x) +#define GPIO_PIN18_INT_TYPE_SET(x) WLAN_GPIO_PIN18_INT_TYPE_SET(x) +#define GPIO_PIN18_PAD_PULL_MSB WLAN_GPIO_PIN18_PAD_PULL_MSB +#define GPIO_PIN18_PAD_PULL_LSB WLAN_GPIO_PIN18_PAD_PULL_LSB +#define GPIO_PIN18_PAD_PULL_MASK WLAN_GPIO_PIN18_PAD_PULL_MASK +#define GPIO_PIN18_PAD_PULL_GET(x) WLAN_GPIO_PIN18_PAD_PULL_GET(x) +#define GPIO_PIN18_PAD_PULL_SET(x) WLAN_GPIO_PIN18_PAD_PULL_SET(x) +#define GPIO_PIN18_PAD_STRENGTH_MSB WLAN_GPIO_PIN18_PAD_STRENGTH_MSB +#define GPIO_PIN18_PAD_STRENGTH_LSB WLAN_GPIO_PIN18_PAD_STRENGTH_LSB +#define GPIO_PIN18_PAD_STRENGTH_MASK WLAN_GPIO_PIN18_PAD_STRENGTH_MASK +#define GPIO_PIN18_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x) +#define GPIO_PIN18_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x) +#define GPIO_PIN18_PAD_DRIVER_MSB WLAN_GPIO_PIN18_PAD_DRIVER_MSB +#define GPIO_PIN18_PAD_DRIVER_LSB WLAN_GPIO_PIN18_PAD_DRIVER_LSB +#define GPIO_PIN18_PAD_DRIVER_MASK WLAN_GPIO_PIN18_PAD_DRIVER_MASK +#define GPIO_PIN18_PAD_DRIVER_GET(x) WLAN_GPIO_PIN18_PAD_DRIVER_GET(x) +#define GPIO_PIN18_PAD_DRIVER_SET(x) WLAN_GPIO_PIN18_PAD_DRIVER_SET(x) +#define GPIO_PIN18_SOURCE_MSB WLAN_GPIO_PIN18_SOURCE_MSB +#define GPIO_PIN18_SOURCE_LSB WLAN_GPIO_PIN18_SOURCE_LSB +#define GPIO_PIN18_SOURCE_MASK WLAN_GPIO_PIN18_SOURCE_MASK +#define GPIO_PIN18_SOURCE_GET(x) WLAN_GPIO_PIN18_SOURCE_GET(x) +#define GPIO_PIN18_SOURCE_SET(x) WLAN_GPIO_PIN18_SOURCE_SET(x) +#define GPIO_PIN19_ADDRESS WLAN_GPIO_PIN19_ADDRESS +#define GPIO_PIN19_OFFSET WLAN_GPIO_PIN19_OFFSET +#define GPIO_PIN19_CONFIG_MSB WLAN_GPIO_PIN19_CONFIG_MSB +#define GPIO_PIN19_CONFIG_LSB WLAN_GPIO_PIN19_CONFIG_LSB +#define GPIO_PIN19_CONFIG_MASK WLAN_GPIO_PIN19_CONFIG_MASK +#define GPIO_PIN19_CONFIG_GET(x) WLAN_GPIO_PIN19_CONFIG_GET(x) +#define GPIO_PIN19_CONFIG_SET(x) WLAN_GPIO_PIN19_CONFIG_SET(x) +#define GPIO_PIN19_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB +#define GPIO_PIN19_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB +#define GPIO_PIN19_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK +#define GPIO_PIN19_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN19_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN19_INT_TYPE_MSB WLAN_GPIO_PIN19_INT_TYPE_MSB +#define GPIO_PIN19_INT_TYPE_LSB WLAN_GPIO_PIN19_INT_TYPE_LSB +#define GPIO_PIN19_INT_TYPE_MASK WLAN_GPIO_PIN19_INT_TYPE_MASK +#define GPIO_PIN19_INT_TYPE_GET(x) WLAN_GPIO_PIN19_INT_TYPE_GET(x) +#define GPIO_PIN19_INT_TYPE_SET(x) WLAN_GPIO_PIN19_INT_TYPE_SET(x) +#define GPIO_PIN19_PAD_PULL_MSB WLAN_GPIO_PIN19_PAD_PULL_MSB +#define GPIO_PIN19_PAD_PULL_LSB WLAN_GPIO_PIN19_PAD_PULL_LSB +#define GPIO_PIN19_PAD_PULL_MASK WLAN_GPIO_PIN19_PAD_PULL_MASK +#define GPIO_PIN19_PAD_PULL_GET(x) WLAN_GPIO_PIN19_PAD_PULL_GET(x) +#define GPIO_PIN19_PAD_PULL_SET(x) WLAN_GPIO_PIN19_PAD_PULL_SET(x) +#define GPIO_PIN19_PAD_STRENGTH_MSB WLAN_GPIO_PIN19_PAD_STRENGTH_MSB +#define GPIO_PIN19_PAD_STRENGTH_LSB WLAN_GPIO_PIN19_PAD_STRENGTH_LSB +#define GPIO_PIN19_PAD_STRENGTH_MASK WLAN_GPIO_PIN19_PAD_STRENGTH_MASK +#define GPIO_PIN19_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x) +#define GPIO_PIN19_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x) +#define GPIO_PIN19_PAD_DRIVER_MSB WLAN_GPIO_PIN19_PAD_DRIVER_MSB +#define GPIO_PIN19_PAD_DRIVER_LSB WLAN_GPIO_PIN19_PAD_DRIVER_LSB +#define GPIO_PIN19_PAD_DRIVER_MASK WLAN_GPIO_PIN19_PAD_DRIVER_MASK +#define GPIO_PIN19_PAD_DRIVER_GET(x) WLAN_GPIO_PIN19_PAD_DRIVER_GET(x) +#define GPIO_PIN19_PAD_DRIVER_SET(x) WLAN_GPIO_PIN19_PAD_DRIVER_SET(x) +#define GPIO_PIN19_SOURCE_MSB WLAN_GPIO_PIN19_SOURCE_MSB +#define GPIO_PIN19_SOURCE_LSB WLAN_GPIO_PIN19_SOURCE_LSB +#define GPIO_PIN19_SOURCE_MASK WLAN_GPIO_PIN19_SOURCE_MASK +#define GPIO_PIN19_SOURCE_GET(x) WLAN_GPIO_PIN19_SOURCE_GET(x) +#define GPIO_PIN19_SOURCE_SET(x) WLAN_GPIO_PIN19_SOURCE_SET(x) +#define GPIO_PIN20_ADDRESS WLAN_GPIO_PIN20_ADDRESS +#define GPIO_PIN20_OFFSET WLAN_GPIO_PIN20_OFFSET +#define GPIO_PIN20_CONFIG_MSB WLAN_GPIO_PIN20_CONFIG_MSB +#define GPIO_PIN20_CONFIG_LSB WLAN_GPIO_PIN20_CONFIG_LSB +#define GPIO_PIN20_CONFIG_MASK WLAN_GPIO_PIN20_CONFIG_MASK +#define GPIO_PIN20_CONFIG_GET(x) WLAN_GPIO_PIN20_CONFIG_GET(x) +#define GPIO_PIN20_CONFIG_SET(x) WLAN_GPIO_PIN20_CONFIG_SET(x) +#define GPIO_PIN20_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB +#define GPIO_PIN20_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB +#define GPIO_PIN20_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK +#define GPIO_PIN20_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN20_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN20_INT_TYPE_MSB WLAN_GPIO_PIN20_INT_TYPE_MSB +#define GPIO_PIN20_INT_TYPE_LSB WLAN_GPIO_PIN20_INT_TYPE_LSB +#define GPIO_PIN20_INT_TYPE_MASK WLAN_GPIO_PIN20_INT_TYPE_MASK +#define GPIO_PIN20_INT_TYPE_GET(x) WLAN_GPIO_PIN20_INT_TYPE_GET(x) +#define GPIO_PIN20_INT_TYPE_SET(x) WLAN_GPIO_PIN20_INT_TYPE_SET(x) +#define GPIO_PIN20_PAD_PULL_MSB WLAN_GPIO_PIN20_PAD_PULL_MSB +#define GPIO_PIN20_PAD_PULL_LSB WLAN_GPIO_PIN20_PAD_PULL_LSB +#define GPIO_PIN20_PAD_PULL_MASK WLAN_GPIO_PIN20_PAD_PULL_MASK +#define GPIO_PIN20_PAD_PULL_GET(x) WLAN_GPIO_PIN20_PAD_PULL_GET(x) +#define GPIO_PIN20_PAD_PULL_SET(x) WLAN_GPIO_PIN20_PAD_PULL_SET(x) +#define GPIO_PIN20_PAD_STRENGTH_MSB WLAN_GPIO_PIN20_PAD_STRENGTH_MSB +#define GPIO_PIN20_PAD_STRENGTH_LSB WLAN_GPIO_PIN20_PAD_STRENGTH_LSB +#define GPIO_PIN20_PAD_STRENGTH_MASK WLAN_GPIO_PIN20_PAD_STRENGTH_MASK +#define GPIO_PIN20_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x) +#define GPIO_PIN20_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x) +#define GPIO_PIN20_PAD_DRIVER_MSB WLAN_GPIO_PIN20_PAD_DRIVER_MSB +#define GPIO_PIN20_PAD_DRIVER_LSB WLAN_GPIO_PIN20_PAD_DRIVER_LSB +#define GPIO_PIN20_PAD_DRIVER_MASK WLAN_GPIO_PIN20_PAD_DRIVER_MASK +#define GPIO_PIN20_PAD_DRIVER_GET(x) WLAN_GPIO_PIN20_PAD_DRIVER_GET(x) +#define GPIO_PIN20_PAD_DRIVER_SET(x) WLAN_GPIO_PIN20_PAD_DRIVER_SET(x) +#define GPIO_PIN20_SOURCE_MSB WLAN_GPIO_PIN20_SOURCE_MSB +#define GPIO_PIN20_SOURCE_LSB WLAN_GPIO_PIN20_SOURCE_LSB +#define GPIO_PIN20_SOURCE_MASK WLAN_GPIO_PIN20_SOURCE_MASK +#define GPIO_PIN20_SOURCE_GET(x) WLAN_GPIO_PIN20_SOURCE_GET(x) +#define GPIO_PIN20_SOURCE_SET(x) WLAN_GPIO_PIN20_SOURCE_SET(x) +#define GPIO_PIN21_ADDRESS WLAN_GPIO_PIN21_ADDRESS +#define GPIO_PIN21_OFFSET WLAN_GPIO_PIN21_OFFSET +#define GPIO_PIN21_CONFIG_MSB WLAN_GPIO_PIN21_CONFIG_MSB +#define GPIO_PIN21_CONFIG_LSB WLAN_GPIO_PIN21_CONFIG_LSB +#define GPIO_PIN21_CONFIG_MASK WLAN_GPIO_PIN21_CONFIG_MASK +#define GPIO_PIN21_CONFIG_GET(x) WLAN_GPIO_PIN21_CONFIG_GET(x) +#define GPIO_PIN21_CONFIG_SET(x) WLAN_GPIO_PIN21_CONFIG_SET(x) +#define GPIO_PIN21_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB +#define GPIO_PIN21_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB +#define GPIO_PIN21_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK +#define GPIO_PIN21_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN21_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN21_INT_TYPE_MSB WLAN_GPIO_PIN21_INT_TYPE_MSB +#define GPIO_PIN21_INT_TYPE_LSB WLAN_GPIO_PIN21_INT_TYPE_LSB +#define GPIO_PIN21_INT_TYPE_MASK WLAN_GPIO_PIN21_INT_TYPE_MASK +#define GPIO_PIN21_INT_TYPE_GET(x) WLAN_GPIO_PIN21_INT_TYPE_GET(x) +#define GPIO_PIN21_INT_TYPE_SET(x) WLAN_GPIO_PIN21_INT_TYPE_SET(x) +#define GPIO_PIN21_PAD_PULL_MSB WLAN_GPIO_PIN21_PAD_PULL_MSB +#define GPIO_PIN21_PAD_PULL_LSB WLAN_GPIO_PIN21_PAD_PULL_LSB +#define GPIO_PIN21_PAD_PULL_MASK WLAN_GPIO_PIN21_PAD_PULL_MASK +#define GPIO_PIN21_PAD_PULL_GET(x) WLAN_GPIO_PIN21_PAD_PULL_GET(x) +#define GPIO_PIN21_PAD_PULL_SET(x) WLAN_GPIO_PIN21_PAD_PULL_SET(x) +#define GPIO_PIN21_PAD_STRENGTH_MSB WLAN_GPIO_PIN21_PAD_STRENGTH_MSB +#define GPIO_PIN21_PAD_STRENGTH_LSB WLAN_GPIO_PIN21_PAD_STRENGTH_LSB +#define GPIO_PIN21_PAD_STRENGTH_MASK WLAN_GPIO_PIN21_PAD_STRENGTH_MASK +#define GPIO_PIN21_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x) +#define GPIO_PIN21_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x) +#define GPIO_PIN21_PAD_DRIVER_MSB WLAN_GPIO_PIN21_PAD_DRIVER_MSB +#define GPIO_PIN21_PAD_DRIVER_LSB WLAN_GPIO_PIN21_PAD_DRIVER_LSB +#define GPIO_PIN21_PAD_DRIVER_MASK WLAN_GPIO_PIN21_PAD_DRIVER_MASK +#define GPIO_PIN21_PAD_DRIVER_GET(x) WLAN_GPIO_PIN21_PAD_DRIVER_GET(x) +#define GPIO_PIN21_PAD_DRIVER_SET(x) WLAN_GPIO_PIN21_PAD_DRIVER_SET(x) +#define GPIO_PIN21_SOURCE_MSB WLAN_GPIO_PIN21_SOURCE_MSB +#define GPIO_PIN21_SOURCE_LSB WLAN_GPIO_PIN21_SOURCE_LSB +#define GPIO_PIN21_SOURCE_MASK WLAN_GPIO_PIN21_SOURCE_MASK +#define GPIO_PIN21_SOURCE_GET(x) WLAN_GPIO_PIN21_SOURCE_GET(x) +#define GPIO_PIN21_SOURCE_SET(x) WLAN_GPIO_PIN21_SOURCE_SET(x) +#define GPIO_PIN22_ADDRESS WLAN_GPIO_PIN22_ADDRESS +#define GPIO_PIN22_OFFSET WLAN_GPIO_PIN22_OFFSET +#define GPIO_PIN22_CONFIG_MSB WLAN_GPIO_PIN22_CONFIG_MSB +#define GPIO_PIN22_CONFIG_LSB WLAN_GPIO_PIN22_CONFIG_LSB +#define GPIO_PIN22_CONFIG_MASK WLAN_GPIO_PIN22_CONFIG_MASK +#define GPIO_PIN22_CONFIG_GET(x) WLAN_GPIO_PIN22_CONFIG_GET(x) +#define GPIO_PIN22_CONFIG_SET(x) WLAN_GPIO_PIN22_CONFIG_SET(x) +#define GPIO_PIN22_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB +#define GPIO_PIN22_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB +#define GPIO_PIN22_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK +#define GPIO_PIN22_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN22_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN22_INT_TYPE_MSB WLAN_GPIO_PIN22_INT_TYPE_MSB +#define GPIO_PIN22_INT_TYPE_LSB WLAN_GPIO_PIN22_INT_TYPE_LSB +#define GPIO_PIN22_INT_TYPE_MASK WLAN_GPIO_PIN22_INT_TYPE_MASK +#define GPIO_PIN22_INT_TYPE_GET(x) WLAN_GPIO_PIN22_INT_TYPE_GET(x) +#define GPIO_PIN22_INT_TYPE_SET(x) WLAN_GPIO_PIN22_INT_TYPE_SET(x) +#define GPIO_PIN22_PAD_PULL_MSB WLAN_GPIO_PIN22_PAD_PULL_MSB +#define GPIO_PIN22_PAD_PULL_LSB WLAN_GPIO_PIN22_PAD_PULL_LSB +#define GPIO_PIN22_PAD_PULL_MASK WLAN_GPIO_PIN22_PAD_PULL_MASK +#define GPIO_PIN22_PAD_PULL_GET(x) WLAN_GPIO_PIN22_PAD_PULL_GET(x) +#define GPIO_PIN22_PAD_PULL_SET(x) WLAN_GPIO_PIN22_PAD_PULL_SET(x) +#define GPIO_PIN22_PAD_STRENGTH_MSB WLAN_GPIO_PIN22_PAD_STRENGTH_MSB +#define GPIO_PIN22_PAD_STRENGTH_LSB WLAN_GPIO_PIN22_PAD_STRENGTH_LSB +#define GPIO_PIN22_PAD_STRENGTH_MASK WLAN_GPIO_PIN22_PAD_STRENGTH_MASK +#define GPIO_PIN22_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x) +#define GPIO_PIN22_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x) +#define GPIO_PIN22_PAD_DRIVER_MSB WLAN_GPIO_PIN22_PAD_DRIVER_MSB +#define GPIO_PIN22_PAD_DRIVER_LSB WLAN_GPIO_PIN22_PAD_DRIVER_LSB +#define GPIO_PIN22_PAD_DRIVER_MASK WLAN_GPIO_PIN22_PAD_DRIVER_MASK +#define GPIO_PIN22_PAD_DRIVER_GET(x) WLAN_GPIO_PIN22_PAD_DRIVER_GET(x) +#define GPIO_PIN22_PAD_DRIVER_SET(x) WLAN_GPIO_PIN22_PAD_DRIVER_SET(x) +#define GPIO_PIN22_SOURCE_MSB WLAN_GPIO_PIN22_SOURCE_MSB +#define GPIO_PIN22_SOURCE_LSB WLAN_GPIO_PIN22_SOURCE_LSB +#define GPIO_PIN22_SOURCE_MASK WLAN_GPIO_PIN22_SOURCE_MASK +#define GPIO_PIN22_SOURCE_GET(x) WLAN_GPIO_PIN22_SOURCE_GET(x) +#define GPIO_PIN22_SOURCE_SET(x) WLAN_GPIO_PIN22_SOURCE_SET(x) +#define GPIO_PIN23_ADDRESS WLAN_GPIO_PIN23_ADDRESS +#define GPIO_PIN23_OFFSET WLAN_GPIO_PIN23_OFFSET +#define GPIO_PIN23_CONFIG_MSB WLAN_GPIO_PIN23_CONFIG_MSB +#define GPIO_PIN23_CONFIG_LSB WLAN_GPIO_PIN23_CONFIG_LSB +#define GPIO_PIN23_CONFIG_MASK WLAN_GPIO_PIN23_CONFIG_MASK +#define GPIO_PIN23_CONFIG_GET(x) WLAN_GPIO_PIN23_CONFIG_GET(x) +#define GPIO_PIN23_CONFIG_SET(x) WLAN_GPIO_PIN23_CONFIG_SET(x) +#define GPIO_PIN23_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB +#define GPIO_PIN23_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB +#define GPIO_PIN23_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK +#define GPIO_PIN23_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN23_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN23_INT_TYPE_MSB WLAN_GPIO_PIN23_INT_TYPE_MSB +#define GPIO_PIN23_INT_TYPE_LSB WLAN_GPIO_PIN23_INT_TYPE_LSB +#define GPIO_PIN23_INT_TYPE_MASK WLAN_GPIO_PIN23_INT_TYPE_MASK +#define GPIO_PIN23_INT_TYPE_GET(x) WLAN_GPIO_PIN23_INT_TYPE_GET(x) +#define GPIO_PIN23_INT_TYPE_SET(x) WLAN_GPIO_PIN23_INT_TYPE_SET(x) +#define GPIO_PIN23_PAD_DRIVER_MSB WLAN_GPIO_PIN23_PAD_DRIVER_MSB +#define GPIO_PIN23_PAD_DRIVER_LSB WLAN_GPIO_PIN23_PAD_DRIVER_LSB +#define GPIO_PIN23_PAD_DRIVER_MASK WLAN_GPIO_PIN23_PAD_DRIVER_MASK +#define GPIO_PIN23_PAD_DRIVER_GET(x) WLAN_GPIO_PIN23_PAD_DRIVER_GET(x) +#define GPIO_PIN23_PAD_DRIVER_SET(x) WLAN_GPIO_PIN23_PAD_DRIVER_SET(x) +#define GPIO_PIN23_SOURCE_MSB WLAN_GPIO_PIN23_SOURCE_MSB +#define GPIO_PIN23_SOURCE_LSB WLAN_GPIO_PIN23_SOURCE_LSB +#define GPIO_PIN23_SOURCE_MASK WLAN_GPIO_PIN23_SOURCE_MASK +#define GPIO_PIN23_SOURCE_GET(x) WLAN_GPIO_PIN23_SOURCE_GET(x) +#define GPIO_PIN23_SOURCE_SET(x) WLAN_GPIO_PIN23_SOURCE_SET(x) +#define GPIO_PIN24_ADDRESS WLAN_GPIO_PIN24_ADDRESS +#define GPIO_PIN24_OFFSET WLAN_GPIO_PIN24_OFFSET +#define GPIO_PIN24_CONFIG_MSB WLAN_GPIO_PIN24_CONFIG_MSB +#define GPIO_PIN24_CONFIG_LSB WLAN_GPIO_PIN24_CONFIG_LSB +#define GPIO_PIN24_CONFIG_MASK WLAN_GPIO_PIN24_CONFIG_MASK +#define GPIO_PIN24_CONFIG_GET(x) WLAN_GPIO_PIN24_CONFIG_GET(x) +#define GPIO_PIN24_CONFIG_SET(x) WLAN_GPIO_PIN24_CONFIG_SET(x) +#define GPIO_PIN24_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB +#define GPIO_PIN24_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB +#define GPIO_PIN24_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK +#define GPIO_PIN24_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN24_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN24_INT_TYPE_MSB WLAN_GPIO_PIN24_INT_TYPE_MSB +#define GPIO_PIN24_INT_TYPE_LSB WLAN_GPIO_PIN24_INT_TYPE_LSB +#define GPIO_PIN24_INT_TYPE_MASK WLAN_GPIO_PIN24_INT_TYPE_MASK +#define GPIO_PIN24_INT_TYPE_GET(x) WLAN_GPIO_PIN24_INT_TYPE_GET(x) +#define GPIO_PIN24_INT_TYPE_SET(x) WLAN_GPIO_PIN24_INT_TYPE_SET(x) +#define GPIO_PIN24_PAD_DRIVER_MSB WLAN_GPIO_PIN24_PAD_DRIVER_MSB +#define GPIO_PIN24_PAD_DRIVER_LSB WLAN_GPIO_PIN24_PAD_DRIVER_LSB +#define GPIO_PIN24_PAD_DRIVER_MASK WLAN_GPIO_PIN24_PAD_DRIVER_MASK +#define GPIO_PIN24_PAD_DRIVER_GET(x) WLAN_GPIO_PIN24_PAD_DRIVER_GET(x) +#define GPIO_PIN24_PAD_DRIVER_SET(x) WLAN_GPIO_PIN24_PAD_DRIVER_SET(x) +#define GPIO_PIN24_SOURCE_MSB WLAN_GPIO_PIN24_SOURCE_MSB +#define GPIO_PIN24_SOURCE_LSB WLAN_GPIO_PIN24_SOURCE_LSB +#define GPIO_PIN24_SOURCE_MASK WLAN_GPIO_PIN24_SOURCE_MASK +#define GPIO_PIN24_SOURCE_GET(x) WLAN_GPIO_PIN24_SOURCE_GET(x) +#define GPIO_PIN24_SOURCE_SET(x) WLAN_GPIO_PIN24_SOURCE_SET(x) +#define GPIO_PIN25_ADDRESS WLAN_GPIO_PIN25_ADDRESS +#define GPIO_PIN25_OFFSET WLAN_GPIO_PIN25_OFFSET +#define GPIO_PIN25_CONFIG_MSB WLAN_GPIO_PIN25_CONFIG_MSB +#define GPIO_PIN25_CONFIG_LSB WLAN_GPIO_PIN25_CONFIG_LSB +#define GPIO_PIN25_CONFIG_MASK WLAN_GPIO_PIN25_CONFIG_MASK +#define GPIO_PIN25_CONFIG_GET(x) WLAN_GPIO_PIN25_CONFIG_GET(x) +#define GPIO_PIN25_CONFIG_SET(x) WLAN_GPIO_PIN25_CONFIG_SET(x) +#define GPIO_PIN25_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB +#define GPIO_PIN25_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB +#define GPIO_PIN25_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK +#define GPIO_PIN25_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN25_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN25_INT_TYPE_MSB WLAN_GPIO_PIN25_INT_TYPE_MSB +#define GPIO_PIN25_INT_TYPE_LSB WLAN_GPIO_PIN25_INT_TYPE_LSB +#define GPIO_PIN25_INT_TYPE_MASK WLAN_GPIO_PIN25_INT_TYPE_MASK +#define GPIO_PIN25_INT_TYPE_GET(x) WLAN_GPIO_PIN25_INT_TYPE_GET(x) +#define GPIO_PIN25_INT_TYPE_SET(x) WLAN_GPIO_PIN25_INT_TYPE_SET(x) +#define GPIO_PIN25_PAD_DRIVER_MSB WLAN_GPIO_PIN25_PAD_DRIVER_MSB +#define GPIO_PIN25_PAD_DRIVER_LSB WLAN_GPIO_PIN25_PAD_DRIVER_LSB +#define GPIO_PIN25_PAD_DRIVER_MASK WLAN_GPIO_PIN25_PAD_DRIVER_MASK +#define GPIO_PIN25_PAD_DRIVER_GET(x) WLAN_GPIO_PIN25_PAD_DRIVER_GET(x) +#define GPIO_PIN25_PAD_DRIVER_SET(x) WLAN_GPIO_PIN25_PAD_DRIVER_SET(x) +#define GPIO_PIN25_SOURCE_MSB WLAN_GPIO_PIN25_SOURCE_MSB +#define GPIO_PIN25_SOURCE_LSB WLAN_GPIO_PIN25_SOURCE_LSB +#define GPIO_PIN25_SOURCE_MASK WLAN_GPIO_PIN25_SOURCE_MASK +#define GPIO_PIN25_SOURCE_GET(x) WLAN_GPIO_PIN25_SOURCE_GET(x) +#define GPIO_PIN25_SOURCE_SET(x) WLAN_GPIO_PIN25_SOURCE_SET(x) +#define SIGMA_DELTA_ADDRESS WLAN_SIGMA_DELTA_ADDRESS +#define SIGMA_DELTA_OFFSET WLAN_SIGMA_DELTA_OFFSET +#define SIGMA_DELTA_ENABLE_MSB WLAN_SIGMA_DELTA_ENABLE_MSB +#define SIGMA_DELTA_ENABLE_LSB WLAN_SIGMA_DELTA_ENABLE_LSB +#define SIGMA_DELTA_ENABLE_MASK WLAN_SIGMA_DELTA_ENABLE_MASK +#define SIGMA_DELTA_ENABLE_GET(x) WLAN_SIGMA_DELTA_ENABLE_GET(x) +#define SIGMA_DELTA_ENABLE_SET(x) WLAN_SIGMA_DELTA_ENABLE_SET(x) +#define SIGMA_DELTA_PRESCALAR_MSB WLAN_SIGMA_DELTA_PRESCALAR_MSB +#define SIGMA_DELTA_PRESCALAR_LSB WLAN_SIGMA_DELTA_PRESCALAR_LSB +#define SIGMA_DELTA_PRESCALAR_MASK WLAN_SIGMA_DELTA_PRESCALAR_MASK +#define SIGMA_DELTA_PRESCALAR_GET(x) WLAN_SIGMA_DELTA_PRESCALAR_GET(x) +#define SIGMA_DELTA_PRESCALAR_SET(x) WLAN_SIGMA_DELTA_PRESCALAR_SET(x) +#define SIGMA_DELTA_TARGET_MSB WLAN_SIGMA_DELTA_TARGET_MSB +#define SIGMA_DELTA_TARGET_LSB WLAN_SIGMA_DELTA_TARGET_LSB +#define SIGMA_DELTA_TARGET_MASK WLAN_SIGMA_DELTA_TARGET_MASK +#define SIGMA_DELTA_TARGET_GET(x) WLAN_SIGMA_DELTA_TARGET_GET(x) +#define SIGMA_DELTA_TARGET_SET(x) WLAN_SIGMA_DELTA_TARGET_SET(x) +#define DEBUG_CONTROL_ADDRESS WLAN_DEBUG_CONTROL_ADDRESS +#define DEBUG_CONTROL_OFFSET WLAN_DEBUG_CONTROL_OFFSET +#define DEBUG_CONTROL_ENABLE_MSB WLAN_DEBUG_CONTROL_ENABLE_MSB +#define DEBUG_CONTROL_ENABLE_LSB WLAN_DEBUG_CONTROL_ENABLE_LSB +#define DEBUG_CONTROL_ENABLE_MASK WLAN_DEBUG_CONTROL_ENABLE_MASK +#define DEBUG_CONTROL_ENABLE_GET(x) WLAN_DEBUG_CONTROL_ENABLE_GET(x) +#define DEBUG_CONTROL_ENABLE_SET(x) WLAN_DEBUG_CONTROL_ENABLE_SET(x) +#define DEBUG_INPUT_SEL_ADDRESS WLAN_DEBUG_INPUT_SEL_ADDRESS +#define DEBUG_INPUT_SEL_OFFSET WLAN_DEBUG_INPUT_SEL_OFFSET +#define DEBUG_INPUT_SEL_SHIFT_MSB WLAN_DEBUG_INPUT_SEL_SHIFT_MSB +#define DEBUG_INPUT_SEL_SHIFT_LSB WLAN_DEBUG_INPUT_SEL_SHIFT_LSB +#define DEBUG_INPUT_SEL_SHIFT_MASK WLAN_DEBUG_INPUT_SEL_SHIFT_MASK +#define DEBUG_INPUT_SEL_SHIFT_GET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x) +#define DEBUG_INPUT_SEL_SHIFT_SET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x) +#define DEBUG_INPUT_SEL_SRC_MSB WLAN_DEBUG_INPUT_SEL_SRC_MSB +#define DEBUG_INPUT_SEL_SRC_LSB WLAN_DEBUG_INPUT_SEL_SRC_LSB +#define DEBUG_INPUT_SEL_SRC_MASK WLAN_DEBUG_INPUT_SEL_SRC_MASK +#define DEBUG_INPUT_SEL_SRC_GET(x) WLAN_DEBUG_INPUT_SEL_SRC_GET(x) +#define DEBUG_INPUT_SEL_SRC_SET(x) WLAN_DEBUG_INPUT_SEL_SRC_SET(x) +#define DEBUG_OUT_ADDRESS WLAN_DEBUG_OUT_ADDRESS +#define DEBUG_OUT_OFFSET WLAN_DEBUG_OUT_OFFSET +#define DEBUG_OUT_DATA_MSB WLAN_DEBUG_OUT_DATA_MSB +#define DEBUG_OUT_DATA_LSB WLAN_DEBUG_OUT_DATA_LSB +#define DEBUG_OUT_DATA_MASK WLAN_DEBUG_OUT_DATA_MASK +#define DEBUG_OUT_DATA_GET(x) WLAN_DEBUG_OUT_DATA_GET(x) +#define DEBUG_OUT_DATA_SET(x) WLAN_DEBUG_OUT_DATA_SET(x) +#define RESET_TUPLE_STATUS_ADDRESS WLAN_RESET_TUPLE_STATUS_ADDRESS +#define RESET_TUPLE_STATUS_OFFSET WLAN_RESET_TUPLE_STATUS_OFFSET +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h new file mode 100644 index 000000000000..f82f809171a0 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h @@ -0,0 +1,605 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2002-2010 Atheros Communications Inc. +// All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +/*****************************************************************************/ +/* AR6003 WLAN MAC DMA register definitions */ +/*****************************************************************************/ + +#ifndef _AR6000_DMAREG_H_ +#define _AR6000_DMAREG_H_ + +/* + * Definitions for the Atheros AR6003 chipset. + */ + +/* DMA Control and Interrupt Registers */ +#define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control register */ +#define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */ +#define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable */ +#define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software interrupt */ + +#define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue descriptor pointer */ + +#define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration and status register */ +#define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descriptor words */ +#define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data buffer words */ +#define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descriptor words */ +#define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data buffer words */ +#define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register access data words */ +#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */ +#define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */ +#define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disable */ + +#define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate threshold register */ +#define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF + +#define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt enable register */ +#define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt enable */ +#define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt disable */ + +#define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrupt Mitigation Threshold */ +#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */ +#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */ + +#define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt Mitigation Threshold */ +#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */ +#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */ + +#define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size config register */ +#define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame trigger level */ +#define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame trigger level */ +#define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */ +#define MAC_DMA_FTRIG_64B 0x00000010 /* default */ +#define MAC_DMA_FTRIG_128B 0x00000020 +#define MAC_DMA_FTRIG_192B 0x00000030 +#define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */ +#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800 + +#define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size config register */ +#define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of zero-length frame */ +#define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */ +#define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */ + +#define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control register */ +#define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow warning */ +#define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB counters */ +#define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counters */ +#define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter strobe, increment all */ + +#define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout prescale count */ +#define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */ + +#define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame received timeout */ +#define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */ + +#define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame trasmitted timeout */ +#define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */ +#define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */ + /* for which frame completions will cause */ + /* a reset of the no frame xmit'd timeout */ + +#define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive frame gap timeout */ +#define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */ + +#define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive frame count limit */ +#define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */ + +#define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneous control/status register */ +#define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA observation bus mux select */ +#define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA observation bus mux select */ +#define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */ +#define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC observation bus mux select */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC observation bus mux select (lsb) */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC observation bus mux select (msb) */ + + +#define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary interrupt status register */ +/* + * Interrupt Status Registers + * + * Only the bits in the ISR_P register and the IMR_P registers + * control whether the MAC's INTA# output is asserted. The bits in + * the secondary interrupt status/mask registers control what bits + * are set in the primary interrupt status register; however the + * IMR_S* registers DO NOT determine whether INTA# is asserted. + * That is INTA# is asserted only when the logical AND of ISR_P + * and IMR_P is non-zero. The secondary interrupt mask/status + * registers affect what bits are set in ISR_P but they do not + * directly affect whether INTA# is asserted. + */ +#define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */ +#define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt request */ +#define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error interrupt */ +#define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */ +#define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */ +#define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */ +#define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */ +#define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */ +#define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error interrupt */ +#define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */ +#define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */ +#define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */ +#define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */ +#define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrupt */ +#define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */ +#define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */ +#define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high threshold interrupt */ +#define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold interrupt */ +#define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */ +#define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */ +#define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready interrupt */ +#define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */ +#define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */ +#define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */ +#define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */ +#define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */ +#define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */ +#define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt */ +#define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt */ +#define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */ +#define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */ + +#define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary interrupt status register 0 */ +#define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QCU 0-9) */ +#define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0 +#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */ +#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16 + +#define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary interrupt status register 1 */ +#define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (QCU 0-9) */ +#define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0 +#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */ +#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16 + +#define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary interrupt status register 2 */ +#define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */ +#define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-9) */ +#define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800 +#define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000 +#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000 +#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 +#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 +#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000 +#define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000 +#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000 +#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 +#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000 +#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 +#define MAC_DMA_ISR_S2_CST_MASK 0x00400000 +#define MAC_DMA_ISR_S2_GTT_MASK 0x00800000 +#define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */ +#define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */ +#define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ +#define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ +#define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */ +#define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */ +#define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ + +#define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary interrupt status register 3 */ +#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ +#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ + +#define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary interrupt status register 4 */ +#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */ + +#define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary interrupt status register 5 */ +#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 +#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 +#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 +#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 +#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 +#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 +#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 +#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 +#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 +#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 +#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i)) +#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000 +#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 +#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 +#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 +#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 +#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 +#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000 +#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) + +#define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary interrupt mask register */ +/* + * Interrupt Mask Registers + * + * Only the bits in the IMR control whether the MAC's INTA# + * output will be asserted. The bits in the secondary interrupt + * mask registers control what bits get set in the primary + * interrupt status register; however the IMR_S* registers + * DO NOT determine whether INTA# is asserted. + */ +#define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */ +#define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt request */ +#define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error interrupt */ +#define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */ +#define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */ +#define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */ +#define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */ +#define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */ +#define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error interrupt */ +#define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */ +#define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */ +#define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */ +#define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */ +#define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrupt */ +#define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */ +#define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */ +#define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi threshold interrupt */ +#define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo threshold interrupt */ +#define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */ +#define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */ +#define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */ +#define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */ +#define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */ +#define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */ +#define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */ +#define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */ +#define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */ +#define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt */ +#define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/ +#define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */ +#define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */ + +#define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary interrupt mask register 0 */ +#define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */ +#define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0 +#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9) */ +#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16 + +#define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary interrupt mask register 1 */ +#define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) */ +#define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0 +#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) */ +#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16 + +#define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary interrupt mask register 2 */ +#define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */ +#define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0 +#define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800 +#define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000 +#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000 +#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 +#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 +#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000 +#define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000 +#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000 +#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 +#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000 +#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 +#define MAC_DMA_IMR_S2_CST_MASK 0x00400000 +#define MAC_DMA_IMR_S2_GTT_MASK 0x00800000 +#define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */ +#define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */ +#define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ +#define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ +#define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */ +#define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */ +#define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ + +#define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary interrupt mask register 3 */ +#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ +#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ +#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16 + +#define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary interrupt mask register 4 */ +#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */ + +#define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary interrupt mask register 5 */ +#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 +#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 +#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 +#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 +#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 +#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 +#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 +#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i)) +#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000 +#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 +#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 +#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 +#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 +#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 +#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000 +#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) + +#define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-clear access */ + +/* Shadow copies with read-and-clear access */ +#define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow copy */ +#define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow copy */ +#define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow copy */ +#define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow copy */ +#define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow copy */ +#define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow copy */ + +#define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Queue enable */ +#define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Queue disable */ +/* QCU registers */ + +#define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configuration */ +#define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configuration */ +#define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configuration */ +#define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configuration */ +#define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configuration */ +#define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configuration */ +#define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configuration */ +#define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configuration */ +#define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configuration */ +#define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configuration */ +#define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR interval (us) */ +#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval */ +#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR overflow threshold */ +#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow thresh */ + + +#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime configuration */ +#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime configuration */ +#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime configuration */ +#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us) */ +#define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Interval (us) */ +#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */ + +#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm set control */ +#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm clear control */ + +#define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling Policy mask */ +#define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */ +#define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */ +#define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */ +#define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */ +#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */ +#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable */ +#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expired counter incr + (empty q) */ +#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expired counter incr + (empty beacon q) */ +#define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indication */ +#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired counter limit enable */ +#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */ +#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expired counter */ +#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early termination request control */ + +#define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending Frame Count */ +#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expired counter */ + +#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShutdown status */ + +/* DCU registers */ + +#define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */ +#define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */ +#define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */ +#define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */ +#define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */ +#define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */ +#define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */ +#define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */ +#define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */ +#define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */ +#define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */ + +#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS settings */ + + +#define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2)) +#define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN */ +#define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0 +#define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX */ +#define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10 +#define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */ +#define MAC_DMA_D_LCL_IFS_AIFS_LSB 20 +/* + * Note: even though this field is 8 bits wide the + * maximum supported AIFS value is 0xFc. Setting the AIFS value + * to 0xFd 0xFe, or 0xFf will not work correctly and will cause + * the DCU to hang. + */ +#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot interval */ + +#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits */ +#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits */ +#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits */ +#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits */ +#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits */ +#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits */ +#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits */ +#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits */ +#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits */ +#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits */ +#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure limit */ +#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0 +#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failure limit */ +#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8 +#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short retry limit */ +#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14 + +#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS setting */ + +#define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime settings */ +#define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime settings */ +#define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime settings */ +#define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime settings */ +#define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime settings */ +#define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime settings */ +#define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime settings */ +#define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime settings */ +#define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime settings */ +#define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime settings */ +#define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime duration (us) */ +#define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime duration */ +#define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enable */ + +#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc. IFS settings */ +#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */ +#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indication */ +#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */ +#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000 + +#define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D0_EOL_ADDRESS 0x00001180 +#define MAC_DMA_D1_EOL_ADDRESS 0x00001184 +#define MAC_DMA_D2_EOL_ADDRESS 0x00001188 +#define MAC_DMA_D3_EOL_ADDRESS 0x0000118C +#define MAC_DMA_D4_EOL_ADDRESS 0x00001190 +#define MAC_DMA_D5_EOL_ADDRESS 0x00001194 +#define MAC_DMA_D6_EOL_ADDRESS 0x00001198 +#define MAC_DMA_D7_EOL_ADDRESS 0x0000119C +#define MAC_DMA_D8_EOL_ADDRESS 0x00001200 +#define MAC_DMA_D9_EOL_ADDRESS 0x00001204 +#define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold */ +#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0 +#define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmission series + station RTS/data failure + count reset policy */ +#define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmission series + CW reset policy */ +#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvation Policy */ + +#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a frag burst */ +#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable */ +#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persistence factor + setting */ +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual collision + handling policy */ +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14 +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */ +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */ +#define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indication */ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbiter lockout control */ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17 +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockout ignore control */ +#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number increment disable */ +#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff disable */ +#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. handling policy */ +#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling policy */ + +#define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequence number */ + + + +#define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame prefetch settings */ +#define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit pause control/status */ + +#endif /* _AR6000_DMMAEG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h new file mode 100644 index 000000000000..6ccb08c5dab2 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h @@ -0,0 +1,3065 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MAC_PCU_REG_H_ +#define _MAC_PCU_REG_H_ + +#define MAC_PCU_STA_ADDR_L32_ADDRESS 0x00008000 +#define MAC_PCU_STA_ADDR_L32_OFFSET 0x00000000 +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MSB 31 +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB 0 +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK 0xffffffff +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_GET(x) (((x) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) >> MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_SET(x) (((x) << MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) + +#define MAC_PCU_STA_ADDR_U16_ADDRESS 0x00008004 +#define MAC_PCU_STA_ADDR_U16_OFFSET 0x00000004 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MSB 31 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB 31 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK 0x80000000 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MSB 30 +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB 30 +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK 0x40000000 +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) >> MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MSB 29 +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB 29 +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK 0x20000000 +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) >> MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MSB 28 +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB 28 +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK 0x10000000 +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) >> MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MSB 27 +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB 27 +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK 0x08000000 +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) >> MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MSB 26 +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB 26 +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK 0x04000000 +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) >> MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MSB 25 +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB 25 +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK 0x02000000 +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) >> MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MSB 24 +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB 24 +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK 0x01000000 +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) >> MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MSB 23 +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB 23 +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK 0x00800000 +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) >> MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MSB 22 +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB 22 +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK 0x00400000 +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) >> MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MSB 21 +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB 21 +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK 0x00200000 +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) >> MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) +#define MAC_PCU_STA_ADDR_U16_PCF_MSB 20 +#define MAC_PCU_STA_ADDR_U16_PCF_LSB 20 +#define MAC_PCU_STA_ADDR_U16_PCF_MASK 0x00100000 +#define MAC_PCU_STA_ADDR_U16_PCF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PCF_MASK) >> MAC_PCU_STA_ADDR_U16_PCF_LSB) +#define MAC_PCU_STA_ADDR_U16_PCF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PCF_LSB) & MAC_PCU_STA_ADDR_U16_PCF_MASK) +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MSB 19 +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB 19 +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK 0x00080000 +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) >> MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MSB 18 +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB 18 +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK 0x00040000 +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) >> MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) +#define MAC_PCU_STA_ADDR_U16_ADHOC_MSB 17 +#define MAC_PCU_STA_ADDR_U16_ADHOC_LSB 17 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MASK 0x00020000 +#define MAC_PCU_STA_ADDR_U16_ADHOC_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_LSB) +#define MAC_PCU_STA_ADDR_U16_ADHOC_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) +#define MAC_PCU_STA_ADDR_U16_STA_AP_MSB 16 +#define MAC_PCU_STA_ADDR_U16_STA_AP_LSB 16 +#define MAC_PCU_STA_ADDR_U16_STA_AP_MASK 0x00010000 +#define MAC_PCU_STA_ADDR_U16_STA_AP_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) >> MAC_PCU_STA_ADDR_U16_STA_AP_LSB) +#define MAC_PCU_STA_ADDR_U16_STA_AP_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_STA_AP_LSB) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MSB 15 +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB 0 +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK 0x0000ffff +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) >> MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) + +#define MAC_PCU_BSSID_L32_ADDRESS 0x00008008 +#define MAC_PCU_BSSID_L32_OFFSET 0x00000008 +#define MAC_PCU_BSSID_L32_ADDR_MSB 31 +#define MAC_PCU_BSSID_L32_ADDR_LSB 0 +#define MAC_PCU_BSSID_L32_ADDR_MASK 0xffffffff +#define MAC_PCU_BSSID_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID_L32_ADDR_MASK) >> MAC_PCU_BSSID_L32_ADDR_LSB) +#define MAC_PCU_BSSID_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID_L32_ADDR_LSB) & MAC_PCU_BSSID_L32_ADDR_MASK) + +#define MAC_PCU_BSSID_U16_ADDRESS 0x0000800c +#define MAC_PCU_BSSID_U16_OFFSET 0x0000000c +#define MAC_PCU_BSSID_U16_AID_MSB 26 +#define MAC_PCU_BSSID_U16_AID_LSB 16 +#define MAC_PCU_BSSID_U16_AID_MASK 0x07ff0000 +#define MAC_PCU_BSSID_U16_AID_GET(x) (((x) & MAC_PCU_BSSID_U16_AID_MASK) >> MAC_PCU_BSSID_U16_AID_LSB) +#define MAC_PCU_BSSID_U16_AID_SET(x) (((x) << MAC_PCU_BSSID_U16_AID_LSB) & MAC_PCU_BSSID_U16_AID_MASK) +#define MAC_PCU_BSSID_U16_ADDR_MSB 15 +#define MAC_PCU_BSSID_U16_ADDR_LSB 0 +#define MAC_PCU_BSSID_U16_ADDR_MASK 0x0000ffff +#define MAC_PCU_BSSID_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID_U16_ADDR_MASK) >> MAC_PCU_BSSID_U16_ADDR_LSB) +#define MAC_PCU_BSSID_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID_U16_ADDR_LSB) & MAC_PCU_BSSID_U16_ADDR_MASK) + +#define MAC_PCU_BCN_RSSI_AVE_ADDRESS 0x00008010 +#define MAC_PCU_BCN_RSSI_AVE_OFFSET 0x00000010 +#define MAC_PCU_BCN_RSSI_AVE_VALUE_MSB 11 +#define MAC_PCU_BCN_RSSI_AVE_VALUE_LSB 0 +#define MAC_PCU_BCN_RSSI_AVE_VALUE_MASK 0x00000fff +#define MAC_PCU_BCN_RSSI_AVE_VALUE_GET(x) (((x) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) >> MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) +#define MAC_PCU_BCN_RSSI_AVE_VALUE_SET(x) (((x) << MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) + +#define MAC_PCU_ACK_CTS_TIMEOUT_ADDRESS 0x00008014 +#define MAC_PCU_ACK_CTS_TIMEOUT_OFFSET 0x00000014 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MSB 29 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB 16 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK 0x3fff0000 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MSB 13 +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB 0 +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK 0x00003fff +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) + +#define MAC_PCU_BCN_RSSI_CTL_ADDRESS 0x00008018 +#define MAC_PCU_BCN_RSSI_CTL_OFFSET 0x00000018 +#define MAC_PCU_BCN_RSSI_CTL_RESET_MSB 29 +#define MAC_PCU_BCN_RSSI_CTL_RESET_LSB 29 +#define MAC_PCU_BCN_RSSI_CTL_RESET_MASK 0x20000000 +#define MAC_PCU_BCN_RSSI_CTL_RESET_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) >> MAC_PCU_BCN_RSSI_CTL_RESET_LSB) +#define MAC_PCU_BCN_RSSI_CTL_RESET_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RESET_LSB) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MSB 28 +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB 24 +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK 0x1f000000 +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) >> MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MSB 23 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB 16 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK 0x00ff0000 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MSB 15 +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB 8 +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK 0x0000ff00 +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MSB 7 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB 0 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK 0x000000ff +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) + +#define MAC_PCU_USEC_LATENCY_ADDRESS 0x0000801c +#define MAC_PCU_USEC_LATENCY_OFFSET 0x0000001c +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MSB 28 +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB 23 +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK 0x1f800000 +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MSB 22 +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB 14 +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK 0x007fc000 +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) +#define MAC_PCU_USEC_LATENCY_USEC_MSB 7 +#define MAC_PCU_USEC_LATENCY_USEC_LSB 0 +#define MAC_PCU_USEC_LATENCY_USEC_MASK 0x000000ff +#define MAC_PCU_USEC_LATENCY_USEC_GET(x) (((x) & MAC_PCU_USEC_LATENCY_USEC_MASK) >> MAC_PCU_USEC_LATENCY_USEC_LSB) +#define MAC_PCU_USEC_LATENCY_USEC_SET(x) (((x) << MAC_PCU_USEC_LATENCY_USEC_LSB) & MAC_PCU_USEC_LATENCY_USEC_MASK) + +#define PCU_MAX_CFP_DUR_ADDRESS 0x00008020 +#define PCU_MAX_CFP_DUR_OFFSET 0x00000020 +#define PCU_MAX_CFP_DUR_VALUE_MSB 15 +#define PCU_MAX_CFP_DUR_VALUE_LSB 0 +#define PCU_MAX_CFP_DUR_VALUE_MASK 0x0000ffff +#define PCU_MAX_CFP_DUR_VALUE_GET(x) (((x) & PCU_MAX_CFP_DUR_VALUE_MASK) >> PCU_MAX_CFP_DUR_VALUE_LSB) +#define PCU_MAX_CFP_DUR_VALUE_SET(x) (((x) << PCU_MAX_CFP_DUR_VALUE_LSB) & PCU_MAX_CFP_DUR_VALUE_MASK) + +#define MAC_PCU_RX_FILTER_ADDRESS 0x00008024 +#define MAC_PCU_RX_FILTER_OFFSET 0x00000024 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MSB 25 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB 24 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK 0x03000000 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MSB 23 +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB 18 +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK 0x00fc0000 +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) +#define MAC_PCU_RX_FILTER_FROM_TO_DS_MSB 17 +#define MAC_PCU_RX_FILTER_FROM_TO_DS_LSB 17 +#define MAC_PCU_RX_FILTER_FROM_TO_DS_MASK 0x00020000 +#define MAC_PCU_RX_FILTER_FROM_TO_DS_GET(x) (((x) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) >> MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) +#define MAC_PCU_RX_FILTER_FROM_TO_DS_SET(x) (((x) << MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MSB 16 +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB 16 +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK 0x00010000 +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_GET(x) (((x) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) >> MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_SET(x) (((x) << MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MSB 15 +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB 15 +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK 0x00008000 +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_GET(x) (((x) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) >> MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_SET(x) (((x) << MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) +#define MAC_PCU_RX_FILTER_PS_POLL_MSB 14 +#define MAC_PCU_RX_FILTER_PS_POLL_LSB 14 +#define MAC_PCU_RX_FILTER_PS_POLL_MASK 0x00004000 +#define MAC_PCU_RX_FILTER_PS_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_PS_POLL_MASK) >> MAC_PCU_RX_FILTER_PS_POLL_LSB) +#define MAC_PCU_RX_FILTER_PS_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_PS_POLL_LSB) & MAC_PCU_RX_FILTER_PS_POLL_MASK) +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MSB 13 +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB 13 +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK 0x00002000 +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_GET(x) (((x) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) >> MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_SET(x) (((x) << MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MSB 12 +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB 12 +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK 0x00001000 +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) >> MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MSB 11 +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB 11 +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK 0x00000800 +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MSB 10 +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB 10 +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK 0x00000400 +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) +#define MAC_PCU_RX_FILTER_MY_BEACON_MSB 9 +#define MAC_PCU_RX_FILTER_MY_BEACON_LSB 9 +#define MAC_PCU_RX_FILTER_MY_BEACON_MASK 0x00000200 +#define MAC_PCU_RX_FILTER_MY_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) >> MAC_PCU_RX_FILTER_MY_BEACON_LSB) +#define MAC_PCU_RX_FILTER_MY_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_MY_BEACON_LSB) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) +#define MAC_PCU_RX_FILTER_SYNC_FRAME_MSB 8 +#define MAC_PCU_RX_FILTER_SYNC_FRAME_LSB 8 +#define MAC_PCU_RX_FILTER_SYNC_FRAME_MASK 0x00000100 +#define MAC_PCU_RX_FILTER_SYNC_FRAME_GET(x) (((x) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) >> MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) +#define MAC_PCU_RX_FILTER_SYNC_FRAME_SET(x) (((x) << MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) +#define MAC_PCU_RX_FILTER_PROBE_REQ_MSB 7 +#define MAC_PCU_RX_FILTER_PROBE_REQ_LSB 7 +#define MAC_PCU_RX_FILTER_PROBE_REQ_MASK 0x00000080 +#define MAC_PCU_RX_FILTER_PROBE_REQ_GET(x) (((x) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) >> MAC_PCU_RX_FILTER_PROBE_REQ_LSB) +#define MAC_PCU_RX_FILTER_PROBE_REQ_SET(x) (((x) << MAC_PCU_RX_FILTER_PROBE_REQ_LSB) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) +#define MAC_PCU_RX_FILTER_XR_POLL_MSB 6 +#define MAC_PCU_RX_FILTER_XR_POLL_LSB 6 +#define MAC_PCU_RX_FILTER_XR_POLL_MASK 0x00000040 +#define MAC_PCU_RX_FILTER_XR_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_XR_POLL_MASK) >> MAC_PCU_RX_FILTER_XR_POLL_LSB) +#define MAC_PCU_RX_FILTER_XR_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_XR_POLL_LSB) & MAC_PCU_RX_FILTER_XR_POLL_MASK) +#define MAC_PCU_RX_FILTER_PROMISCUOUS_MSB 5 +#define MAC_PCU_RX_FILTER_PROMISCUOUS_LSB 5 +#define MAC_PCU_RX_FILTER_PROMISCUOUS_MASK 0x00000020 +#define MAC_PCU_RX_FILTER_PROMISCUOUS_GET(x) (((x) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) >> MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) +#define MAC_PCU_RX_FILTER_PROMISCUOUS_SET(x) (((x) << MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) +#define MAC_PCU_RX_FILTER_BEACON_MSB 4 +#define MAC_PCU_RX_FILTER_BEACON_LSB 4 +#define MAC_PCU_RX_FILTER_BEACON_MASK 0x00000010 +#define MAC_PCU_RX_FILTER_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_BEACON_MASK) >> MAC_PCU_RX_FILTER_BEACON_LSB) +#define MAC_PCU_RX_FILTER_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_BEACON_LSB) & MAC_PCU_RX_FILTER_BEACON_MASK) +#define MAC_PCU_RX_FILTER_CONTROL_MSB 3 +#define MAC_PCU_RX_FILTER_CONTROL_LSB 3 +#define MAC_PCU_RX_FILTER_CONTROL_MASK 0x00000008 +#define MAC_PCU_RX_FILTER_CONTROL_GET(x) (((x) & MAC_PCU_RX_FILTER_CONTROL_MASK) >> MAC_PCU_RX_FILTER_CONTROL_LSB) +#define MAC_PCU_RX_FILTER_CONTROL_SET(x) (((x) << MAC_PCU_RX_FILTER_CONTROL_LSB) & MAC_PCU_RX_FILTER_CONTROL_MASK) +#define MAC_PCU_RX_FILTER_BROADCAST_MSB 2 +#define MAC_PCU_RX_FILTER_BROADCAST_LSB 2 +#define MAC_PCU_RX_FILTER_BROADCAST_MASK 0x00000004 +#define MAC_PCU_RX_FILTER_BROADCAST_GET(x) (((x) & MAC_PCU_RX_FILTER_BROADCAST_MASK) >> MAC_PCU_RX_FILTER_BROADCAST_LSB) +#define MAC_PCU_RX_FILTER_BROADCAST_SET(x) (((x) << MAC_PCU_RX_FILTER_BROADCAST_LSB) & MAC_PCU_RX_FILTER_BROADCAST_MASK) +#define MAC_PCU_RX_FILTER_MULTICAST_MSB 1 +#define MAC_PCU_RX_FILTER_MULTICAST_LSB 1 +#define MAC_PCU_RX_FILTER_MULTICAST_MASK 0x00000002 +#define MAC_PCU_RX_FILTER_MULTICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_MULTICAST_MASK) >> MAC_PCU_RX_FILTER_MULTICAST_LSB) +#define MAC_PCU_RX_FILTER_MULTICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_MULTICAST_LSB) & MAC_PCU_RX_FILTER_MULTICAST_MASK) +#define MAC_PCU_RX_FILTER_UNICAST_MSB 0 +#define MAC_PCU_RX_FILTER_UNICAST_LSB 0 +#define MAC_PCU_RX_FILTER_UNICAST_MASK 0x00000001 +#define MAC_PCU_RX_FILTER_UNICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_UNICAST_MASK) >> MAC_PCU_RX_FILTER_UNICAST_LSB) +#define MAC_PCU_RX_FILTER_UNICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_UNICAST_LSB) & MAC_PCU_RX_FILTER_UNICAST_MASK) + +#define MAC_PCU_MCAST_FILTER_L32_ADDRESS 0x00008028 +#define MAC_PCU_MCAST_FILTER_L32_OFFSET 0x00000028 +#define MAC_PCU_MCAST_FILTER_L32_VALUE_MSB 31 +#define MAC_PCU_MCAST_FILTER_L32_VALUE_LSB 0 +#define MAC_PCU_MCAST_FILTER_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_MCAST_FILTER_L32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) +#define MAC_PCU_MCAST_FILTER_L32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) + +#define MAC_PCU_MCAST_FILTER_U32_ADDRESS 0x0000802c +#define MAC_PCU_MCAST_FILTER_U32_OFFSET 0x0000002c +#define MAC_PCU_MCAST_FILTER_U32_VALUE_MSB 31 +#define MAC_PCU_MCAST_FILTER_U32_VALUE_LSB 0 +#define MAC_PCU_MCAST_FILTER_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_MCAST_FILTER_U32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) +#define MAC_PCU_MCAST_FILTER_U32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) + +#define MAC_PCU_DIAG_SW_ADDRESS 0x00008030 +#define MAC_PCU_DIAG_SW_OFFSET 0x00000030 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_MSB 31 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_LSB 30 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_MASK 0xc0000000 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_GET(x) (((x) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) >> MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) +#define MAC_PCU_DIAG_SW_DEBUG_MODE_SET(x) (((x) << MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MSB 29 +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB 29 +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK 0x20000000 +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MSB 28 +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB 28 +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK 0x10000000 +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) +#define MAC_PCU_DIAG_SW_OBS_SEL_2_MSB 27 +#define MAC_PCU_DIAG_SW_OBS_SEL_2_LSB 27 +#define MAC_PCU_DIAG_SW_OBS_SEL_2_MASK 0x08000000 +#define MAC_PCU_DIAG_SW_OBS_SEL_2_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) +#define MAC_PCU_DIAG_SW_OBS_SEL_2_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MSB 26 +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB 26 +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK 0x04000000 +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_GET(x) (((x) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) >> MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_SET(x) (((x) << MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MSB 25 +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB 25 +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK 0x02000000 +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_GET(x) (((x) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) >> MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_SET(x) (((x) << MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MSB 24 +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB 24 +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK 0x01000000 +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MSB 23 +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB 23 +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK 0x00800000 +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_GET(x) (((x) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) >> MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_SET(x) (((x) << MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MSB 22 +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB 22 +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK 0x00400000 +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) >> MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) +#define MAC_PCU_DIAG_SW_IGNORE_NAV_MSB 21 +#define MAC_PCU_DIAG_SW_IGNORE_NAV_LSB 21 +#define MAC_PCU_DIAG_SW_IGNORE_NAV_MASK 0x00200000 +#define MAC_PCU_DIAG_SW_IGNORE_NAV_GET(x) (((x) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) >> MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) +#define MAC_PCU_DIAG_SW_IGNORE_NAV_SET(x) (((x) << MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MSB 20 +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB 20 +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK 0x00100000 +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MSB 19 +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB 18 +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK 0x000c0000 +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MSB 17 +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB 17 +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK 0x00020000 +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_GET(x) (((x) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) >> MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_SET(x) (((x) << MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MSB 8 +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB 8 +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK 0x00000100 +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MSB 7 +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB 7 +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK 0x00000080 +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_GET(x) (((x) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) >> MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_SET(x) (((x) << MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) +#define MAC_PCU_DIAG_SW_LOOP_BACK_MSB 6 +#define MAC_PCU_DIAG_SW_LOOP_BACK_LSB 6 +#define MAC_PCU_DIAG_SW_LOOP_BACK_MASK 0x00000040 +#define MAC_PCU_DIAG_SW_LOOP_BACK_GET(x) (((x) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) >> MAC_PCU_DIAG_SW_LOOP_BACK_LSB) +#define MAC_PCU_DIAG_SW_LOOP_BACK_SET(x) (((x) << MAC_PCU_DIAG_SW_LOOP_BACK_LSB) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) +#define MAC_PCU_DIAG_SW_HALT_RX_MSB 5 +#define MAC_PCU_DIAG_SW_HALT_RX_LSB 5 +#define MAC_PCU_DIAG_SW_HALT_RX_MASK 0x00000020 +#define MAC_PCU_DIAG_SW_HALT_RX_GET(x) (((x) & MAC_PCU_DIAG_SW_HALT_RX_MASK) >> MAC_PCU_DIAG_SW_HALT_RX_LSB) +#define MAC_PCU_DIAG_SW_HALT_RX_SET(x) (((x) << MAC_PCU_DIAG_SW_HALT_RX_LSB) & MAC_PCU_DIAG_SW_HALT_RX_MASK) +#define MAC_PCU_DIAG_SW_NO_DECRYPT_MSB 4 +#define MAC_PCU_DIAG_SW_NO_DECRYPT_LSB 4 +#define MAC_PCU_DIAG_SW_NO_DECRYPT_MASK 0x00000010 +#define MAC_PCU_DIAG_SW_NO_DECRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) +#define MAC_PCU_DIAG_SW_NO_DECRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MSB 3 +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB 3 +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK 0x00000008 +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) +#define MAC_PCU_DIAG_SW_NO_CTS_MSB 2 +#define MAC_PCU_DIAG_SW_NO_CTS_LSB 2 +#define MAC_PCU_DIAG_SW_NO_CTS_MASK 0x00000004 +#define MAC_PCU_DIAG_SW_NO_CTS_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_CTS_MASK) >> MAC_PCU_DIAG_SW_NO_CTS_LSB) +#define MAC_PCU_DIAG_SW_NO_CTS_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_CTS_LSB) & MAC_PCU_DIAG_SW_NO_CTS_MASK) +#define MAC_PCU_DIAG_SW_NO_ACK_MSB 1 +#define MAC_PCU_DIAG_SW_NO_ACK_LSB 1 +#define MAC_PCU_DIAG_SW_NO_ACK_MASK 0x00000002 +#define MAC_PCU_DIAG_SW_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_NO_ACK_LSB) +#define MAC_PCU_DIAG_SW_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ACK_LSB) & MAC_PCU_DIAG_SW_NO_ACK_MASK) +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MSB 0 +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB 0 +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK 0x00000001 +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) + +#define MAC_PCU_TST_ADDAC_ADDRESS 0x00008034 +#define MAC_PCU_TST_ADDAC_OFFSET 0x00000034 +#define MAC_PCU_TST_ADDAC_TEST_ARM_MSB 20 +#define MAC_PCU_TST_ADDAC_TEST_ARM_LSB 20 +#define MAC_PCU_TST_ADDAC_TEST_ARM_MASK 0x00100000 +#define MAC_PCU_TST_ADDAC_TEST_ARM_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) >> MAC_PCU_TST_ADDAC_TEST_ARM_LSB) +#define MAC_PCU_TST_ADDAC_TEST_ARM_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_ARM_LSB) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MSB 19 +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB 19 +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK 0x00080000 +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) >> MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) +#define MAC_PCU_TST_ADDAC_CONT_TEST_MSB 18 +#define MAC_PCU_TST_ADDAC_CONT_TEST_LSB 18 +#define MAC_PCU_TST_ADDAC_CONT_TEST_MASK 0x00040000 +#define MAC_PCU_TST_ADDAC_CONT_TEST_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) >> MAC_PCU_TST_ADDAC_CONT_TEST_LSB) +#define MAC_PCU_TST_ADDAC_CONT_TEST_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TEST_LSB) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MSB 17 +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB 17 +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK 0x00020000 +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) >> MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) +#define MAC_PCU_TST_ADDAC_TRIG_SEL_MSB 16 +#define MAC_PCU_TST_ADDAC_TRIG_SEL_LSB 16 +#define MAC_PCU_TST_ADDAC_TRIG_SEL_MASK 0x00010000 +#define MAC_PCU_TST_ADDAC_TRIG_SEL_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) >> MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) +#define MAC_PCU_TST_ADDAC_TRIG_SEL_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) +#define MAC_PCU_TST_ADDAC_UPPER_8B_MSB 14 +#define MAC_PCU_TST_ADDAC_UPPER_8B_LSB 14 +#define MAC_PCU_TST_ADDAC_UPPER_8B_MASK 0x00004000 +#define MAC_PCU_TST_ADDAC_UPPER_8B_GET(x) (((x) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) >> MAC_PCU_TST_ADDAC_UPPER_8B_LSB) +#define MAC_PCU_TST_ADDAC_UPPER_8B_SET(x) (((x) << MAC_PCU_TST_ADDAC_UPPER_8B_LSB) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) +#define MAC_PCU_TST_ADDAC_LOOP_LEN_MSB 13 +#define MAC_PCU_TST_ADDAC_LOOP_LEN_LSB 3 +#define MAC_PCU_TST_ADDAC_LOOP_LEN_MASK 0x00003ff8 +#define MAC_PCU_TST_ADDAC_LOOP_LEN_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) +#define MAC_PCU_TST_ADDAC_LOOP_LEN_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) +#define MAC_PCU_TST_ADDAC_LOOP_MSB 2 +#define MAC_PCU_TST_ADDAC_LOOP_LSB 2 +#define MAC_PCU_TST_ADDAC_LOOP_MASK 0x00000004 +#define MAC_PCU_TST_ADDAC_LOOP_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LSB) +#define MAC_PCU_TST_ADDAC_LOOP_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LSB) & MAC_PCU_TST_ADDAC_LOOP_MASK) +#define MAC_PCU_TST_ADDAC_TESTMODE_MSB 1 +#define MAC_PCU_TST_ADDAC_TESTMODE_LSB 1 +#define MAC_PCU_TST_ADDAC_TESTMODE_MASK 0x00000002 +#define MAC_PCU_TST_ADDAC_TESTMODE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) >> MAC_PCU_TST_ADDAC_TESTMODE_LSB) +#define MAC_PCU_TST_ADDAC_TESTMODE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TESTMODE_LSB) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) +#define MAC_PCU_TST_ADDAC_CONT_TX_MSB 0 +#define MAC_PCU_TST_ADDAC_CONT_TX_LSB 0 +#define MAC_PCU_TST_ADDAC_CONT_TX_MASK 0x00000001 +#define MAC_PCU_TST_ADDAC_CONT_TX_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) >> MAC_PCU_TST_ADDAC_CONT_TX_LSB) +#define MAC_PCU_TST_ADDAC_CONT_TX_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TX_LSB) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) + +#define MAC_PCU_DEF_ANTENNA_ADDRESS 0x00008038 +#define MAC_PCU_DEF_ANTENNA_OFFSET 0x00000038 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MSB 28 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB 28 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK 0x10000000 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MSB 24 +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB 24 +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK 0x01000000 +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) +#define MAC_PCU_DEF_ANTENNA_VALUE_MSB 23 +#define MAC_PCU_DEF_ANTENNA_VALUE_LSB 0 +#define MAC_PCU_DEF_ANTENNA_VALUE_MASK 0x00ffffff +#define MAC_PCU_DEF_ANTENNA_VALUE_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) >> MAC_PCU_DEF_ANTENNA_VALUE_LSB) +#define MAC_PCU_DEF_ANTENNA_VALUE_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_VALUE_LSB) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) + +#define MAC_PCU_AES_MUTE_MASK_0_ADDRESS 0x0000803c +#define MAC_PCU_AES_MUTE_MASK_0_OFFSET 0x0000003c +#define MAC_PCU_AES_MUTE_MASK_0_QOS_MSB 31 +#define MAC_PCU_AES_MUTE_MASK_0_QOS_LSB 16 +#define MAC_PCU_AES_MUTE_MASK_0_QOS_MASK 0xffff0000 +#define MAC_PCU_AES_MUTE_MASK_0_QOS_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) >> MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) +#define MAC_PCU_AES_MUTE_MASK_0_QOS_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) +#define MAC_PCU_AES_MUTE_MASK_0_FC_MSB 15 +#define MAC_PCU_AES_MUTE_MASK_0_FC_LSB 0 +#define MAC_PCU_AES_MUTE_MASK_0_FC_MASK 0x0000ffff +#define MAC_PCU_AES_MUTE_MASK_0_FC_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) >> MAC_PCU_AES_MUTE_MASK_0_FC_LSB) +#define MAC_PCU_AES_MUTE_MASK_0_FC_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_FC_LSB) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) + +#define MAC_PCU_AES_MUTE_MASK_1_ADDRESS 0x00008040 +#define MAC_PCU_AES_MUTE_MASK_1_OFFSET 0x00000040 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MSB 31 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB 16 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK 0xffff0000 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) >> MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MSB 15 +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB 0 +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK 0x0000ffff +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) >> MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) + +#define MAC_PCU_GATED_CLKS_ADDRESS 0x00008044 +#define MAC_PCU_GATED_CLKS_OFFSET 0x00000044 +#define MAC_PCU_GATED_CLKS_GATED_REG_MSB 3 +#define MAC_PCU_GATED_CLKS_GATED_REG_LSB 3 +#define MAC_PCU_GATED_CLKS_GATED_REG_MASK 0x00000008 +#define MAC_PCU_GATED_CLKS_GATED_REG_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) >> MAC_PCU_GATED_CLKS_GATED_REG_LSB) +#define MAC_PCU_GATED_CLKS_GATED_REG_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_REG_LSB) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) +#define MAC_PCU_GATED_CLKS_GATED_RX_MSB 2 +#define MAC_PCU_GATED_CLKS_GATED_RX_LSB 2 +#define MAC_PCU_GATED_CLKS_GATED_RX_MASK 0x00000004 +#define MAC_PCU_GATED_CLKS_GATED_RX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) >> MAC_PCU_GATED_CLKS_GATED_RX_LSB) +#define MAC_PCU_GATED_CLKS_GATED_RX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_RX_LSB) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) +#define MAC_PCU_GATED_CLKS_GATED_TX_MSB 1 +#define MAC_PCU_GATED_CLKS_GATED_TX_LSB 1 +#define MAC_PCU_GATED_CLKS_GATED_TX_MASK 0x00000002 +#define MAC_PCU_GATED_CLKS_GATED_TX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) >> MAC_PCU_GATED_CLKS_GATED_TX_LSB) +#define MAC_PCU_GATED_CLKS_GATED_TX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_TX_LSB) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) + +#define MAC_PCU_OBS_BUS_2_ADDRESS 0x00008048 +#define MAC_PCU_OBS_BUS_2_OFFSET 0x00000048 +#define MAC_PCU_OBS_BUS_2_VALUE_MSB 17 +#define MAC_PCU_OBS_BUS_2_VALUE_LSB 0 +#define MAC_PCU_OBS_BUS_2_VALUE_MASK 0x0003ffff +#define MAC_PCU_OBS_BUS_2_VALUE_GET(x) (((x) & MAC_PCU_OBS_BUS_2_VALUE_MASK) >> MAC_PCU_OBS_BUS_2_VALUE_LSB) +#define MAC_PCU_OBS_BUS_2_VALUE_SET(x) (((x) << MAC_PCU_OBS_BUS_2_VALUE_LSB) & MAC_PCU_OBS_BUS_2_VALUE_MASK) + +#define MAC_PCU_OBS_BUS_1_ADDRESS 0x0000804c +#define MAC_PCU_OBS_BUS_1_OFFSET 0x0000004c +#define MAC_PCU_OBS_BUS_1_TX_STATE_MSB 30 +#define MAC_PCU_OBS_BUS_1_TX_STATE_LSB 25 +#define MAC_PCU_OBS_BUS_1_TX_STATE_MASK 0x7e000000 +#define MAC_PCU_OBS_BUS_1_TX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_TX_STATE_LSB) +#define MAC_PCU_OBS_BUS_1_TX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_STATE_LSB) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) +#define MAC_PCU_OBS_BUS_1_RX_STATE_MSB 24 +#define MAC_PCU_OBS_BUS_1_RX_STATE_LSB 20 +#define MAC_PCU_OBS_BUS_1_RX_STATE_MASK 0x01f00000 +#define MAC_PCU_OBS_BUS_1_RX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_RX_STATE_LSB) +#define MAC_PCU_OBS_BUS_1_RX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_STATE_LSB) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) +#define MAC_PCU_OBS_BUS_1_WEP_STATE_MSB 17 +#define MAC_PCU_OBS_BUS_1_WEP_STATE_LSB 12 +#define MAC_PCU_OBS_BUS_1_WEP_STATE_MASK 0x0003f000 +#define MAC_PCU_OBS_BUS_1_WEP_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) >> MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) +#define MAC_PCU_OBS_BUS_1_WEP_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MSB 11 +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB 11 +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK 0x00000800 +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) >> MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) +#define MAC_PCU_OBS_BUS_1_RX_FRAME_MSB 10 +#define MAC_PCU_OBS_BUS_1_RX_FRAME_LSB 10 +#define MAC_PCU_OBS_BUS_1_RX_FRAME_MASK 0x00000400 +#define MAC_PCU_OBS_BUS_1_RX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) +#define MAC_PCU_OBS_BUS_1_RX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) +#define MAC_PCU_OBS_BUS_1_TX_FRAME_MSB 9 +#define MAC_PCU_OBS_BUS_1_TX_FRAME_LSB 9 +#define MAC_PCU_OBS_BUS_1_TX_FRAME_MASK 0x00000200 +#define MAC_PCU_OBS_BUS_1_TX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) +#define MAC_PCU_OBS_BUS_1_TX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) +#define MAC_PCU_OBS_BUS_1_TX_HOLD_MSB 8 +#define MAC_PCU_OBS_BUS_1_TX_HOLD_LSB 8 +#define MAC_PCU_OBS_BUS_1_TX_HOLD_MASK 0x00000100 +#define MAC_PCU_OBS_BUS_1_TX_HOLD_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) >> MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) +#define MAC_PCU_OBS_BUS_1_TX_HOLD_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MSB 7 +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB 7 +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK 0x00000080 +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) >> MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MSB 6 +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB 6 +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK 0x00000040 +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) >> MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) +#define MAC_PCU_OBS_BUS_1_TX_HCF_MSB 5 +#define MAC_PCU_OBS_BUS_1_TX_HCF_LSB 5 +#define MAC_PCU_OBS_BUS_1_TX_HCF_MASK 0x00000020 +#define MAC_PCU_OBS_BUS_1_TX_HCF_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) >> MAC_PCU_OBS_BUS_1_TX_HCF_LSB) +#define MAC_PCU_OBS_BUS_1_TX_HCF_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HCF_LSB) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MSB 4 +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB 4 +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK 0x00000010 +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_GET(x) (((x) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) >> MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_SET(x) (((x) << MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MSB 3 +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB 3 +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK 0x00000008 +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) >> MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) +#define MAC_PCU_OBS_BUS_1_RX_WEP_MSB 2 +#define MAC_PCU_OBS_BUS_1_RX_WEP_LSB 2 +#define MAC_PCU_OBS_BUS_1_RX_WEP_MASK 0x00000004 +#define MAC_PCU_OBS_BUS_1_RX_WEP_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) >> MAC_PCU_OBS_BUS_1_RX_WEP_LSB) +#define MAC_PCU_OBS_BUS_1_RX_WEP_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_WEP_LSB) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MSB 1 +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB 1 +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK 0x00000002 +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) >> MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MSB 0 +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB 0 +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK 0x00000001 +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) >> MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) + +#define MAC_PCU_DYM_MIMO_PWR_SAVE_ADDRESS 0x00008050 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_OFFSET 0x00000050 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MSB 10 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB 8 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK 0x00000700 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MSB 6 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB 4 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK 0x00000070 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MSB 2 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB 2 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK 0x00000004 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MSB 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK 0x00000002 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MSB 0 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB 0 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK 0x00000001 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) + +#define MAC_PCU_LAST_BEACON_TSF_ADDRESS 0x00008054 +#define MAC_PCU_LAST_BEACON_TSF_OFFSET 0x00000054 +#define MAC_PCU_LAST_BEACON_TSF_VALUE_MSB 31 +#define MAC_PCU_LAST_BEACON_TSF_VALUE_LSB 0 +#define MAC_PCU_LAST_BEACON_TSF_VALUE_MASK 0xffffffff +#define MAC_PCU_LAST_BEACON_TSF_VALUE_GET(x) (((x) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) >> MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) +#define MAC_PCU_LAST_BEACON_TSF_VALUE_SET(x) (((x) << MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) + +#define MAC_PCU_NAV_ADDRESS 0x00008058 +#define MAC_PCU_NAV_OFFSET 0x00000058 +#define MAC_PCU_NAV_VALUE_MSB 25 +#define MAC_PCU_NAV_VALUE_LSB 0 +#define MAC_PCU_NAV_VALUE_MASK 0x03ffffff +#define MAC_PCU_NAV_VALUE_GET(x) (((x) & MAC_PCU_NAV_VALUE_MASK) >> MAC_PCU_NAV_VALUE_LSB) +#define MAC_PCU_NAV_VALUE_SET(x) (((x) << MAC_PCU_NAV_VALUE_LSB) & MAC_PCU_NAV_VALUE_MASK) + +#define MAC_PCU_RTS_SUCCESS_CNT_ADDRESS 0x0000805c +#define MAC_PCU_RTS_SUCCESS_CNT_OFFSET 0x0000005c +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MSB 15 +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB 0 +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) >> MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) + +#define MAC_PCU_RTS_FAIL_CNT_ADDRESS 0x00008060 +#define MAC_PCU_RTS_FAIL_CNT_OFFSET 0x00000060 +#define MAC_PCU_RTS_FAIL_CNT_VALUE_MSB 15 +#define MAC_PCU_RTS_FAIL_CNT_VALUE_LSB 0 +#define MAC_PCU_RTS_FAIL_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_RTS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) +#define MAC_PCU_RTS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) + +#define MAC_PCU_ACK_FAIL_CNT_ADDRESS 0x00008064 +#define MAC_PCU_ACK_FAIL_CNT_OFFSET 0x00000064 +#define MAC_PCU_ACK_FAIL_CNT_VALUE_MSB 15 +#define MAC_PCU_ACK_FAIL_CNT_VALUE_LSB 0 +#define MAC_PCU_ACK_FAIL_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_ACK_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) >> MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) +#define MAC_PCU_ACK_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) + +#define MAC_PCU_FCS_FAIL_CNT_ADDRESS 0x00008068 +#define MAC_PCU_FCS_FAIL_CNT_OFFSET 0x00000068 +#define MAC_PCU_FCS_FAIL_CNT_VALUE_MSB 15 +#define MAC_PCU_FCS_FAIL_CNT_VALUE_LSB 0 +#define MAC_PCU_FCS_FAIL_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_FCS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) +#define MAC_PCU_FCS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) + +#define MAC_PCU_BEACON_CNT_ADDRESS 0x0000806c +#define MAC_PCU_BEACON_CNT_OFFSET 0x0000006c +#define MAC_PCU_BEACON_CNT_VALUE_MSB 15 +#define MAC_PCU_BEACON_CNT_VALUE_LSB 0 +#define MAC_PCU_BEACON_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_BEACON_CNT_VALUE_GET(x) (((x) & MAC_PCU_BEACON_CNT_VALUE_MASK) >> MAC_PCU_BEACON_CNT_VALUE_LSB) +#define MAC_PCU_BEACON_CNT_VALUE_SET(x) (((x) << MAC_PCU_BEACON_CNT_VALUE_LSB) & MAC_PCU_BEACON_CNT_VALUE_MASK) + +#define MAC_PCU_XRMODE_ADDRESS 0x00008070 +#define MAC_PCU_XRMODE_OFFSET 0x00000070 +#define MAC_PCU_XRMODE_FRAME_HOLD_MSB 31 +#define MAC_PCU_XRMODE_FRAME_HOLD_LSB 20 +#define MAC_PCU_XRMODE_FRAME_HOLD_MASK 0xfff00000 +#define MAC_PCU_XRMODE_FRAME_HOLD_GET(x) (((x) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) >> MAC_PCU_XRMODE_FRAME_HOLD_LSB) +#define MAC_PCU_XRMODE_FRAME_HOLD_SET(x) (((x) << MAC_PCU_XRMODE_FRAME_HOLD_LSB) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MSB 7 +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB 7 +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK 0x00000080 +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_GET(x) (((x) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) >> MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_SET(x) (((x) << MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) +#define MAC_PCU_XRMODE_POLL_TYPE_MSB 5 +#define MAC_PCU_XRMODE_POLL_TYPE_LSB 0 +#define MAC_PCU_XRMODE_POLL_TYPE_MASK 0x0000003f +#define MAC_PCU_XRMODE_POLL_TYPE_GET(x) (((x) & MAC_PCU_XRMODE_POLL_TYPE_MASK) >> MAC_PCU_XRMODE_POLL_TYPE_LSB) +#define MAC_PCU_XRMODE_POLL_TYPE_SET(x) (((x) << MAC_PCU_XRMODE_POLL_TYPE_LSB) & MAC_PCU_XRMODE_POLL_TYPE_MASK) + +#define MAC_PCU_XRDEL_ADDRESS 0x00008074 +#define MAC_PCU_XRDEL_OFFSET 0x00000074 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MSB 31 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB 16 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK 0xffff0000 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) >> MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) +#define MAC_PCU_XRDEL_SLOT_DELAY_MSB 15 +#define MAC_PCU_XRDEL_SLOT_DELAY_LSB 0 +#define MAC_PCU_XRDEL_SLOT_DELAY_MASK 0x0000ffff +#define MAC_PCU_XRDEL_SLOT_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) >> MAC_PCU_XRDEL_SLOT_DELAY_LSB) +#define MAC_PCU_XRDEL_SLOT_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_SLOT_DELAY_LSB) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) + +#define MAC_PCU_XRTO_ADDRESS 0x00008078 +#define MAC_PCU_XRTO_OFFSET 0x00000078 +#define MAC_PCU_XRTO_POLL_TIMEOUT_MSB 31 +#define MAC_PCU_XRTO_POLL_TIMEOUT_LSB 16 +#define MAC_PCU_XRTO_POLL_TIMEOUT_MASK 0xffff0000 +#define MAC_PCU_XRTO_POLL_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) >> MAC_PCU_XRTO_POLL_TIMEOUT_LSB) +#define MAC_PCU_XRTO_POLL_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_POLL_TIMEOUT_LSB) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MSB 15 +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB 0 +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) >> MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) + +#define MAC_PCU_XRCRP_ADDRESS 0x0000807c +#define MAC_PCU_XRCRP_OFFSET 0x0000007c +#define MAC_PCU_XRCRP_CHIRP_GAP_MSB 31 +#define MAC_PCU_XRCRP_CHIRP_GAP_LSB 16 +#define MAC_PCU_XRCRP_CHIRP_GAP_MASK 0xffff0000 +#define MAC_PCU_XRCRP_CHIRP_GAP_GET(x) (((x) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) >> MAC_PCU_XRCRP_CHIRP_GAP_LSB) +#define MAC_PCU_XRCRP_CHIRP_GAP_SET(x) (((x) << MAC_PCU_XRCRP_CHIRP_GAP_LSB) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) +#define MAC_PCU_XRCRP_SEND_CHIRP_MSB 0 +#define MAC_PCU_XRCRP_SEND_CHIRP_LSB 0 +#define MAC_PCU_XRCRP_SEND_CHIRP_MASK 0x00000001 +#define MAC_PCU_XRCRP_SEND_CHIRP_GET(x) (((x) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) >> MAC_PCU_XRCRP_SEND_CHIRP_LSB) +#define MAC_PCU_XRCRP_SEND_CHIRP_SET(x) (((x) << MAC_PCU_XRCRP_SEND_CHIRP_LSB) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) + +#define MAC_PCU_XRSTMP_ADDRESS 0x00008080 +#define MAC_PCU_XRSTMP_OFFSET 0x00000080 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MSB 23 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB 16 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK 0x00ff0000 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MSB 15 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB 8 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK 0x0000ff00 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MSB 5 +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB 5 +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK 0x00000020 +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MSB 4 +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB 4 +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK 0x00000010 +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MSB 3 +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB 3 +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK 0x00000008 +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MSB 2 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB 2 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK 0x00000004 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MSB 1 +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB 1 +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK 0x00000002 +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MSB 0 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB 0 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK 0x00000001 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) + +#define MAC_PCU_ADDR1_MASK_L32_ADDRESS 0x00008084 +#define MAC_PCU_ADDR1_MASK_L32_OFFSET 0x00000084 +#define MAC_PCU_ADDR1_MASK_L32_VALUE_MSB 31 +#define MAC_PCU_ADDR1_MASK_L32_VALUE_LSB 0 +#define MAC_PCU_ADDR1_MASK_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_ADDR1_MASK_L32_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) +#define MAC_PCU_ADDR1_MASK_L32_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) + +#define MAC_PCU_ADDR1_MASK_U16_ADDRESS 0x00008088 +#define MAC_PCU_ADDR1_MASK_U16_OFFSET 0x00000088 +#define MAC_PCU_ADDR1_MASK_U16_VALUE_MSB 15 +#define MAC_PCU_ADDR1_MASK_U16_VALUE_LSB 0 +#define MAC_PCU_ADDR1_MASK_U16_VALUE_MASK 0x0000ffff +#define MAC_PCU_ADDR1_MASK_U16_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) +#define MAC_PCU_ADDR1_MASK_U16_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) + +#define MAC_PCU_TPC_ADDRESS 0x0000808c +#define MAC_PCU_TPC_OFFSET 0x0000008c +#define MAC_PCU_TPC_CHIRP_PWR_MSB 21 +#define MAC_PCU_TPC_CHIRP_PWR_LSB 16 +#define MAC_PCU_TPC_CHIRP_PWR_MASK 0x003f0000 +#define MAC_PCU_TPC_CHIRP_PWR_GET(x) (((x) & MAC_PCU_TPC_CHIRP_PWR_MASK) >> MAC_PCU_TPC_CHIRP_PWR_LSB) +#define MAC_PCU_TPC_CHIRP_PWR_SET(x) (((x) << MAC_PCU_TPC_CHIRP_PWR_LSB) & MAC_PCU_TPC_CHIRP_PWR_MASK) +#define MAC_PCU_TPC_CTS_PWR_MSB 13 +#define MAC_PCU_TPC_CTS_PWR_LSB 8 +#define MAC_PCU_TPC_CTS_PWR_MASK 0x00003f00 +#define MAC_PCU_TPC_CTS_PWR_GET(x) (((x) & MAC_PCU_TPC_CTS_PWR_MASK) >> MAC_PCU_TPC_CTS_PWR_LSB) +#define MAC_PCU_TPC_CTS_PWR_SET(x) (((x) << MAC_PCU_TPC_CTS_PWR_LSB) & MAC_PCU_TPC_CTS_PWR_MASK) +#define MAC_PCU_TPC_ACK_PWR_MSB 5 +#define MAC_PCU_TPC_ACK_PWR_LSB 0 +#define MAC_PCU_TPC_ACK_PWR_MASK 0x0000003f +#define MAC_PCU_TPC_ACK_PWR_GET(x) (((x) & MAC_PCU_TPC_ACK_PWR_MASK) >> MAC_PCU_TPC_ACK_PWR_LSB) +#define MAC_PCU_TPC_ACK_PWR_SET(x) (((x) << MAC_PCU_TPC_ACK_PWR_LSB) & MAC_PCU_TPC_ACK_PWR_MASK) + +#define MAC_PCU_TX_FRAME_CNT_ADDRESS 0x00008090 +#define MAC_PCU_TX_FRAME_CNT_OFFSET 0x00000090 +#define MAC_PCU_TX_FRAME_CNT_VALUE_MSB 31 +#define MAC_PCU_TX_FRAME_CNT_VALUE_LSB 0 +#define MAC_PCU_TX_FRAME_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_TX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_TX_FRAME_CNT_VALUE_LSB) +#define MAC_PCU_TX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_TX_FRAME_CNT_VALUE_LSB) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) + +#define MAC_PCU_RX_FRAME_CNT_ADDRESS 0x00008094 +#define MAC_PCU_RX_FRAME_CNT_OFFSET 0x00000094 +#define MAC_PCU_RX_FRAME_CNT_VALUE_MSB 31 +#define MAC_PCU_RX_FRAME_CNT_VALUE_LSB 0 +#define MAC_PCU_RX_FRAME_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_RX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_RX_FRAME_CNT_VALUE_LSB) +#define MAC_PCU_RX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_FRAME_CNT_VALUE_LSB) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) + +#define MAC_PCU_RX_CLEAR_CNT_ADDRESS 0x00008098 +#define MAC_PCU_RX_CLEAR_CNT_OFFSET 0x00000098 +#define MAC_PCU_RX_CLEAR_CNT_VALUE_MSB 31 +#define MAC_PCU_RX_CLEAR_CNT_VALUE_LSB 0 +#define MAC_PCU_RX_CLEAR_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_RX_CLEAR_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) +#define MAC_PCU_RX_CLEAR_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) + +#define MAC_PCU_CYCLE_CNT_ADDRESS 0x0000809c +#define MAC_PCU_CYCLE_CNT_OFFSET 0x0000009c +#define MAC_PCU_CYCLE_CNT_VALUE_MSB 31 +#define MAC_PCU_CYCLE_CNT_VALUE_LSB 0 +#define MAC_PCU_CYCLE_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_CYCLE_CNT_VALUE_GET(x) (((x) & MAC_PCU_CYCLE_CNT_VALUE_MASK) >> MAC_PCU_CYCLE_CNT_VALUE_LSB) +#define MAC_PCU_CYCLE_CNT_VALUE_SET(x) (((x) << MAC_PCU_CYCLE_CNT_VALUE_LSB) & MAC_PCU_CYCLE_CNT_VALUE_MASK) + +#define MAC_PCU_QUIET_TIME_1_ADDRESS 0x000080a0 +#define MAC_PCU_QUIET_TIME_1_OFFSET 0x000000a0 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MSB 17 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB 17 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK 0x00020000 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_GET(x) (((x) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) >> MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_SET(x) (((x) << MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) + +#define MAC_PCU_QUIET_TIME_2_ADDRESS 0x000080a4 +#define MAC_PCU_QUIET_TIME_2_OFFSET 0x000000a4 +#define MAC_PCU_QUIET_TIME_2_DURATION_MSB 31 +#define MAC_PCU_QUIET_TIME_2_DURATION_LSB 16 +#define MAC_PCU_QUIET_TIME_2_DURATION_MASK 0xffff0000 +#define MAC_PCU_QUIET_TIME_2_DURATION_GET(x) (((x) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) >> MAC_PCU_QUIET_TIME_2_DURATION_LSB) +#define MAC_PCU_QUIET_TIME_2_DURATION_SET(x) (((x) << MAC_PCU_QUIET_TIME_2_DURATION_LSB) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) + +#define MAC_PCU_QOS_NO_ACK_ADDRESS 0x000080a8 +#define MAC_PCU_QOS_NO_ACK_OFFSET 0x000000a8 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MSB 8 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB 7 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK 0x00000180 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MSB 6 +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB 4 +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK 0x00000070 +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MSB 3 +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB 0 +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK 0x0000000f +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) >> MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) + +#define MAC_PCU_PHY_ERROR_MASK_ADDRESS 0x000080ac +#define MAC_PCU_PHY_ERROR_MASK_OFFSET 0x000000ac +#define MAC_PCU_PHY_ERROR_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERROR_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERROR_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERROR_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) + +#define MAC_PCU_XRLAT_ADDRESS 0x000080b0 +#define MAC_PCU_XRLAT_OFFSET 0x000000b0 +#define MAC_PCU_XRLAT_VALUE_MSB 11 +#define MAC_PCU_XRLAT_VALUE_LSB 0 +#define MAC_PCU_XRLAT_VALUE_MASK 0x00000fff +#define MAC_PCU_XRLAT_VALUE_GET(x) (((x) & MAC_PCU_XRLAT_VALUE_MASK) >> MAC_PCU_XRLAT_VALUE_LSB) +#define MAC_PCU_XRLAT_VALUE_SET(x) (((x) << MAC_PCU_XRLAT_VALUE_LSB) & MAC_PCU_XRLAT_VALUE_MASK) + +#define MAC_PCU_RXBUF_ADDRESS 0x000080b4 +#define MAC_PCU_RXBUF_OFFSET 0x000000b4 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_MSB 11 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_LSB 11 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_MASK 0x00000800 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_GET(x) (((x) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) >> MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) +#define MAC_PCU_RXBUF_REG_RD_ENABLE_SET(x) (((x) << MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MSB 10 +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB 0 +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK 0x000007ff +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_GET(x) (((x) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) >> MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_SET(x) (((x) << MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) + +#define MAC_PCU_MIC_QOS_CONTROL_ADDRESS 0x000080b8 +#define MAC_PCU_MIC_QOS_CONTROL_OFFSET 0x000000b8 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MSB 16 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB 16 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK 0x00010000 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) >> MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MSB 15 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB 14 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK 0x0000c000 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MSB 13 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB 12 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK 0x00003000 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MSB 11 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB 10 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK 0x00000c00 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MSB 9 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB 8 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK 0x00000300 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MSB 7 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB 6 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK 0x000000c0 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MSB 5 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB 4 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK 0x00000030 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MSB 3 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB 2 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK 0x0000000c +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MSB 1 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB 0 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK 0x00000003 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) + +#define MAC_PCU_MIC_QOS_SELECT_ADDRESS 0x000080bc +#define MAC_PCU_MIC_QOS_SELECT_OFFSET 0x000000bc +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MSB 31 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB 28 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK 0xf0000000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MSB 27 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB 24 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK 0x0f000000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MSB 23 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB 20 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK 0x00f00000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MSB 19 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB 16 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK 0x000f0000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MSB 15 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB 12 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK 0x0000f000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MSB 11 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB 8 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK 0x00000f00 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MSB 7 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB 4 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK 0x000000f0 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MSB 3 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB 0 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK 0x0000000f +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) + +#define MAC_PCU_MISC_MODE_ADDRESS 0x000080c0 +#define MAC_PCU_MISC_MODE_OFFSET 0x000000c0 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_MSB 31 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_LSB 30 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_MASK 0xc0000000 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MSB 29 +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB 29 +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK 0x20000000 +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_GET(x) (((x) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) >> MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_SET(x) (((x) << MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MSB 28 +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB 28 +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK 0x10000000 +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_GET(x) (((x) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) >> MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_SET(x) (((x) << MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) +#define MAC_PCU_MISC_MODE_SEL_EVM_MSB 27 +#define MAC_PCU_MISC_MODE_SEL_EVM_LSB 27 +#define MAC_PCU_MISC_MODE_SEL_EVM_MASK 0x08000000 +#define MAC_PCU_MISC_MODE_SEL_EVM_GET(x) (((x) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) >> MAC_PCU_MISC_MODE_SEL_EVM_LSB) +#define MAC_PCU_MISC_MODE_SEL_EVM_SET(x) (((x) << MAC_PCU_MISC_MODE_SEL_EVM_LSB) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MSB 26 +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB 26 +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK 0x04000000 +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) >> MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MSB 25 +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB 25 +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK 0x02000000 +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) +#define MAC_PCU_MISC_MODE_CLEAR_VMF_MSB 24 +#define MAC_PCU_MISC_MODE_CLEAR_VMF_LSB 24 +#define MAC_PCU_MISC_MODE_CLEAR_VMF_MASK 0x01000000 +#define MAC_PCU_MISC_MODE_CLEAR_VMF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) +#define MAC_PCU_MISC_MODE_CLEAR_VMF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MSB 23 +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB 23 +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK 0x00800000 +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) >> MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MSB 22 +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB 22 +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK 0x00400000 +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_GET(x) (((x) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) >> MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_SET(x) (((x) << MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MSB 21 +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB 21 +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK 0x00200000 +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_GET(x) (((x) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) >> MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_SET(x) (((x) << MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MSB 20 +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB 20 +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK 0x00100000 +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_GET(x) (((x) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) >> MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_SET(x) (((x) << MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MSB 18 +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB 18 +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK 0x00040000 +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_GET(x) (((x) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) >> MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_SET(x) (((x) << MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MSB 14 +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB 14 +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK 0x00004000 +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_GET(x) (((x) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) >> MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_SET(x) (((x) << MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MSB 12 +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB 12 +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK 0x00001000 +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) >> MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MSB 11 +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB 11 +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK 0x00000800 +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_GET(x) (((x) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) >> MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_SET(x) (((x) << MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MSB 10 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB 10 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK 0x00000400 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MSB 9 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB 9 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK 0x00000200 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MSB 4 +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB 4 +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK 0x00000010 +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) >> MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MSB 3 +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB 3 +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK 0x00000008 +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_GET(x) (((x) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) >> MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_SET(x) (((x) << MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MSB 2 +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB 2 +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK 0x00000004 +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) >> MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MSB 1 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB 1 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK 0x00000002 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MSB 0 +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB 0 +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK 0x00000001 +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_GET(x) (((x) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) >> MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_SET(x) (((x) << MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) + +#define MAC_PCU_FILTER_OFDM_CNT_ADDRESS 0x000080c4 +#define MAC_PCU_FILTER_OFDM_CNT_OFFSET 0x000000c4 +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MSB 23 +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB 0 +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK 0x00ffffff +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) >> MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) + +#define MAC_PCU_FILTER_CCK_CNT_ADDRESS 0x000080c8 +#define MAC_PCU_FILTER_CCK_CNT_OFFSET 0x000000c8 +#define MAC_PCU_FILTER_CCK_CNT_VALUE_MSB 23 +#define MAC_PCU_FILTER_CCK_CNT_VALUE_LSB 0 +#define MAC_PCU_FILTER_CCK_CNT_VALUE_MASK 0x00ffffff +#define MAC_PCU_FILTER_CCK_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) >> MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) +#define MAC_PCU_FILTER_CCK_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_1_ADDRESS 0x000080cc +#define MAC_PCU_PHY_ERR_CNT_1_OFFSET 0x000000cc +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK 0x00ffffff +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_1_MASK_ADDRESS 0x000080d0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_OFFSET 0x000000d0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_2_ADDRESS 0x000080d4 +#define MAC_PCU_PHY_ERR_CNT_2_OFFSET 0x000000d4 +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK 0x00ffffff +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_2_MASK_ADDRESS 0x000080d8 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_OFFSET 0x000000d8 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) + +#define MAC_PCU_TSF_THRESHOLD_ADDRESS 0x000080dc +#define MAC_PCU_TSF_THRESHOLD_OFFSET 0x000000dc +#define MAC_PCU_TSF_THRESHOLD_VALUE_MSB 15 +#define MAC_PCU_TSF_THRESHOLD_VALUE_LSB 0 +#define MAC_PCU_TSF_THRESHOLD_VALUE_MASK 0x0000ffff +#define MAC_PCU_TSF_THRESHOLD_VALUE_GET(x) (((x) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) >> MAC_PCU_TSF_THRESHOLD_VALUE_LSB) +#define MAC_PCU_TSF_THRESHOLD_VALUE_SET(x) (((x) << MAC_PCU_TSF_THRESHOLD_VALUE_LSB) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) + +#define MAC_PCU_PHY_ERROR_EIFS_MASK_ADDRESS 0x000080e0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_OFFSET 0x000000e0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_3_ADDRESS 0x000080e4 +#define MAC_PCU_PHY_ERR_CNT_3_OFFSET 0x000000e4 +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK 0x00ffffff +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_3_MASK_ADDRESS 0x000080e8 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_OFFSET 0x000000e8 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_MODE_ADDRESS 0x000080ec +#define MAC_PCU_BLUETOOTH_MODE_OFFSET 0x000000ec +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB 24 +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK 0xff000000 +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MSB 23 +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB 18 +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK 0x00fc0000 +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MSB 17 +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB 17 +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK 0x00020000 +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) >> MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MSB 16 +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB 13 +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK 0x0001e000 +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) +#define MAC_PCU_BLUETOOTH_MODE_QUIET_MSB 12 +#define MAC_PCU_BLUETOOTH_MODE_QUIET_LSB 12 +#define MAC_PCU_BLUETOOTH_MODE_QUIET_MASK 0x00001000 +#define MAC_PCU_BLUETOOTH_MODE_QUIET_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) >> MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) +#define MAC_PCU_BLUETOOTH_MODE_QUIET_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) +#define MAC_PCU_BLUETOOTH_MODE_MODE_MSB 11 +#define MAC_PCU_BLUETOOTH_MODE_MODE_LSB 10 +#define MAC_PCU_BLUETOOTH_MODE_MODE_MASK 0x00000c00 +#define MAC_PCU_BLUETOOTH_MODE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE_MODE_LSB) +#define MAC_PCU_BLUETOOTH_MODE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MSB 9 +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB 9 +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK 0x00000200 +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MSB 8 +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB 8 +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK 0x00000100 +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MSB 7 +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK 0x000000ff +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) + +#define MAC_PCU_BLUETOOTH_WEIGHTS_ADDRESS 0x000080f0 +#define MAC_PCU_BLUETOOTH_WEIGHTS_OFFSET 0x000000f0 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MSB 31 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB 16 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK 0xffff0000 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MSB 15 +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB 0 +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK 0x0000ffff +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) + +#define MAC_PCU_BLUETOOTH_MODE2_ADDRESS 0x000080f4 +#define MAC_PCU_BLUETOOTH_MODE2_OFFSET 0x000000f4 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB 31 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK 0x80000000 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MSB 30 +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB 30 +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK 0x40000000 +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MSB 29 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB 28 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK 0x30000000 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MSB 27 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB 26 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK 0x0c000000 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MSB 25 +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB 25 +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK 0x02000000 +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MSB 24 +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB 24 +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK 0x01000000 +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MSB 23 +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB 22 +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK 0x00c00000 +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MSB 21 +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB 21 +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK 0x00200000 +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MSB 20 +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB 20 +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK 0x00100000 +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MSB 19 +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB 19 +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK 0x00080000 +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MSB 17 +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB 17 +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK 0x00020000 +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MSB 16 +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB 16 +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK 0x00010000 +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) >> MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MSB 15 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB 8 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK 0x0000ff00 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MSB 7 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK 0x000000ff +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) + +#define MAC_PCU_TXSIFS_ADDRESS 0x000080f8 +#define MAC_PCU_TXSIFS_OFFSET 0x000000f8 +#define MAC_PCU_TXSIFS_ACK_SHIFT_MSB 14 +#define MAC_PCU_TXSIFS_ACK_SHIFT_LSB 12 +#define MAC_PCU_TXSIFS_ACK_SHIFT_MASK 0x00007000 +#define MAC_PCU_TXSIFS_ACK_SHIFT_GET(x) (((x) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) >> MAC_PCU_TXSIFS_ACK_SHIFT_LSB) +#define MAC_PCU_TXSIFS_ACK_SHIFT_SET(x) (((x) << MAC_PCU_TXSIFS_ACK_SHIFT_LSB) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) +#define MAC_PCU_TXSIFS_TX_LATENCY_MSB 11 +#define MAC_PCU_TXSIFS_TX_LATENCY_LSB 8 +#define MAC_PCU_TXSIFS_TX_LATENCY_MASK 0x00000f00 +#define MAC_PCU_TXSIFS_TX_LATENCY_GET(x) (((x) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) >> MAC_PCU_TXSIFS_TX_LATENCY_LSB) +#define MAC_PCU_TXSIFS_TX_LATENCY_SET(x) (((x) << MAC_PCU_TXSIFS_TX_LATENCY_LSB) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) +#define MAC_PCU_TXSIFS_SIFS_TIME_MSB 7 +#define MAC_PCU_TXSIFS_SIFS_TIME_LSB 0 +#define MAC_PCU_TXSIFS_SIFS_TIME_MASK 0x000000ff +#define MAC_PCU_TXSIFS_SIFS_TIME_GET(x) (((x) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) >> MAC_PCU_TXSIFS_SIFS_TIME_LSB) +#define MAC_PCU_TXSIFS_SIFS_TIME_SET(x) (((x) << MAC_PCU_TXSIFS_SIFS_TIME_LSB) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) + +#define MAC_PCU_TXOP_X_ADDRESS 0x000080fc +#define MAC_PCU_TXOP_X_OFFSET 0x000000fc +#define MAC_PCU_TXOP_X_VALUE_MSB 7 +#define MAC_PCU_TXOP_X_VALUE_LSB 0 +#define MAC_PCU_TXOP_X_VALUE_MASK 0x000000ff +#define MAC_PCU_TXOP_X_VALUE_GET(x) (((x) & MAC_PCU_TXOP_X_VALUE_MASK) >> MAC_PCU_TXOP_X_VALUE_LSB) +#define MAC_PCU_TXOP_X_VALUE_SET(x) (((x) << MAC_PCU_TXOP_X_VALUE_LSB) & MAC_PCU_TXOP_X_VALUE_MASK) + +#define MAC_PCU_TXOP_0_3_ADDRESS 0x00008100 +#define MAC_PCU_TXOP_0_3_OFFSET 0x00000100 +#define MAC_PCU_TXOP_0_3_VALUE_3_MSB 31 +#define MAC_PCU_TXOP_0_3_VALUE_3_LSB 24 +#define MAC_PCU_TXOP_0_3_VALUE_3_MASK 0xff000000 +#define MAC_PCU_TXOP_0_3_VALUE_3_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) >> MAC_PCU_TXOP_0_3_VALUE_3_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_3_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_3_LSB) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) +#define MAC_PCU_TXOP_0_3_VALUE_2_MSB 23 +#define MAC_PCU_TXOP_0_3_VALUE_2_LSB 16 +#define MAC_PCU_TXOP_0_3_VALUE_2_MASK 0x00ff0000 +#define MAC_PCU_TXOP_0_3_VALUE_2_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) >> MAC_PCU_TXOP_0_3_VALUE_2_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_2_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_2_LSB) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) +#define MAC_PCU_TXOP_0_3_VALUE_1_MSB 15 +#define MAC_PCU_TXOP_0_3_VALUE_1_LSB 8 +#define MAC_PCU_TXOP_0_3_VALUE_1_MASK 0x0000ff00 +#define MAC_PCU_TXOP_0_3_VALUE_1_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) >> MAC_PCU_TXOP_0_3_VALUE_1_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_1_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_1_LSB) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) +#define MAC_PCU_TXOP_0_3_VALUE_0_MSB 7 +#define MAC_PCU_TXOP_0_3_VALUE_0_LSB 0 +#define MAC_PCU_TXOP_0_3_VALUE_0_MASK 0x000000ff +#define MAC_PCU_TXOP_0_3_VALUE_0_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) >> MAC_PCU_TXOP_0_3_VALUE_0_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_0_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_0_LSB) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) + +#define MAC_PCU_TXOP_4_7_ADDRESS 0x00008104 +#define MAC_PCU_TXOP_4_7_OFFSET 0x00000104 +#define MAC_PCU_TXOP_4_7_VALUE_7_MSB 31 +#define MAC_PCU_TXOP_4_7_VALUE_7_LSB 24 +#define MAC_PCU_TXOP_4_7_VALUE_7_MASK 0xff000000 +#define MAC_PCU_TXOP_4_7_VALUE_7_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) >> MAC_PCU_TXOP_4_7_VALUE_7_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_7_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_7_LSB) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) +#define MAC_PCU_TXOP_4_7_VALUE_6_MSB 23 +#define MAC_PCU_TXOP_4_7_VALUE_6_LSB 16 +#define MAC_PCU_TXOP_4_7_VALUE_6_MASK 0x00ff0000 +#define MAC_PCU_TXOP_4_7_VALUE_6_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) >> MAC_PCU_TXOP_4_7_VALUE_6_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_6_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_6_LSB) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) +#define MAC_PCU_TXOP_4_7_VALUE_5_MSB 15 +#define MAC_PCU_TXOP_4_7_VALUE_5_LSB 8 +#define MAC_PCU_TXOP_4_7_VALUE_5_MASK 0x0000ff00 +#define MAC_PCU_TXOP_4_7_VALUE_5_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) >> MAC_PCU_TXOP_4_7_VALUE_5_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_5_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_5_LSB) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) +#define MAC_PCU_TXOP_4_7_VALUE_4_MSB 7 +#define MAC_PCU_TXOP_4_7_VALUE_4_LSB 0 +#define MAC_PCU_TXOP_4_7_VALUE_4_MASK 0x000000ff +#define MAC_PCU_TXOP_4_7_VALUE_4_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) >> MAC_PCU_TXOP_4_7_VALUE_4_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_4_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_4_LSB) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) + +#define MAC_PCU_TXOP_8_11_ADDRESS 0x00008108 +#define MAC_PCU_TXOP_8_11_OFFSET 0x00000108 +#define MAC_PCU_TXOP_8_11_VALUE_11_MSB 31 +#define MAC_PCU_TXOP_8_11_VALUE_11_LSB 24 +#define MAC_PCU_TXOP_8_11_VALUE_11_MASK 0xff000000 +#define MAC_PCU_TXOP_8_11_VALUE_11_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) >> MAC_PCU_TXOP_8_11_VALUE_11_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_11_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_11_LSB) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) +#define MAC_PCU_TXOP_8_11_VALUE_10_MSB 23 +#define MAC_PCU_TXOP_8_11_VALUE_10_LSB 16 +#define MAC_PCU_TXOP_8_11_VALUE_10_MASK 0x00ff0000 +#define MAC_PCU_TXOP_8_11_VALUE_10_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) >> MAC_PCU_TXOP_8_11_VALUE_10_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_10_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_10_LSB) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) +#define MAC_PCU_TXOP_8_11_VALUE_9_MSB 15 +#define MAC_PCU_TXOP_8_11_VALUE_9_LSB 8 +#define MAC_PCU_TXOP_8_11_VALUE_9_MASK 0x0000ff00 +#define MAC_PCU_TXOP_8_11_VALUE_9_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) >> MAC_PCU_TXOP_8_11_VALUE_9_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_9_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_9_LSB) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) +#define MAC_PCU_TXOP_8_11_VALUE_8_MSB 7 +#define MAC_PCU_TXOP_8_11_VALUE_8_LSB 0 +#define MAC_PCU_TXOP_8_11_VALUE_8_MASK 0x000000ff +#define MAC_PCU_TXOP_8_11_VALUE_8_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) >> MAC_PCU_TXOP_8_11_VALUE_8_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_8_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_8_LSB) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) + +#define MAC_PCU_TXOP_12_15_ADDRESS 0x0000810c +#define MAC_PCU_TXOP_12_15_OFFSET 0x0000010c +#define MAC_PCU_TXOP_12_15_VALUE_15_MSB 31 +#define MAC_PCU_TXOP_12_15_VALUE_15_LSB 24 +#define MAC_PCU_TXOP_12_15_VALUE_15_MASK 0xff000000 +#define MAC_PCU_TXOP_12_15_VALUE_15_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) >> MAC_PCU_TXOP_12_15_VALUE_15_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_15_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_15_LSB) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) +#define MAC_PCU_TXOP_12_15_VALUE_14_MSB 23 +#define MAC_PCU_TXOP_12_15_VALUE_14_LSB 16 +#define MAC_PCU_TXOP_12_15_VALUE_14_MASK 0x00ff0000 +#define MAC_PCU_TXOP_12_15_VALUE_14_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) >> MAC_PCU_TXOP_12_15_VALUE_14_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_14_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_14_LSB) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) +#define MAC_PCU_TXOP_12_15_VALUE_13_MSB 15 +#define MAC_PCU_TXOP_12_15_VALUE_13_LSB 8 +#define MAC_PCU_TXOP_12_15_VALUE_13_MASK 0x0000ff00 +#define MAC_PCU_TXOP_12_15_VALUE_13_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) >> MAC_PCU_TXOP_12_15_VALUE_13_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_13_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_13_LSB) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) +#define MAC_PCU_TXOP_12_15_VALUE_12_MSB 7 +#define MAC_PCU_TXOP_12_15_VALUE_12_LSB 0 +#define MAC_PCU_TXOP_12_15_VALUE_12_MASK 0x000000ff +#define MAC_PCU_TXOP_12_15_VALUE_12_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) >> MAC_PCU_TXOP_12_15_VALUE_12_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_12_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_12_LSB) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) + +#define MAC_PCU_LOGIC_ANALYZER_ADDRESS 0x00008110 +#define MAC_PCU_LOGIC_ANALYZER_OFFSET 0x00000110 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MSB 31 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB 18 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK 0xfffc0000 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) >> MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MSB 17 +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB 8 +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK 0x0003ff00 +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) >> MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MSB 7 +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB 4 +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK 0x000000f0 +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) >> MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MSB 3 +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB 3 +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK 0x00000008 +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) >> MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) +#define MAC_PCU_LOGIC_ANALYZER_STATE_MSB 2 +#define MAC_PCU_LOGIC_ANALYZER_STATE_LSB 2 +#define MAC_PCU_LOGIC_ANALYZER_STATE_MASK 0x00000004 +#define MAC_PCU_LOGIC_ANALYZER_STATE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) >> MAC_PCU_LOGIC_ANALYZER_STATE_LSB) +#define MAC_PCU_LOGIC_ANALYZER_STATE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_STATE_LSB) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MSB 1 +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB 1 +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK 0x00000002 +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) >> MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) +#define MAC_PCU_LOGIC_ANALYZER_HOLD_MSB 0 +#define MAC_PCU_LOGIC_ANALYZER_HOLD_LSB 0 +#define MAC_PCU_LOGIC_ANALYZER_HOLD_MASK 0x00000001 +#define MAC_PCU_LOGIC_ANALYZER_HOLD_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) >> MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) +#define MAC_PCU_LOGIC_ANALYZER_HOLD_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) + +#define MAC_PCU_LOGIC_ANALYZER_32L_ADDRESS 0x00008114 +#define MAC_PCU_LOGIC_ANALYZER_32L_OFFSET 0x00000114 +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MSB 31 +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB 0 +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK 0xffffffff +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) + +#define MAC_PCU_LOGIC_ANALYZER_16U_ADDRESS 0x00008118 +#define MAC_PCU_LOGIC_ANALYZER_16U_OFFSET 0x00000118 +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MSB 15 +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB 0 +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK 0x0000ffff +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) + +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_ADDRESS 0x0000811c +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_OFFSET 0x0000011c +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB 16 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK 0x00ff0000 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MSB 15 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK 0x0000ff00 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MSB 7 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK 0x000000ff +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) + +#define MAC_PCU_AZIMUTH_MODE_ADDRESS 0x00008120 +#define MAC_PCU_AZIMUTH_MODE_OFFSET 0x00000120 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MSB 7 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB 7 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK 0x00000080 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MSB 6 +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB 6 +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK 0x00000040 +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) >> MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MSB 5 +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB 5 +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK 0x00000020 +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MSB 4 +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB 4 +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK 0x00000010 +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MSB 3 +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB 3 +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK 0x00000008 +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MSB 2 +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB 2 +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK 0x00000004 +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MSB 1 +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB 1 +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK 0x00000002 +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MSB 0 +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB 0 +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK 0x00000001 +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) >> MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) + +#define MAC_PCU_20_40_MODE_ADDRESS 0x00008124 +#define MAC_PCU_20_40_MODE_OFFSET 0x00000124 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MSB 15 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB 4 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK 0x0000fff0 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_GET(x) (((x) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) >> MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_SET(x) (((x) << MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MSB 3 +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB 3 +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK 0x00000008 +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_GET(x) (((x) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) >> MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_SET(x) (((x) << MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MSB 2 +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB 2 +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK 0x00000004 +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_GET(x) (((x) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) >> MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_SET(x) (((x) << MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MSB 1 +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB 1 +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK 0x00000002 +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_GET(x) (((x) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) >> MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_SET(x) (((x) << MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MSB 0 +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB 0 +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK 0x00000001 +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_GET(x) (((x) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) >> MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_SET(x) (((x) << MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) + +#define MAC_PCU_RX_CLEAR_DIFF_CNT_ADDRESS 0x00008128 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_OFFSET 0x00000128 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MSB 31 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB 0 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) + +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_ADDRESS 0x0000812c +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_OFFSET 0x0000012c +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MSB 2 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB 0 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK 0x00000007 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_GET(x) (((x) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) >> MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_SET(x) (((x) << MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) + +#define MAC_PCU_BA_BAR_CONTROL_ADDRESS 0x00008130 +#define MAC_PCU_BA_BAR_CONTROL_OFFSET 0x00000130 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MSB 12 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB 12 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK 0x00001000 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) >> MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MSB 11 +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB 11 +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK 0x00000800 +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) >> MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MSB 10 +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB 10 +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK 0x00000400 +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) >> MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MSB 9 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB 9 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK 0x00000200 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MSB 8 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB 8 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK 0x00000100 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MSB 7 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB 4 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK 0x000000f0 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MSB 3 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB 0 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK 0x0000000f +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) + +#define MAC_PCU_LEGACY_PLCP_SPOOF_ADDRESS 0x00008134 +#define MAC_PCU_LEGACY_PLCP_SPOOF_OFFSET 0x00000134 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MSB 12 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB 8 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK 0x00001f00 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MSB 7 +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB 0 +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK 0x000000ff +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) + +#define MAC_PCU_PHY_ERROR_MASK_CONT_ADDRESS 0x00008138 +#define MAC_PCU_PHY_ERROR_MASK_CONT_OFFSET 0x00000138 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MSB 23 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB 16 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK 0x00ff0000 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MSB 7 +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK 0x000000ff +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) + +#define MAC_PCU_TX_TIMER_ADDRESS 0x0000813c +#define MAC_PCU_TX_TIMER_OFFSET 0x0000013c +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MSB 25 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB 25 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK 0x02000000 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) +#define MAC_PCU_TX_TIMER_QUIET_TIMER_MSB 24 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_LSB 20 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_MASK 0x01f00000 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) +#define MAC_PCU_TX_TIMER_QUIET_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) +#define MAC_PCU_TX_TIMER_RIFS_TIMER_MSB 19 +#define MAC_PCU_TX_TIMER_RIFS_TIMER_LSB 16 +#define MAC_PCU_TX_TIMER_RIFS_TIMER_MASK 0x000f0000 +#define MAC_PCU_TX_TIMER_RIFS_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) >> MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) +#define MAC_PCU_TX_TIMER_RIFS_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MSB 15 +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB 15 +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK 0x00008000 +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) +#define MAC_PCU_TX_TIMER_TX_TIMER_MSB 14 +#define MAC_PCU_TX_TIMER_TX_TIMER_LSB 0 +#define MAC_PCU_TX_TIMER_TX_TIMER_MASK 0x00007fff +#define MAC_PCU_TX_TIMER_TX_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_LSB) +#define MAC_PCU_TX_TIMER_TX_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) + +#define MAC_PCU_TXBUF_CTRL_ADDRESS 0x00008140 +#define MAC_PCU_TXBUF_CTRL_OFFSET 0x00000140 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MSB 16 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB 16 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK 0x00010000 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) >> MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MSB 11 +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB 0 +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK 0x00000fff +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) >> MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) + +#define MAC_PCU_MISC_MODE2_ADDRESS 0x00008144 +#define MAC_PCU_MISC_MODE2_OFFSET 0x00000144 +#define MAC_PCU_MISC_MODE2_RESERVED_1_MSB 31 +#define MAC_PCU_MISC_MODE2_RESERVED_1_LSB 28 +#define MAC_PCU_MISC_MODE2_RESERVED_1_MASK 0xf0000000 +#define MAC_PCU_MISC_MODE2_RESERVED_1_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_1_LSB) +#define MAC_PCU_MISC_MODE2_RESERVED_1_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_1_LSB) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MSB 27 +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB 27 +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK 0x08000000 +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_GET(x) (((x) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) >> MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_SET(x) (((x) << MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MSB 26 +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB 26 +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK 0x04000000 +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_GET(x) (((x) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) >> MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_SET(x) (((x) << MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MSB 25 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB 25 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK 0x02000000 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MSB 24 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB 24 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK 0x01000000 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MSB 23 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB 23 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK 0x00800000 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MSB 22 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB 22 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK 0x00400000 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MSB 21 +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB 21 +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK 0x00200000 +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_GET(x) (((x) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) >> MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_SET(x) (((x) << MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) +#define MAC_PCU_MISC_MODE2_BUG_28676_MSB 20 +#define MAC_PCU_MISC_MODE2_BUG_28676_LSB 20 +#define MAC_PCU_MISC_MODE2_BUG_28676_MASK 0x00100000 +#define MAC_PCU_MISC_MODE2_BUG_28676_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) >> MAC_PCU_MISC_MODE2_BUG_28676_LSB) +#define MAC_PCU_MISC_MODE2_BUG_28676_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_28676_LSB) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MSB 19 +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB 19 +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK 0x00080000 +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_GET(x) (((x) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) >> MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_SET(x) (((x) << MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MSB 18 +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB 18 +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK 0x00040000 +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) >> MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) +#define MAC_PCU_MISC_MODE2_AGG_WEP_MSB 17 +#define MAC_PCU_MISC_MODE2_AGG_WEP_LSB 17 +#define MAC_PCU_MISC_MODE2_AGG_WEP_MASK 0x00020000 +#define MAC_PCU_MISC_MODE2_AGG_WEP_GET(x) (((x) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) >> MAC_PCU_MISC_MODE2_AGG_WEP_LSB) +#define MAC_PCU_MISC_MODE2_AGG_WEP_SET(x) (((x) << MAC_PCU_MISC_MODE2_AGG_WEP_LSB) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MSB 16 +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB 16 +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK 0x00010000 +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_GET(x) (((x) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) >> MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_SET(x) (((x) << MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) +#define MAC_PCU_MISC_MODE2_MGMT_QOS_MSB 15 +#define MAC_PCU_MISC_MODE2_MGMT_QOS_LSB 8 +#define MAC_PCU_MISC_MODE2_MGMT_QOS_MASK 0x0000ff00 +#define MAC_PCU_MISC_MODE2_MGMT_QOS_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) >> MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) +#define MAC_PCU_MISC_MODE2_MGMT_QOS_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MSB 7 +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB 7 +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK 0x00000080 +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_GET(x) (((x) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) >> MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_SET(x) (((x) << MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MSB 6 +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB 6 +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK 0x00000040 +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) +#define MAC_PCU_MISC_MODE2_RESERVED_2_MSB 5 +#define MAC_PCU_MISC_MODE2_RESERVED_2_LSB 5 +#define MAC_PCU_MISC_MODE2_RESERVED_2_MASK 0x00000020 +#define MAC_PCU_MISC_MODE2_RESERVED_2_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_2_LSB) +#define MAC_PCU_MISC_MODE2_RESERVED_2_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_2_LSB) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MSB 4 +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB 4 +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK 0x00000010 +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) +#define MAC_PCU_MISC_MODE2_RESERVED_0_MSB 3 +#define MAC_PCU_MISC_MODE2_RESERVED_0_LSB 3 +#define MAC_PCU_MISC_MODE2_RESERVED_0_MASK 0x00000008 +#define MAC_PCU_MISC_MODE2_RESERVED_0_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_0_LSB) +#define MAC_PCU_MISC_MODE2_RESERVED_0_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_0_LSB) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MSB 2 +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB 2 +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK 0x00000004 +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) >> MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MSB 1 +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB 1 +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK 0x00000002 +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MSB 0 +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB 0 +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK 0x00000001 +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) + +#define MAC_PCU_ALT_AES_MUTE_MASK_ADDRESS 0x00008148 +#define MAC_PCU_ALT_AES_MUTE_MASK_OFFSET 0x00000148 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MSB 31 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB 16 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK 0xffff0000 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_GET(x) (((x) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) >> MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_SET(x) (((x) << MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) + +#define MAC_PCU_AZIMUTH_TIME_STAMP_ADDRESS 0x0000814c +#define MAC_PCU_AZIMUTH_TIME_STAMP_OFFSET 0x0000014c +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MSB 31 +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB 0 +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK 0xffffffff +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_GET(x) (((x) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) >> MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_SET(x) (((x) << MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) + +#define MAC_PCU_MAX_CFP_DUR_ADDRESS 0x00008150 +#define MAC_PCU_MAX_CFP_DUR_OFFSET 0x00000150 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MSB 7 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB 4 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK 0x000000f0 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MSB 3 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB 0 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK 0x0000000f +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) + +#define MAC_PCU_HCF_TIMEOUT_ADDRESS 0x00008154 +#define MAC_PCU_HCF_TIMEOUT_OFFSET 0x00000154 +#define MAC_PCU_HCF_TIMEOUT_VALUE_MSB 15 +#define MAC_PCU_HCF_TIMEOUT_VALUE_LSB 0 +#define MAC_PCU_HCF_TIMEOUT_VALUE_MASK 0x0000ffff +#define MAC_PCU_HCF_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) >> MAC_PCU_HCF_TIMEOUT_VALUE_LSB) +#define MAC_PCU_HCF_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_HCF_TIMEOUT_VALUE_LSB) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_WEIGHTS2_ADDRESS 0x00008158 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_OFFSET 0x00000158 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MSB 31 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB 16 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK 0xffff0000 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) + +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_ADDRESS 0x0000815c +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_OFFSET 0x0000015c +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MSB 31 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK 0xffffffff +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_ADDRESS 0x00008160 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_OFFSET 0x00000160 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MSB 31 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK 0xffffffff +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_MODE3_ADDRESS 0x00008164 +#define MAC_PCU_BLUETOOTH_MODE3_OFFSET 0x00000164 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB 28 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK 0xf0000000 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MSB 27 +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB 27 +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK 0x08000000 +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MSB 26 +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB 25 +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK 0x06000000 +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MSB 24 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB 24 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK 0x01000000 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MSB 23 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB 23 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK 0x00800000 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MSB 22 +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB 22 +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK 0x00400000 +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) >> MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MSB 21 +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB 21 +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK 0x00200000 +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MSB 20 +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB 20 +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK 0x00100000 +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MSB 19 +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB 16 +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK 0x000f0000 +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MSB 15 +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB 8 +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK 0x0000ff00 +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MSB 7 +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK 0x000000ff +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) + +#define MAC_PCU_BLUETOOTH_MODE4_ADDRESS 0x00008168 +#define MAC_PCU_BLUETOOTH_MODE4_OFFSET 0x00000168 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB 16 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK 0xffff0000 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MSB 15 +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK 0x0000ffff +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) + +#define MAC_PCU_BT_BT_ADDRESS 0x00008200 +#define MAC_PCU_BT_BT_OFFSET 0x00000200 +#define MAC_PCU_BT_BT_WEIGHT_MSB 31 +#define MAC_PCU_BT_BT_WEIGHT_LSB 0 +#define MAC_PCU_BT_BT_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_WEIGHT_MASK) >> MAC_PCU_BT_BT_WEIGHT_LSB) +#define MAC_PCU_BT_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_WEIGHT_LSB) & MAC_PCU_BT_BT_WEIGHT_MASK) + +#define MAC_PCU_BT_BT_ASYNC_ADDRESS 0x00008300 +#define MAC_PCU_BT_BT_ASYNC_OFFSET 0x00000300 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MSB 15 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB 12 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK 0x0000f000 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MSB 11 +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB 8 +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK 0x00000f00 +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MSB 7 +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB 4 +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK 0x000000f0 +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MSB 3 +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB 0 +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK 0x0000000f +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_1_ADDRESS 0x00008304 +#define MAC_PCU_BT_WL_1_OFFSET 0x00000304 +#define MAC_PCU_BT_WL_1_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_1_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_1_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_1_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_1_WEIGHT_MASK) >> MAC_PCU_BT_WL_1_WEIGHT_LSB) +#define MAC_PCU_BT_WL_1_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_1_WEIGHT_LSB) & MAC_PCU_BT_WL_1_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_2_ADDRESS 0x00008308 +#define MAC_PCU_BT_WL_2_OFFSET 0x00000308 +#define MAC_PCU_BT_WL_2_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_2_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_2_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_2_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_2_WEIGHT_MASK) >> MAC_PCU_BT_WL_2_WEIGHT_LSB) +#define MAC_PCU_BT_WL_2_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_2_WEIGHT_LSB) & MAC_PCU_BT_WL_2_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_3_ADDRESS 0x0000830c +#define MAC_PCU_BT_WL_3_OFFSET 0x0000030c +#define MAC_PCU_BT_WL_3_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_3_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_3_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_3_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_3_WEIGHT_MASK) >> MAC_PCU_BT_WL_3_WEIGHT_LSB) +#define MAC_PCU_BT_WL_3_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_3_WEIGHT_LSB) & MAC_PCU_BT_WL_3_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_4_ADDRESS 0x00008310 +#define MAC_PCU_BT_WL_4_OFFSET 0x00000310 +#define MAC_PCU_BT_WL_4_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_4_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_4_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_4_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_4_WEIGHT_MASK) >> MAC_PCU_BT_WL_4_WEIGHT_LSB) +#define MAC_PCU_BT_WL_4_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_4_WEIGHT_LSB) & MAC_PCU_BT_WL_4_WEIGHT_MASK) + +#define MAC_PCU_COEX_EPTA_ADDRESS 0x00008314 +#define MAC_PCU_COEX_EPTA_OFFSET 0x00000314 +#define MAC_PCU_COEX_EPTA_WT_IDX_MSB 12 +#define MAC_PCU_COEX_EPTA_WT_IDX_LSB 6 +#define MAC_PCU_COEX_EPTA_WT_IDX_MASK 0x00001fc0 +#define MAC_PCU_COEX_EPTA_WT_IDX_GET(x) (((x) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) >> MAC_PCU_COEX_EPTA_WT_IDX_LSB) +#define MAC_PCU_COEX_EPTA_WT_IDX_SET(x) (((x) << MAC_PCU_COEX_EPTA_WT_IDX_LSB) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) +#define MAC_PCU_COEX_EPTA_LINKID_MSB 5 +#define MAC_PCU_COEX_EPTA_LINKID_LSB 0 +#define MAC_PCU_COEX_EPTA_LINKID_MASK 0x0000003f +#define MAC_PCU_COEX_EPTA_LINKID_GET(x) (((x) & MAC_PCU_COEX_EPTA_LINKID_MASK) >> MAC_PCU_COEX_EPTA_LINKID_LSB) +#define MAC_PCU_COEX_EPTA_LINKID_SET(x) (((x) << MAC_PCU_COEX_EPTA_LINKID_LSB) & MAC_PCU_COEX_EPTA_LINKID_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN1_ADDRESS 0x00008318 +#define MAC_PCU_COEX_LNAMAXGAIN1_OFFSET 0x00000318 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN2_ADDRESS 0x0000831c +#define MAC_PCU_COEX_LNAMAXGAIN2_OFFSET 0x0000031c +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN3_ADDRESS 0x00008320 +#define MAC_PCU_COEX_LNAMAXGAIN3_OFFSET 0x00000320 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN4_ADDRESS 0x00008324 +#define MAC_PCU_COEX_LNAMAXGAIN4_OFFSET 0x00000324 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) + +#define MAC_PCU_BASIC_RATE_SET0_ADDRESS 0x00008328 +#define MAC_PCU_BASIC_RATE_SET0_OFFSET 0x00000328 +#define MAC_PCU_BASIC_RATE_SET0_VALUE_MSB 29 +#define MAC_PCU_BASIC_RATE_SET0_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET0_VALUE_MASK 0x3fffffff +#define MAC_PCU_BASIC_RATE_SET0_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET0_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) + +#define MAC_PCU_BASIC_RATE_SET1_ADDRESS 0x0000832c +#define MAC_PCU_BASIC_RATE_SET1_OFFSET 0x0000032c +#define MAC_PCU_BASIC_RATE_SET1_VALUE_MSB 29 +#define MAC_PCU_BASIC_RATE_SET1_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET1_VALUE_MASK 0x3fffffff +#define MAC_PCU_BASIC_RATE_SET1_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET1_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) + +#define MAC_PCU_BASIC_RATE_SET2_ADDRESS 0x00008330 +#define MAC_PCU_BASIC_RATE_SET2_OFFSET 0x00000330 +#define MAC_PCU_BASIC_RATE_SET2_VALUE_MSB 29 +#define MAC_PCU_BASIC_RATE_SET2_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET2_VALUE_MASK 0x3fffffff +#define MAC_PCU_BASIC_RATE_SET2_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET2_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) + +#define MAC_PCU_BASIC_RATE_SET3_ADDRESS 0x00008334 +#define MAC_PCU_BASIC_RATE_SET3_OFFSET 0x00000334 +#define MAC_PCU_BASIC_RATE_SET3_VALUE_MSB 24 +#define MAC_PCU_BASIC_RATE_SET3_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET3_VALUE_MASK 0x01ffffff +#define MAC_PCU_BASIC_RATE_SET3_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET3_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) + +#define MAC_PCU_RX_INT_STATUS0_ADDRESS 0x00008338 +#define MAC_PCU_RX_INT_STATUS0_OFFSET 0x00000338 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MSB 31 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB 24 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK 0xff000000 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MSB 23 +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB 16 +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK 0x00ff0000 +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MSB 15 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB 8 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK 0x0000ff00 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MSB 7 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB 0 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK 0x000000ff +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) + +#define MAC_PCU_RX_INT_STATUS1_ADDRESS 0x0000833c +#define MAC_PCU_RX_INT_STATUS1_OFFSET 0x0000033c +#define MAC_PCU_RX_INT_STATUS1_VALUE_MSB 17 +#define MAC_PCU_RX_INT_STATUS1_VALUE_LSB 0 +#define MAC_PCU_RX_INT_STATUS1_VALUE_MASK 0x0003ffff +#define MAC_PCU_RX_INT_STATUS1_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS1_VALUE_LSB) +#define MAC_PCU_RX_INT_STATUS1_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS1_VALUE_LSB) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) + +#define MAC_PCU_RX_INT_STATUS2_ADDRESS 0x00008340 +#define MAC_PCU_RX_INT_STATUS2_OFFSET 0x00000340 +#define MAC_PCU_RX_INT_STATUS2_VALUE_MSB 26 +#define MAC_PCU_RX_INT_STATUS2_VALUE_LSB 0 +#define MAC_PCU_RX_INT_STATUS2_VALUE_MASK 0x07ffffff +#define MAC_PCU_RX_INT_STATUS2_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS2_VALUE_LSB) +#define MAC_PCU_RX_INT_STATUS2_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS2_VALUE_LSB) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) + +#define MAC_PCU_RX_INT_STATUS3_ADDRESS 0x00008344 +#define MAC_PCU_RX_INT_STATUS3_OFFSET 0x00000344 +#define MAC_PCU_RX_INT_STATUS3_VALUE_MSB 23 +#define MAC_PCU_RX_INT_STATUS3_VALUE_LSB 0 +#define MAC_PCU_RX_INT_STATUS3_VALUE_MASK 0x00ffffff +#define MAC_PCU_RX_INT_STATUS3_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS3_VALUE_LSB) +#define MAC_PCU_RX_INT_STATUS3_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS3_VALUE_LSB) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) + +#define HT_HALF_GI_RATE1_ADDRESS 0x00008348 +#define HT_HALF_GI_RATE1_OFFSET 0x00000348 +#define HT_HALF_GI_RATE1_MCS3_MSB 31 +#define HT_HALF_GI_RATE1_MCS3_LSB 24 +#define HT_HALF_GI_RATE1_MCS3_MASK 0xff000000 +#define HT_HALF_GI_RATE1_MCS3_GET(x) (((x) & HT_HALF_GI_RATE1_MCS3_MASK) >> HT_HALF_GI_RATE1_MCS3_LSB) +#define HT_HALF_GI_RATE1_MCS3_SET(x) (((x) << HT_HALF_GI_RATE1_MCS3_LSB) & HT_HALF_GI_RATE1_MCS3_MASK) +#define HT_HALF_GI_RATE1_MCS2_MSB 23 +#define HT_HALF_GI_RATE1_MCS2_LSB 16 +#define HT_HALF_GI_RATE1_MCS2_MASK 0x00ff0000 +#define HT_HALF_GI_RATE1_MCS2_GET(x) (((x) & HT_HALF_GI_RATE1_MCS2_MASK) >> HT_HALF_GI_RATE1_MCS2_LSB) +#define HT_HALF_GI_RATE1_MCS2_SET(x) (((x) << HT_HALF_GI_RATE1_MCS2_LSB) & HT_HALF_GI_RATE1_MCS2_MASK) +#define HT_HALF_GI_RATE1_MCS1_MSB 15 +#define HT_HALF_GI_RATE1_MCS1_LSB 8 +#define HT_HALF_GI_RATE1_MCS1_MASK 0x0000ff00 +#define HT_HALF_GI_RATE1_MCS1_GET(x) (((x) & HT_HALF_GI_RATE1_MCS1_MASK) >> HT_HALF_GI_RATE1_MCS1_LSB) +#define HT_HALF_GI_RATE1_MCS1_SET(x) (((x) << HT_HALF_GI_RATE1_MCS1_LSB) & HT_HALF_GI_RATE1_MCS1_MASK) +#define HT_HALF_GI_RATE1_MCS0_MSB 7 +#define HT_HALF_GI_RATE1_MCS0_LSB 0 +#define HT_HALF_GI_RATE1_MCS0_MASK 0x000000ff +#define HT_HALF_GI_RATE1_MCS0_GET(x) (((x) & HT_HALF_GI_RATE1_MCS0_MASK) >> HT_HALF_GI_RATE1_MCS0_LSB) +#define HT_HALF_GI_RATE1_MCS0_SET(x) (((x) << HT_HALF_GI_RATE1_MCS0_LSB) & HT_HALF_GI_RATE1_MCS0_MASK) + +#define HT_HALF_GI_RATE2_ADDRESS 0x0000834c +#define HT_HALF_GI_RATE2_OFFSET 0x0000034c +#define HT_HALF_GI_RATE2_MCS7_MSB 31 +#define HT_HALF_GI_RATE2_MCS7_LSB 24 +#define HT_HALF_GI_RATE2_MCS7_MASK 0xff000000 +#define HT_HALF_GI_RATE2_MCS7_GET(x) (((x) & HT_HALF_GI_RATE2_MCS7_MASK) >> HT_HALF_GI_RATE2_MCS7_LSB) +#define HT_HALF_GI_RATE2_MCS7_SET(x) (((x) << HT_HALF_GI_RATE2_MCS7_LSB) & HT_HALF_GI_RATE2_MCS7_MASK) +#define HT_HALF_GI_RATE2_MCS6_MSB 23 +#define HT_HALF_GI_RATE2_MCS6_LSB 16 +#define HT_HALF_GI_RATE2_MCS6_MASK 0x00ff0000 +#define HT_HALF_GI_RATE2_MCS6_GET(x) (((x) & HT_HALF_GI_RATE2_MCS6_MASK) >> HT_HALF_GI_RATE2_MCS6_LSB) +#define HT_HALF_GI_RATE2_MCS6_SET(x) (((x) << HT_HALF_GI_RATE2_MCS6_LSB) & HT_HALF_GI_RATE2_MCS6_MASK) +#define HT_HALF_GI_RATE2_MCS5_MSB 15 +#define HT_HALF_GI_RATE2_MCS5_LSB 8 +#define HT_HALF_GI_RATE2_MCS5_MASK 0x0000ff00 +#define HT_HALF_GI_RATE2_MCS5_GET(x) (((x) & HT_HALF_GI_RATE2_MCS5_MASK) >> HT_HALF_GI_RATE2_MCS5_LSB) +#define HT_HALF_GI_RATE2_MCS5_SET(x) (((x) << HT_HALF_GI_RATE2_MCS5_LSB) & HT_HALF_GI_RATE2_MCS5_MASK) +#define HT_HALF_GI_RATE2_MCS4_MSB 7 +#define HT_HALF_GI_RATE2_MCS4_LSB 0 +#define HT_HALF_GI_RATE2_MCS4_MASK 0x000000ff +#define HT_HALF_GI_RATE2_MCS4_GET(x) (((x) & HT_HALF_GI_RATE2_MCS4_MASK) >> HT_HALF_GI_RATE2_MCS4_LSB) +#define HT_HALF_GI_RATE2_MCS4_SET(x) (((x) << HT_HALF_GI_RATE2_MCS4_LSB) & HT_HALF_GI_RATE2_MCS4_MASK) + +#define HT_FULL_GI_RATE1_ADDRESS 0x00008350 +#define HT_FULL_GI_RATE1_OFFSET 0x00000350 +#define HT_FULL_GI_RATE1_MCS3_MSB 31 +#define HT_FULL_GI_RATE1_MCS3_LSB 24 +#define HT_FULL_GI_RATE1_MCS3_MASK 0xff000000 +#define HT_FULL_GI_RATE1_MCS3_GET(x) (((x) & HT_FULL_GI_RATE1_MCS3_MASK) >> HT_FULL_GI_RATE1_MCS3_LSB) +#define HT_FULL_GI_RATE1_MCS3_SET(x) (((x) << HT_FULL_GI_RATE1_MCS3_LSB) & HT_FULL_GI_RATE1_MCS3_MASK) +#define HT_FULL_GI_RATE1_MCS2_MSB 23 +#define HT_FULL_GI_RATE1_MCS2_LSB 16 +#define HT_FULL_GI_RATE1_MCS2_MASK 0x00ff0000 +#define HT_FULL_GI_RATE1_MCS2_GET(x) (((x) & HT_FULL_GI_RATE1_MCS2_MASK) >> HT_FULL_GI_RATE1_MCS2_LSB) +#define HT_FULL_GI_RATE1_MCS2_SET(x) (((x) << HT_FULL_GI_RATE1_MCS2_LSB) & HT_FULL_GI_RATE1_MCS2_MASK) +#define HT_FULL_GI_RATE1_MCS1_MSB 15 +#define HT_FULL_GI_RATE1_MCS1_LSB 8 +#define HT_FULL_GI_RATE1_MCS1_MASK 0x0000ff00 +#define HT_FULL_GI_RATE1_MCS1_GET(x) (((x) & HT_FULL_GI_RATE1_MCS1_MASK) >> HT_FULL_GI_RATE1_MCS1_LSB) +#define HT_FULL_GI_RATE1_MCS1_SET(x) (((x) << HT_FULL_GI_RATE1_MCS1_LSB) & HT_FULL_GI_RATE1_MCS1_MASK) +#define HT_FULL_GI_RATE1_MCS0_MSB 7 +#define HT_FULL_GI_RATE1_MCS0_LSB 0 +#define HT_FULL_GI_RATE1_MCS0_MASK 0x000000ff +#define HT_FULL_GI_RATE1_MCS0_GET(x) (((x) & HT_FULL_GI_RATE1_MCS0_MASK) >> HT_FULL_GI_RATE1_MCS0_LSB) +#define HT_FULL_GI_RATE1_MCS0_SET(x) (((x) << HT_FULL_GI_RATE1_MCS0_LSB) & HT_FULL_GI_RATE1_MCS0_MASK) + +#define HT_FULL_GI_RATE2_ADDRESS 0x00008354 +#define HT_FULL_GI_RATE2_OFFSET 0x00000354 +#define HT_FULL_GI_RATE2_MCS7_MSB 31 +#define HT_FULL_GI_RATE2_MCS7_LSB 24 +#define HT_FULL_GI_RATE2_MCS7_MASK 0xff000000 +#define HT_FULL_GI_RATE2_MCS7_GET(x) (((x) & HT_FULL_GI_RATE2_MCS7_MASK) >> HT_FULL_GI_RATE2_MCS7_LSB) +#define HT_FULL_GI_RATE2_MCS7_SET(x) (((x) << HT_FULL_GI_RATE2_MCS7_LSB) & HT_FULL_GI_RATE2_MCS7_MASK) +#define HT_FULL_GI_RATE2_MCS6_MSB 23 +#define HT_FULL_GI_RATE2_MCS6_LSB 16 +#define HT_FULL_GI_RATE2_MCS6_MASK 0x00ff0000 +#define HT_FULL_GI_RATE2_MCS6_GET(x) (((x) & HT_FULL_GI_RATE2_MCS6_MASK) >> HT_FULL_GI_RATE2_MCS6_LSB) +#define HT_FULL_GI_RATE2_MCS6_SET(x) (((x) << HT_FULL_GI_RATE2_MCS6_LSB) & HT_FULL_GI_RATE2_MCS6_MASK) +#define HT_FULL_GI_RATE2_MCS5_MSB 15 +#define HT_FULL_GI_RATE2_MCS5_LSB 8 +#define HT_FULL_GI_RATE2_MCS5_MASK 0x0000ff00 +#define HT_FULL_GI_RATE2_MCS5_GET(x) (((x) & HT_FULL_GI_RATE2_MCS5_MASK) >> HT_FULL_GI_RATE2_MCS5_LSB) +#define HT_FULL_GI_RATE2_MCS5_SET(x) (((x) << HT_FULL_GI_RATE2_MCS5_LSB) & HT_FULL_GI_RATE2_MCS5_MASK) +#define HT_FULL_GI_RATE2_MCS4_MSB 7 +#define HT_FULL_GI_RATE2_MCS4_LSB 0 +#define HT_FULL_GI_RATE2_MCS4_MASK 0x000000ff +#define HT_FULL_GI_RATE2_MCS4_GET(x) (((x) & HT_FULL_GI_RATE2_MCS4_MASK) >> HT_FULL_GI_RATE2_MCS4_LSB) +#define HT_FULL_GI_RATE2_MCS4_SET(x) (((x) << HT_FULL_GI_RATE2_MCS4_LSB) & HT_FULL_GI_RATE2_MCS4_MASK) + +#define LEGACY_RATE1_ADDRESS 0x00008358 +#define LEGACY_RATE1_OFFSET 0x00000358 +#define LEGACY_RATE1_RATE12_MSB 29 +#define LEGACY_RATE1_RATE12_LSB 24 +#define LEGACY_RATE1_RATE12_MASK 0x3f000000 +#define LEGACY_RATE1_RATE12_GET(x) (((x) & LEGACY_RATE1_RATE12_MASK) >> LEGACY_RATE1_RATE12_LSB) +#define LEGACY_RATE1_RATE12_SET(x) (((x) << LEGACY_RATE1_RATE12_LSB) & LEGACY_RATE1_RATE12_MASK) +#define LEGACY_RATE1_RATE11_MSB 23 +#define LEGACY_RATE1_RATE11_LSB 18 +#define LEGACY_RATE1_RATE11_MASK 0x00fc0000 +#define LEGACY_RATE1_RATE11_GET(x) (((x) & LEGACY_RATE1_RATE11_MASK) >> LEGACY_RATE1_RATE11_LSB) +#define LEGACY_RATE1_RATE11_SET(x) (((x) << LEGACY_RATE1_RATE11_LSB) & LEGACY_RATE1_RATE11_MASK) +#define LEGACY_RATE1_RATE10_MSB 17 +#define LEGACY_RATE1_RATE10_LSB 12 +#define LEGACY_RATE1_RATE10_MASK 0x0003f000 +#define LEGACY_RATE1_RATE10_GET(x) (((x) & LEGACY_RATE1_RATE10_MASK) >> LEGACY_RATE1_RATE10_LSB) +#define LEGACY_RATE1_RATE10_SET(x) (((x) << LEGACY_RATE1_RATE10_LSB) & LEGACY_RATE1_RATE10_MASK) +#define LEGACY_RATE1_RATE9_MSB 11 +#define LEGACY_RATE1_RATE9_LSB 6 +#define LEGACY_RATE1_RATE9_MASK 0x00000fc0 +#define LEGACY_RATE1_RATE9_GET(x) (((x) & LEGACY_RATE1_RATE9_MASK) >> LEGACY_RATE1_RATE9_LSB) +#define LEGACY_RATE1_RATE9_SET(x) (((x) << LEGACY_RATE1_RATE9_LSB) & LEGACY_RATE1_RATE9_MASK) +#define LEGACY_RATE1_RATE8_MSB 5 +#define LEGACY_RATE1_RATE8_LSB 0 +#define LEGACY_RATE1_RATE8_MASK 0x0000003f +#define LEGACY_RATE1_RATE8_GET(x) (((x) & LEGACY_RATE1_RATE8_MASK) >> LEGACY_RATE1_RATE8_LSB) +#define LEGACY_RATE1_RATE8_SET(x) (((x) << LEGACY_RATE1_RATE8_LSB) & LEGACY_RATE1_RATE8_MASK) + +#define LEGACY_RATE2_ADDRESS 0x0000835c +#define LEGACY_RATE2_OFFSET 0x0000035c +#define LEGACY_RATE2_RATE25_MSB 29 +#define LEGACY_RATE2_RATE25_LSB 24 +#define LEGACY_RATE2_RATE25_MASK 0x3f000000 +#define LEGACY_RATE2_RATE25_GET(x) (((x) & LEGACY_RATE2_RATE25_MASK) >> LEGACY_RATE2_RATE25_LSB) +#define LEGACY_RATE2_RATE25_SET(x) (((x) << LEGACY_RATE2_RATE25_LSB) & LEGACY_RATE2_RATE25_MASK) +#define LEGACY_RATE2_RATE24_MSB 23 +#define LEGACY_RATE2_RATE24_LSB 18 +#define LEGACY_RATE2_RATE24_MASK 0x00fc0000 +#define LEGACY_RATE2_RATE24_GET(x) (((x) & LEGACY_RATE2_RATE24_MASK) >> LEGACY_RATE2_RATE24_LSB) +#define LEGACY_RATE2_RATE24_SET(x) (((x) << LEGACY_RATE2_RATE24_LSB) & LEGACY_RATE2_RATE24_MASK) +#define LEGACY_RATE2_RATE15_MSB 17 +#define LEGACY_RATE2_RATE15_LSB 12 +#define LEGACY_RATE2_RATE15_MASK 0x0003f000 +#define LEGACY_RATE2_RATE15_GET(x) (((x) & LEGACY_RATE2_RATE15_MASK) >> LEGACY_RATE2_RATE15_LSB) +#define LEGACY_RATE2_RATE15_SET(x) (((x) << LEGACY_RATE2_RATE15_LSB) & LEGACY_RATE2_RATE15_MASK) +#define LEGACY_RATE2_RATE14_MSB 11 +#define LEGACY_RATE2_RATE14_LSB 6 +#define LEGACY_RATE2_RATE14_MASK 0x00000fc0 +#define LEGACY_RATE2_RATE14_GET(x) (((x) & LEGACY_RATE2_RATE14_MASK) >> LEGACY_RATE2_RATE14_LSB) +#define LEGACY_RATE2_RATE14_SET(x) (((x) << LEGACY_RATE2_RATE14_LSB) & LEGACY_RATE2_RATE14_MASK) +#define LEGACY_RATE2_RATE13_MSB 5 +#define LEGACY_RATE2_RATE13_LSB 0 +#define LEGACY_RATE2_RATE13_MASK 0x0000003f +#define LEGACY_RATE2_RATE13_GET(x) (((x) & LEGACY_RATE2_RATE13_MASK) >> LEGACY_RATE2_RATE13_LSB) +#define LEGACY_RATE2_RATE13_SET(x) (((x) << LEGACY_RATE2_RATE13_LSB) & LEGACY_RATE2_RATE13_MASK) + +#define LEGACY_RATE3_ADDRESS 0x00008360 +#define LEGACY_RATE3_OFFSET 0x00000360 +#define LEGACY_RATE3_RATE30_MSB 29 +#define LEGACY_RATE3_RATE30_LSB 24 +#define LEGACY_RATE3_RATE30_MASK 0x3f000000 +#define LEGACY_RATE3_RATE30_GET(x) (((x) & LEGACY_RATE3_RATE30_MASK) >> LEGACY_RATE3_RATE30_LSB) +#define LEGACY_RATE3_RATE30_SET(x) (((x) << LEGACY_RATE3_RATE30_LSB) & LEGACY_RATE3_RATE30_MASK) +#define LEGACY_RATE3_RATE29_MSB 23 +#define LEGACY_RATE3_RATE29_LSB 18 +#define LEGACY_RATE3_RATE29_MASK 0x00fc0000 +#define LEGACY_RATE3_RATE29_GET(x) (((x) & LEGACY_RATE3_RATE29_MASK) >> LEGACY_RATE3_RATE29_LSB) +#define LEGACY_RATE3_RATE29_SET(x) (((x) << LEGACY_RATE3_RATE29_LSB) & LEGACY_RATE3_RATE29_MASK) +#define LEGACY_RATE3_RATE28_MSB 17 +#define LEGACY_RATE3_RATE28_LSB 12 +#define LEGACY_RATE3_RATE28_MASK 0x0003f000 +#define LEGACY_RATE3_RATE28_GET(x) (((x) & LEGACY_RATE3_RATE28_MASK) >> LEGACY_RATE3_RATE28_LSB) +#define LEGACY_RATE3_RATE28_SET(x) (((x) << LEGACY_RATE3_RATE28_LSB) & LEGACY_RATE3_RATE28_MASK) +#define LEGACY_RATE3_RATE27_MSB 11 +#define LEGACY_RATE3_RATE27_LSB 6 +#define LEGACY_RATE3_RATE27_MASK 0x00000fc0 +#define LEGACY_RATE3_RATE27_GET(x) (((x) & LEGACY_RATE3_RATE27_MASK) >> LEGACY_RATE3_RATE27_LSB) +#define LEGACY_RATE3_RATE27_SET(x) (((x) << LEGACY_RATE3_RATE27_LSB) & LEGACY_RATE3_RATE27_MASK) +#define LEGACY_RATE3_RATE26_MSB 5 +#define LEGACY_RATE3_RATE26_LSB 0 +#define LEGACY_RATE3_RATE26_MASK 0x0000003f +#define LEGACY_RATE3_RATE26_GET(x) (((x) & LEGACY_RATE3_RATE26_MASK) >> LEGACY_RATE3_RATE26_LSB) +#define LEGACY_RATE3_RATE26_SET(x) (((x) << LEGACY_RATE3_RATE26_LSB) & LEGACY_RATE3_RATE26_MASK) + +#define RX_INT_FILTER_ADDRESS 0x00008364 +#define RX_INT_FILTER_OFFSET 0x00000364 +#define RX_INT_FILTER_BEACON_MSB 17 +#define RX_INT_FILTER_BEACON_LSB 17 +#define RX_INT_FILTER_BEACON_MASK 0x00020000 +#define RX_INT_FILTER_BEACON_GET(x) (((x) & RX_INT_FILTER_BEACON_MASK) >> RX_INT_FILTER_BEACON_LSB) +#define RX_INT_FILTER_BEACON_SET(x) (((x) << RX_INT_FILTER_BEACON_LSB) & RX_INT_FILTER_BEACON_MASK) +#define RX_INT_FILTER_AMPDU_MSB 16 +#define RX_INT_FILTER_AMPDU_LSB 16 +#define RX_INT_FILTER_AMPDU_MASK 0x00010000 +#define RX_INT_FILTER_AMPDU_GET(x) (((x) & RX_INT_FILTER_AMPDU_MASK) >> RX_INT_FILTER_AMPDU_LSB) +#define RX_INT_FILTER_AMPDU_SET(x) (((x) << RX_INT_FILTER_AMPDU_LSB) & RX_INT_FILTER_AMPDU_MASK) +#define RX_INT_FILTER_EOSP_MSB 15 +#define RX_INT_FILTER_EOSP_LSB 15 +#define RX_INT_FILTER_EOSP_MASK 0x00008000 +#define RX_INT_FILTER_EOSP_GET(x) (((x) & RX_INT_FILTER_EOSP_MASK) >> RX_INT_FILTER_EOSP_LSB) +#define RX_INT_FILTER_EOSP_SET(x) (((x) << RX_INT_FILTER_EOSP_LSB) & RX_INT_FILTER_EOSP_MASK) +#define RX_INT_FILTER_LENGTH_LOW_MSB 14 +#define RX_INT_FILTER_LENGTH_LOW_LSB 14 +#define RX_INT_FILTER_LENGTH_LOW_MASK 0x00004000 +#define RX_INT_FILTER_LENGTH_LOW_GET(x) (((x) & RX_INT_FILTER_LENGTH_LOW_MASK) >> RX_INT_FILTER_LENGTH_LOW_LSB) +#define RX_INT_FILTER_LENGTH_LOW_SET(x) (((x) << RX_INT_FILTER_LENGTH_LOW_LSB) & RX_INT_FILTER_LENGTH_LOW_MASK) +#define RX_INT_FILTER_LENGTH_HIGH_MSB 13 +#define RX_INT_FILTER_LENGTH_HIGH_LSB 13 +#define RX_INT_FILTER_LENGTH_HIGH_MASK 0x00002000 +#define RX_INT_FILTER_LENGTH_HIGH_GET(x) (((x) & RX_INT_FILTER_LENGTH_HIGH_MASK) >> RX_INT_FILTER_LENGTH_HIGH_LSB) +#define RX_INT_FILTER_LENGTH_HIGH_SET(x) (((x) << RX_INT_FILTER_LENGTH_HIGH_LSB) & RX_INT_FILTER_LENGTH_HIGH_MASK) +#define RX_INT_FILTER_RSSI_MSB 12 +#define RX_INT_FILTER_RSSI_LSB 12 +#define RX_INT_FILTER_RSSI_MASK 0x00001000 +#define RX_INT_FILTER_RSSI_GET(x) (((x) & RX_INT_FILTER_RSSI_MASK) >> RX_INT_FILTER_RSSI_LSB) +#define RX_INT_FILTER_RSSI_SET(x) (((x) << RX_INT_FILTER_RSSI_LSB) & RX_INT_FILTER_RSSI_MASK) +#define RX_INT_FILTER_RATE_LOW_MSB 11 +#define RX_INT_FILTER_RATE_LOW_LSB 11 +#define RX_INT_FILTER_RATE_LOW_MASK 0x00000800 +#define RX_INT_FILTER_RATE_LOW_GET(x) (((x) & RX_INT_FILTER_RATE_LOW_MASK) >> RX_INT_FILTER_RATE_LOW_LSB) +#define RX_INT_FILTER_RATE_LOW_SET(x) (((x) << RX_INT_FILTER_RATE_LOW_LSB) & RX_INT_FILTER_RATE_LOW_MASK) +#define RX_INT_FILTER_RATE_HIGH_MSB 10 +#define RX_INT_FILTER_RATE_HIGH_LSB 10 +#define RX_INT_FILTER_RATE_HIGH_MASK 0x00000400 +#define RX_INT_FILTER_RATE_HIGH_GET(x) (((x) & RX_INT_FILTER_RATE_HIGH_MASK) >> RX_INT_FILTER_RATE_HIGH_LSB) +#define RX_INT_FILTER_RATE_HIGH_SET(x) (((x) << RX_INT_FILTER_RATE_HIGH_LSB) & RX_INT_FILTER_RATE_HIGH_MASK) +#define RX_INT_FILTER_MORE_FRAG_MSB 9 +#define RX_INT_FILTER_MORE_FRAG_LSB 9 +#define RX_INT_FILTER_MORE_FRAG_MASK 0x00000200 +#define RX_INT_FILTER_MORE_FRAG_GET(x) (((x) & RX_INT_FILTER_MORE_FRAG_MASK) >> RX_INT_FILTER_MORE_FRAG_LSB) +#define RX_INT_FILTER_MORE_FRAG_SET(x) (((x) << RX_INT_FILTER_MORE_FRAG_LSB) & RX_INT_FILTER_MORE_FRAG_MASK) +#define RX_INT_FILTER_MORE_DATA_MSB 8 +#define RX_INT_FILTER_MORE_DATA_LSB 8 +#define RX_INT_FILTER_MORE_DATA_MASK 0x00000100 +#define RX_INT_FILTER_MORE_DATA_GET(x) (((x) & RX_INT_FILTER_MORE_DATA_MASK) >> RX_INT_FILTER_MORE_DATA_LSB) +#define RX_INT_FILTER_MORE_DATA_SET(x) (((x) << RX_INT_FILTER_MORE_DATA_LSB) & RX_INT_FILTER_MORE_DATA_MASK) +#define RX_INT_FILTER_RETRY_MSB 7 +#define RX_INT_FILTER_RETRY_LSB 7 +#define RX_INT_FILTER_RETRY_MASK 0x00000080 +#define RX_INT_FILTER_RETRY_GET(x) (((x) & RX_INT_FILTER_RETRY_MASK) >> RX_INT_FILTER_RETRY_LSB) +#define RX_INT_FILTER_RETRY_SET(x) (((x) << RX_INT_FILTER_RETRY_LSB) & RX_INT_FILTER_RETRY_MASK) +#define RX_INT_FILTER_CTS_MSB 6 +#define RX_INT_FILTER_CTS_LSB 6 +#define RX_INT_FILTER_CTS_MASK 0x00000040 +#define RX_INT_FILTER_CTS_GET(x) (((x) & RX_INT_FILTER_CTS_MASK) >> RX_INT_FILTER_CTS_LSB) +#define RX_INT_FILTER_CTS_SET(x) (((x) << RX_INT_FILTER_CTS_LSB) & RX_INT_FILTER_CTS_MASK) +#define RX_INT_FILTER_ACK_MSB 5 +#define RX_INT_FILTER_ACK_LSB 5 +#define RX_INT_FILTER_ACK_MASK 0x00000020 +#define RX_INT_FILTER_ACK_GET(x) (((x) & RX_INT_FILTER_ACK_MASK) >> RX_INT_FILTER_ACK_LSB) +#define RX_INT_FILTER_ACK_SET(x) (((x) << RX_INT_FILTER_ACK_LSB) & RX_INT_FILTER_ACK_MASK) +#define RX_INT_FILTER_RTS_MSB 4 +#define RX_INT_FILTER_RTS_LSB 4 +#define RX_INT_FILTER_RTS_MASK 0x00000010 +#define RX_INT_FILTER_RTS_GET(x) (((x) & RX_INT_FILTER_RTS_MASK) >> RX_INT_FILTER_RTS_LSB) +#define RX_INT_FILTER_RTS_SET(x) (((x) << RX_INT_FILTER_RTS_LSB) & RX_INT_FILTER_RTS_MASK) +#define RX_INT_FILTER_MCAST_MSB 3 +#define RX_INT_FILTER_MCAST_LSB 3 +#define RX_INT_FILTER_MCAST_MASK 0x00000008 +#define RX_INT_FILTER_MCAST_GET(x) (((x) & RX_INT_FILTER_MCAST_MASK) >> RX_INT_FILTER_MCAST_LSB) +#define RX_INT_FILTER_MCAST_SET(x) (((x) << RX_INT_FILTER_MCAST_LSB) & RX_INT_FILTER_MCAST_MASK) +#define RX_INT_FILTER_BCAST_MSB 2 +#define RX_INT_FILTER_BCAST_LSB 2 +#define RX_INT_FILTER_BCAST_MASK 0x00000004 +#define RX_INT_FILTER_BCAST_GET(x) (((x) & RX_INT_FILTER_BCAST_MASK) >> RX_INT_FILTER_BCAST_LSB) +#define RX_INT_FILTER_BCAST_SET(x) (((x) << RX_INT_FILTER_BCAST_LSB) & RX_INT_FILTER_BCAST_MASK) +#define RX_INT_FILTER_DIRECTED_MSB 1 +#define RX_INT_FILTER_DIRECTED_LSB 1 +#define RX_INT_FILTER_DIRECTED_MASK 0x00000002 +#define RX_INT_FILTER_DIRECTED_GET(x) (((x) & RX_INT_FILTER_DIRECTED_MASK) >> RX_INT_FILTER_DIRECTED_LSB) +#define RX_INT_FILTER_DIRECTED_SET(x) (((x) << RX_INT_FILTER_DIRECTED_LSB) & RX_INT_FILTER_DIRECTED_MASK) +#define RX_INT_FILTER_ENABLE_MSB 0 +#define RX_INT_FILTER_ENABLE_LSB 0 +#define RX_INT_FILTER_ENABLE_MASK 0x00000001 +#define RX_INT_FILTER_ENABLE_GET(x) (((x) & RX_INT_FILTER_ENABLE_MASK) >> RX_INT_FILTER_ENABLE_LSB) +#define RX_INT_FILTER_ENABLE_SET(x) (((x) << RX_INT_FILTER_ENABLE_LSB) & RX_INT_FILTER_ENABLE_MASK) + +#define RX_INT_OVERFLOW_ADDRESS 0x00008368 +#define RX_INT_OVERFLOW_OFFSET 0x00000368 +#define RX_INT_OVERFLOW_STATUS_MSB 0 +#define RX_INT_OVERFLOW_STATUS_LSB 0 +#define RX_INT_OVERFLOW_STATUS_MASK 0x00000001 +#define RX_INT_OVERFLOW_STATUS_GET(x) (((x) & RX_INT_OVERFLOW_STATUS_MASK) >> RX_INT_OVERFLOW_STATUS_LSB) +#define RX_INT_OVERFLOW_STATUS_SET(x) (((x) << RX_INT_OVERFLOW_STATUS_LSB) & RX_INT_OVERFLOW_STATUS_MASK) + +#define RX_FILTER_THRESH_ADDRESS 0x0000836c +#define RX_FILTER_THRESH_OFFSET 0x0000036c +#define RX_FILTER_THRESH_RSSI_LOW_MSB 23 +#define RX_FILTER_THRESH_RSSI_LOW_LSB 16 +#define RX_FILTER_THRESH_RSSI_LOW_MASK 0x00ff0000 +#define RX_FILTER_THRESH_RSSI_LOW_GET(x) (((x) & RX_FILTER_THRESH_RSSI_LOW_MASK) >> RX_FILTER_THRESH_RSSI_LOW_LSB) +#define RX_FILTER_THRESH_RSSI_LOW_SET(x) (((x) << RX_FILTER_THRESH_RSSI_LOW_LSB) & RX_FILTER_THRESH_RSSI_LOW_MASK) +#define RX_FILTER_THRESH_RATE_LOW_MSB 15 +#define RX_FILTER_THRESH_RATE_LOW_LSB 8 +#define RX_FILTER_THRESH_RATE_LOW_MASK 0x0000ff00 +#define RX_FILTER_THRESH_RATE_LOW_GET(x) (((x) & RX_FILTER_THRESH_RATE_LOW_MASK) >> RX_FILTER_THRESH_RATE_LOW_LSB) +#define RX_FILTER_THRESH_RATE_LOW_SET(x) (((x) << RX_FILTER_THRESH_RATE_LOW_LSB) & RX_FILTER_THRESH_RATE_LOW_MASK) +#define RX_FILTER_THRESH_RATE_HIGH_MSB 7 +#define RX_FILTER_THRESH_RATE_HIGH_LSB 0 +#define RX_FILTER_THRESH_RATE_HIGH_MASK 0x000000ff +#define RX_FILTER_THRESH_RATE_HIGH_GET(x) (((x) & RX_FILTER_THRESH_RATE_HIGH_MASK) >> RX_FILTER_THRESH_RATE_HIGH_LSB) +#define RX_FILTER_THRESH_RATE_HIGH_SET(x) (((x) << RX_FILTER_THRESH_RATE_HIGH_LSB) & RX_FILTER_THRESH_RATE_HIGH_MASK) + +#define RX_FILTER_THRESH1_ADDRESS 0x00008370 +#define RX_FILTER_THRESH1_OFFSET 0x00000370 +#define RX_FILTER_THRESH1_LENGTH_LOW_MSB 23 +#define RX_FILTER_THRESH1_LENGTH_LOW_LSB 12 +#define RX_FILTER_THRESH1_LENGTH_LOW_MASK 0x00fff000 +#define RX_FILTER_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) >> RX_FILTER_THRESH1_LENGTH_LOW_LSB) +#define RX_FILTER_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_LOW_LSB) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) +#define RX_FILTER_THRESH1_LENGTH_HIGH_MSB 11 +#define RX_FILTER_THRESH1_LENGTH_HIGH_LSB 0 +#define RX_FILTER_THRESH1_LENGTH_HIGH_MASK 0x00000fff +#define RX_FILTER_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) >> RX_FILTER_THRESH1_LENGTH_HIGH_LSB) +#define RX_FILTER_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_HIGH_LSB) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) + +#define RX_PRIORITY_THRESH0_ADDRESS 0x00008374 +#define RX_PRIORITY_THRESH0_OFFSET 0x00000374 +#define RX_PRIORITY_THRESH0_RSSI_LOW_MSB 31 +#define RX_PRIORITY_THRESH0_RSSI_LOW_LSB 24 +#define RX_PRIORITY_THRESH0_RSSI_LOW_MASK 0xff000000 +#define RX_PRIORITY_THRESH0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) >> RX_PRIORITY_THRESH0_RSSI_LOW_LSB) +#define RX_PRIORITY_THRESH0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_LOW_LSB) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) +#define RX_PRIORITY_THRESH0_RSSI_HIGH_MSB 23 +#define RX_PRIORITY_THRESH0_RSSI_HIGH_LSB 16 +#define RX_PRIORITY_THRESH0_RSSI_HIGH_MASK 0x00ff0000 +#define RX_PRIORITY_THRESH0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH0_RATE_LOW_MSB 15 +#define RX_PRIORITY_THRESH0_RATE_LOW_LSB 8 +#define RX_PRIORITY_THRESH0_RATE_LOW_MASK 0x0000ff00 +#define RX_PRIORITY_THRESH0_RATE_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) >> RX_PRIORITY_THRESH0_RATE_LOW_LSB) +#define RX_PRIORITY_THRESH0_RATE_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_LOW_LSB) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) +#define RX_PRIORITY_THRESH0_RATE_HIGH_MSB 7 +#define RX_PRIORITY_THRESH0_RATE_HIGH_LSB 0 +#define RX_PRIORITY_THRESH0_RATE_HIGH_MASK 0x000000ff +#define RX_PRIORITY_THRESH0_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) >> RX_PRIORITY_THRESH0_RATE_HIGH_LSB) +#define RX_PRIORITY_THRESH0_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_HIGH_LSB) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) + +#define RX_PRIORITY_THRESH1_ADDRESS 0x00008378 +#define RX_PRIORITY_THRESH1_OFFSET 0x00000378 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MSB 31 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK 0xff000000 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH1_LENGTH_LOW_MSB 23 +#define RX_PRIORITY_THRESH1_LENGTH_LOW_LSB 12 +#define RX_PRIORITY_THRESH1_LENGTH_LOW_MASK 0x00fff000 +#define RX_PRIORITY_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) >> RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) +#define RX_PRIORITY_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MSB 11 +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB 0 +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK 0x00000fff +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) >> RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) + +#define RX_PRIORITY_THRESH2_ADDRESS 0x0000837c +#define RX_PRIORITY_THRESH2_OFFSET 0x0000037c +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MSB 31 +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK 0xff000000 +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MSB 23 +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB 16 +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK 0x00ff0000 +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MSB 15 +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB 8 +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK 0x0000ff00 +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MSB 7 +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB 0 +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK 0x000000ff +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) + +#define RX_PRIORITY_THRESH3_ADDRESS 0x00008380 +#define RX_PRIORITY_THRESH3_OFFSET 0x00000380 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MSB 15 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB 8 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK 0x0000ff00 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MSB 7 +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB 0 +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK 0x000000ff +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) + +#define RX_PRIORITY_OFFSET0_ADDRESS 0x00008384 +#define RX_PRIORITY_OFFSET0_OFFSET 0x00000384 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MSB 29 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET0_RSSI_LOW_MSB 23 +#define RX_PRIORITY_OFFSET0_RSSI_LOW_LSB 18 +#define RX_PRIORITY_OFFSET0_RSSI_LOW_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) >> RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) +#define RX_PRIORITY_OFFSET0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MSB 17 +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB 12 +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MSB 11 +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB 6 +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MSB 5 +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB 0 +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK 0x0000003f +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) + +#define RX_PRIORITY_OFFSET1_ADDRESS 0x00008388 +#define RX_PRIORITY_OFFSET1_OFFSET 0x00000388 +#define RX_PRIORITY_OFFSET1_RTS_MSB 29 +#define RX_PRIORITY_OFFSET1_RTS_LSB 24 +#define RX_PRIORITY_OFFSET1_RTS_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET1_RTS_GET(x) (((x) & RX_PRIORITY_OFFSET1_RTS_MASK) >> RX_PRIORITY_OFFSET1_RTS_LSB) +#define RX_PRIORITY_OFFSET1_RTS_SET(x) (((x) << RX_PRIORITY_OFFSET1_RTS_LSB) & RX_PRIORITY_OFFSET1_RTS_MASK) +#define RX_PRIORITY_OFFSET1_RETX_MSB 23 +#define RX_PRIORITY_OFFSET1_RETX_LSB 18 +#define RX_PRIORITY_OFFSET1_RETX_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET1_RETX_GET(x) (((x) & RX_PRIORITY_OFFSET1_RETX_MASK) >> RX_PRIORITY_OFFSET1_RETX_LSB) +#define RX_PRIORITY_OFFSET1_RETX_SET(x) (((x) << RX_PRIORITY_OFFSET1_RETX_LSB) & RX_PRIORITY_OFFSET1_RETX_MASK) +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MSB 17 +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB 12 +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MSB 11 +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB 6 +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MSB 5 +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB 0 +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK 0x0000003f +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) + +#define RX_PRIORITY_OFFSET2_ADDRESS 0x0000838c +#define RX_PRIORITY_OFFSET2_OFFSET 0x0000038c +#define RX_PRIORITY_OFFSET2_BEACON_MSB 29 +#define RX_PRIORITY_OFFSET2_BEACON_LSB 24 +#define RX_PRIORITY_OFFSET2_BEACON_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET2_BEACON_GET(x) (((x) & RX_PRIORITY_OFFSET2_BEACON_MASK) >> RX_PRIORITY_OFFSET2_BEACON_LSB) +#define RX_PRIORITY_OFFSET2_BEACON_SET(x) (((x) << RX_PRIORITY_OFFSET2_BEACON_LSB) & RX_PRIORITY_OFFSET2_BEACON_MASK) +#define RX_PRIORITY_OFFSET2_MGMT_MSB 23 +#define RX_PRIORITY_OFFSET2_MGMT_LSB 18 +#define RX_PRIORITY_OFFSET2_MGMT_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET2_MGMT_GET(x) (((x) & RX_PRIORITY_OFFSET2_MGMT_MASK) >> RX_PRIORITY_OFFSET2_MGMT_LSB) +#define RX_PRIORITY_OFFSET2_MGMT_SET(x) (((x) << RX_PRIORITY_OFFSET2_MGMT_LSB) & RX_PRIORITY_OFFSET2_MGMT_MASK) +#define RX_PRIORITY_OFFSET2_ATIM_MSB 17 +#define RX_PRIORITY_OFFSET2_ATIM_LSB 12 +#define RX_PRIORITY_OFFSET2_ATIM_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET2_ATIM_GET(x) (((x) & RX_PRIORITY_OFFSET2_ATIM_MASK) >> RX_PRIORITY_OFFSET2_ATIM_LSB) +#define RX_PRIORITY_OFFSET2_ATIM_SET(x) (((x) << RX_PRIORITY_OFFSET2_ATIM_LSB) & RX_PRIORITY_OFFSET2_ATIM_MASK) +#define RX_PRIORITY_OFFSET2_PRESP_MSB 11 +#define RX_PRIORITY_OFFSET2_PRESP_LSB 6 +#define RX_PRIORITY_OFFSET2_PRESP_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET2_PRESP_GET(x) (((x) & RX_PRIORITY_OFFSET2_PRESP_MASK) >> RX_PRIORITY_OFFSET2_PRESP_LSB) +#define RX_PRIORITY_OFFSET2_PRESP_SET(x) (((x) << RX_PRIORITY_OFFSET2_PRESP_LSB) & RX_PRIORITY_OFFSET2_PRESP_MASK) +#define RX_PRIORITY_OFFSET2_XCAST_MSB 5 +#define RX_PRIORITY_OFFSET2_XCAST_LSB 0 +#define RX_PRIORITY_OFFSET2_XCAST_MASK 0x0000003f +#define RX_PRIORITY_OFFSET2_XCAST_GET(x) (((x) & RX_PRIORITY_OFFSET2_XCAST_MASK) >> RX_PRIORITY_OFFSET2_XCAST_LSB) +#define RX_PRIORITY_OFFSET2_XCAST_SET(x) (((x) << RX_PRIORITY_OFFSET2_XCAST_LSB) & RX_PRIORITY_OFFSET2_XCAST_MASK) + +#define RX_PRIORITY_OFFSET3_ADDRESS 0x00008390 +#define RX_PRIORITY_OFFSET3_OFFSET 0x00000390 +#define RX_PRIORITY_OFFSET3_PS_POLL_MSB 29 +#define RX_PRIORITY_OFFSET3_PS_POLL_LSB 24 +#define RX_PRIORITY_OFFSET3_PS_POLL_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET3_PS_POLL_GET(x) (((x) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) >> RX_PRIORITY_OFFSET3_PS_POLL_LSB) +#define RX_PRIORITY_OFFSET3_PS_POLL_SET(x) (((x) << RX_PRIORITY_OFFSET3_PS_POLL_LSB) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) +#define RX_PRIORITY_OFFSET3_AMSDU_MSB 23 +#define RX_PRIORITY_OFFSET3_AMSDU_LSB 18 +#define RX_PRIORITY_OFFSET3_AMSDU_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET3_AMSDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMSDU_MASK) >> RX_PRIORITY_OFFSET3_AMSDU_LSB) +#define RX_PRIORITY_OFFSET3_AMSDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMSDU_LSB) & RX_PRIORITY_OFFSET3_AMSDU_MASK) +#define RX_PRIORITY_OFFSET3_AMPDU_MSB 17 +#define RX_PRIORITY_OFFSET3_AMPDU_LSB 12 +#define RX_PRIORITY_OFFSET3_AMPDU_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET3_AMPDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMPDU_MASK) >> RX_PRIORITY_OFFSET3_AMPDU_LSB) +#define RX_PRIORITY_OFFSET3_AMPDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMPDU_LSB) & RX_PRIORITY_OFFSET3_AMPDU_MASK) +#define RX_PRIORITY_OFFSET3_EOSP_MSB 11 +#define RX_PRIORITY_OFFSET3_EOSP_LSB 6 +#define RX_PRIORITY_OFFSET3_EOSP_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET3_EOSP_GET(x) (((x) & RX_PRIORITY_OFFSET3_EOSP_MASK) >> RX_PRIORITY_OFFSET3_EOSP_LSB) +#define RX_PRIORITY_OFFSET3_EOSP_SET(x) (((x) << RX_PRIORITY_OFFSET3_EOSP_LSB) & RX_PRIORITY_OFFSET3_EOSP_MASK) +#define RX_PRIORITY_OFFSET3_MORE_MSB 5 +#define RX_PRIORITY_OFFSET3_MORE_LSB 0 +#define RX_PRIORITY_OFFSET3_MORE_MASK 0x0000003f +#define RX_PRIORITY_OFFSET3_MORE_GET(x) (((x) & RX_PRIORITY_OFFSET3_MORE_MASK) >> RX_PRIORITY_OFFSET3_MORE_LSB) +#define RX_PRIORITY_OFFSET3_MORE_SET(x) (((x) << RX_PRIORITY_OFFSET3_MORE_LSB) & RX_PRIORITY_OFFSET3_MORE_MASK) + +#define RX_PRIORITY_OFFSET4_ADDRESS 0x00008394 +#define RX_PRIORITY_OFFSET4_OFFSET 0x00000394 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MSB 29 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MSB 23 +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB 18 +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET4_BEACON_SSID_MSB 17 +#define RX_PRIORITY_OFFSET4_BEACON_SSID_LSB 12 +#define RX_PRIORITY_OFFSET4_BEACON_SSID_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET4_BEACON_SSID_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) >> RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) +#define RX_PRIORITY_OFFSET4_BEACON_SSID_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) +#define RX_PRIORITY_OFFSET4_NULL_MSB 11 +#define RX_PRIORITY_OFFSET4_NULL_LSB 6 +#define RX_PRIORITY_OFFSET4_NULL_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET4_NULL_GET(x) (((x) & RX_PRIORITY_OFFSET4_NULL_MASK) >> RX_PRIORITY_OFFSET4_NULL_LSB) +#define RX_PRIORITY_OFFSET4_NULL_SET(x) (((x) << RX_PRIORITY_OFFSET4_NULL_LSB) & RX_PRIORITY_OFFSET4_NULL_MASK) +#define RX_PRIORITY_OFFSET4_PREQ_MSB 5 +#define RX_PRIORITY_OFFSET4_PREQ_LSB 0 +#define RX_PRIORITY_OFFSET4_PREQ_MASK 0x0000003f +#define RX_PRIORITY_OFFSET4_PREQ_GET(x) (((x) & RX_PRIORITY_OFFSET4_PREQ_MASK) >> RX_PRIORITY_OFFSET4_PREQ_LSB) +#define RX_PRIORITY_OFFSET4_PREQ_SET(x) (((x) << RX_PRIORITY_OFFSET4_PREQ_LSB) & RX_PRIORITY_OFFSET4_PREQ_MASK) + +#define RX_PRIORITY_OFFSET5_ADDRESS 0x00008398 +#define RX_PRIORITY_OFFSET5_OFFSET 0x00000398 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MSB 17 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB 12 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MSB 11 +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB 6 +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MSB 5 +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB 0 +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK 0x0000003f +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) + +#define MAC_PCU_BSSID2_L32_ADDRESS 0x0000839c +#define MAC_PCU_BSSID2_L32_OFFSET 0x0000039c +#define MAC_PCU_BSSID2_L32_ADDR_MSB 31 +#define MAC_PCU_BSSID2_L32_ADDR_LSB 0 +#define MAC_PCU_BSSID2_L32_ADDR_MASK 0xffffffff +#define MAC_PCU_BSSID2_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_L32_ADDR_MASK) >> MAC_PCU_BSSID2_L32_ADDR_LSB) +#define MAC_PCU_BSSID2_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_L32_ADDR_LSB) & MAC_PCU_BSSID2_L32_ADDR_MASK) + +#define MAC_PCU_BSSID2_U16_ADDRESS 0x000083a0 +#define MAC_PCU_BSSID2_U16_OFFSET 0x000003a0 +#define MAC_PCU_BSSID2_U16_ENABLE_MSB 16 +#define MAC_PCU_BSSID2_U16_ENABLE_LSB 16 +#define MAC_PCU_BSSID2_U16_ENABLE_MASK 0x00010000 +#define MAC_PCU_BSSID2_U16_ENABLE_GET(x) (((x) & MAC_PCU_BSSID2_U16_ENABLE_MASK) >> MAC_PCU_BSSID2_U16_ENABLE_LSB) +#define MAC_PCU_BSSID2_U16_ENABLE_SET(x) (((x) << MAC_PCU_BSSID2_U16_ENABLE_LSB) & MAC_PCU_BSSID2_U16_ENABLE_MASK) +#define MAC_PCU_BSSID2_U16_ADDR_MSB 15 +#define MAC_PCU_BSSID2_U16_ADDR_LSB 0 +#define MAC_PCU_BSSID2_U16_ADDR_MASK 0x0000ffff +#define MAC_PCU_BSSID2_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_U16_ADDR_MASK) >> MAC_PCU_BSSID2_U16_ADDR_LSB) +#define MAC_PCU_BSSID2_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_U16_ADDR_LSB) & MAC_PCU_BSSID2_U16_ADDR_MASK) + +#define MAC_PCU_TSF1_STATUS_L32_ADDRESS 0x000083a4 +#define MAC_PCU_TSF1_STATUS_L32_OFFSET 0x000003a4 +#define MAC_PCU_TSF1_STATUS_L32_VALUE_MSB 31 +#define MAC_PCU_TSF1_STATUS_L32_VALUE_LSB 0 +#define MAC_PCU_TSF1_STATUS_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF1_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) +#define MAC_PCU_TSF1_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) + +#define MAC_PCU_TSF1_STATUS_U32_ADDRESS 0x000083a8 +#define MAC_PCU_TSF1_STATUS_U32_OFFSET 0x000003a8 +#define MAC_PCU_TSF1_STATUS_U32_VALUE_MSB 31 +#define MAC_PCU_TSF1_STATUS_U32_VALUE_LSB 0 +#define MAC_PCU_TSF1_STATUS_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF1_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) +#define MAC_PCU_TSF1_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) + +#define MAC_PCU_TSF2_STATUS_L32_ADDRESS 0x000083ac +#define MAC_PCU_TSF2_STATUS_L32_OFFSET 0x000003ac +#define MAC_PCU_TSF2_STATUS_L32_VALUE_MSB 31 +#define MAC_PCU_TSF2_STATUS_L32_VALUE_LSB 0 +#define MAC_PCU_TSF2_STATUS_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) +#define MAC_PCU_TSF2_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) + +#define MAC_PCU_TSF2_STATUS_U32_ADDRESS 0x000083b0 +#define MAC_PCU_TSF2_STATUS_U32_OFFSET 0x000003b0 +#define MAC_PCU_TSF2_STATUS_U32_VALUE_MSB 31 +#define MAC_PCU_TSF2_STATUS_U32_VALUE_LSB 0 +#define MAC_PCU_TSF2_STATUS_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) +#define MAC_PCU_TSF2_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) + +#define MAC_PCU_TXBUF_BA_ADDRESS 0x00008400 +#define MAC_PCU_TXBUF_BA_OFFSET 0x00000400 +#define MAC_PCU_TXBUF_BA_DATA_MSB 31 +#define MAC_PCU_TXBUF_BA_DATA_LSB 0 +#define MAC_PCU_TXBUF_BA_DATA_MASK 0xffffffff +#define MAC_PCU_TXBUF_BA_DATA_GET(x) (((x) & MAC_PCU_TXBUF_BA_DATA_MASK) >> MAC_PCU_TXBUF_BA_DATA_LSB) +#define MAC_PCU_TXBUF_BA_DATA_SET(x) (((x) << MAC_PCU_TXBUF_BA_DATA_LSB) & MAC_PCU_TXBUF_BA_DATA_MASK) + +#define MAC_PCU_KEY_CACHE_1_ADDRESS 0x00008800 +#define MAC_PCU_KEY_CACHE_1_OFFSET 0x00000800 +#define MAC_PCU_KEY_CACHE_1_DATA_MSB 31 +#define MAC_PCU_KEY_CACHE_1_DATA_LSB 0 +#define MAC_PCU_KEY_CACHE_1_DATA_MASK 0xffffffff +#define MAC_PCU_KEY_CACHE_1_DATA_GET(x) (((x) & MAC_PCU_KEY_CACHE_1_DATA_MASK) >> MAC_PCU_KEY_CACHE_1_DATA_LSB) +#define MAC_PCU_KEY_CACHE_1_DATA_SET(x) (((x) << MAC_PCU_KEY_CACHE_1_DATA_LSB) & MAC_PCU_KEY_CACHE_1_DATA_MASK) + +#define MAC_PCU_BASEBAND_0_ADDRESS 0x00009800 +#define MAC_PCU_BASEBAND_0_OFFSET 0x00001800 +#define MAC_PCU_BASEBAND_0_DATA_MSB 31 +#define MAC_PCU_BASEBAND_0_DATA_LSB 0 +#define MAC_PCU_BASEBAND_0_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_0_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_0_DATA_MASK) >> MAC_PCU_BASEBAND_0_DATA_LSB) +#define MAC_PCU_BASEBAND_0_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_0_DATA_LSB) & MAC_PCU_BASEBAND_0_DATA_MASK) + +#define MAC_PCU_BASEBAND_1_ADDRESS 0x0000a000 +#define MAC_PCU_BASEBAND_1_OFFSET 0x00002000 +#define MAC_PCU_BASEBAND_1_DATA_MSB 31 +#define MAC_PCU_BASEBAND_1_DATA_LSB 0 +#define MAC_PCU_BASEBAND_1_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_1_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_1_DATA_MASK) >> MAC_PCU_BASEBAND_1_DATA_LSB) +#define MAC_PCU_BASEBAND_1_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_1_DATA_LSB) & MAC_PCU_BASEBAND_1_DATA_MASK) + +#define MAC_PCU_BASEBAND_2_ADDRESS 0x0000c000 +#define MAC_PCU_BASEBAND_2_OFFSET 0x00004000 +#define MAC_PCU_BASEBAND_2_DATA_MSB 31 +#define MAC_PCU_BASEBAND_2_DATA_LSB 0 +#define MAC_PCU_BASEBAND_2_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_2_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_2_DATA_MASK) >> MAC_PCU_BASEBAND_2_DATA_LSB) +#define MAC_PCU_BASEBAND_2_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_2_DATA_LSB) & MAC_PCU_BASEBAND_2_DATA_MASK) + +#define MAC_PCU_BASEBAND_3_ADDRESS 0x0000d000 +#define MAC_PCU_BASEBAND_3_OFFSET 0x00005000 +#define MAC_PCU_BASEBAND_3_DATA_MSB 31 +#define MAC_PCU_BASEBAND_3_DATA_LSB 0 +#define MAC_PCU_BASEBAND_3_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_3_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_3_DATA_MASK) >> MAC_PCU_BASEBAND_3_DATA_LSB) +#define MAC_PCU_BASEBAND_3_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_3_DATA_LSB) & MAC_PCU_BASEBAND_3_DATA_MASK) + +#define MAC_PCU_BUF_ADDRESS 0x0000e000 +#define MAC_PCU_BUF_OFFSET 0x00006000 +#define MAC_PCU_BUF_DATA_MSB 31 +#define MAC_PCU_BUF_DATA_LSB 0 +#define MAC_PCU_BUF_DATA_MASK 0xffffffff +#define MAC_PCU_BUF_DATA_GET(x) (((x) & MAC_PCU_BUF_DATA_MASK) >> MAC_PCU_BUF_DATA_LSB) +#define MAC_PCU_BUF_DATA_SET(x) (((x) << MAC_PCU_BUF_DATA_LSB) & MAC_PCU_BUF_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mac_pcu_reg_s { + volatile unsigned int mac_pcu_sta_addr_l32; + volatile unsigned int mac_pcu_sta_addr_u16; + volatile unsigned int mac_pcu_bssid_l32; + volatile unsigned int mac_pcu_bssid_u16; + volatile unsigned int mac_pcu_bcn_rssi_ave; + volatile unsigned int mac_pcu_ack_cts_timeout; + volatile unsigned int mac_pcu_bcn_rssi_ctl; + volatile unsigned int mac_pcu_usec_latency; + volatile unsigned int pcu_max_cfp_dur; + volatile unsigned int mac_pcu_rx_filter; + volatile unsigned int mac_pcu_mcast_filter_l32; + volatile unsigned int mac_pcu_mcast_filter_u32; + volatile unsigned int mac_pcu_diag_sw; + volatile unsigned int mac_pcu_tst_addac; + volatile unsigned int mac_pcu_def_antenna; + volatile unsigned int mac_pcu_aes_mute_mask_0; + volatile unsigned int mac_pcu_aes_mute_mask_1; + volatile unsigned int mac_pcu_gated_clks; + volatile unsigned int mac_pcu_obs_bus_2; + volatile unsigned int mac_pcu_obs_bus_1; + volatile unsigned int mac_pcu_dym_mimo_pwr_save; + volatile unsigned int mac_pcu_last_beacon_tsf; + volatile unsigned int mac_pcu_nav; + volatile unsigned int mac_pcu_rts_success_cnt; + volatile unsigned int mac_pcu_rts_fail_cnt; + volatile unsigned int mac_pcu_ack_fail_cnt; + volatile unsigned int mac_pcu_fcs_fail_cnt; + volatile unsigned int mac_pcu_beacon_cnt; + volatile unsigned int mac_pcu_xrmode; + volatile unsigned int mac_pcu_xrdel; + volatile unsigned int mac_pcu_xrto; + volatile unsigned int mac_pcu_xrcrp; + volatile unsigned int mac_pcu_xrstmp; + volatile unsigned int mac_pcu_addr1_mask_l32; + volatile unsigned int mac_pcu_addr1_mask_u16; + volatile unsigned int mac_pcu_tpc; + volatile unsigned int mac_pcu_tx_frame_cnt; + volatile unsigned int mac_pcu_rx_frame_cnt; + volatile unsigned int mac_pcu_rx_clear_cnt; + volatile unsigned int mac_pcu_cycle_cnt; + volatile unsigned int mac_pcu_quiet_time_1; + volatile unsigned int mac_pcu_quiet_time_2; + volatile unsigned int mac_pcu_qos_no_ack; + volatile unsigned int mac_pcu_phy_error_mask; + volatile unsigned int mac_pcu_xrlat; + volatile unsigned int mac_pcu_rxbuf; + volatile unsigned int mac_pcu_mic_qos_control; + volatile unsigned int mac_pcu_mic_qos_select; + volatile unsigned int mac_pcu_misc_mode; + volatile unsigned int mac_pcu_filter_ofdm_cnt; + volatile unsigned int mac_pcu_filter_cck_cnt; + volatile unsigned int mac_pcu_phy_err_cnt_1; + volatile unsigned int mac_pcu_phy_err_cnt_1_mask; + volatile unsigned int mac_pcu_phy_err_cnt_2; + volatile unsigned int mac_pcu_phy_err_cnt_2_mask; + volatile unsigned int mac_pcu_tsf_threshold; + volatile unsigned int mac_pcu_phy_error_eifs_mask; + volatile unsigned int mac_pcu_phy_err_cnt_3; + volatile unsigned int mac_pcu_phy_err_cnt_3_mask; + volatile unsigned int mac_pcu_bluetooth_mode; + volatile unsigned int mac_pcu_bluetooth_weights; + volatile unsigned int mac_pcu_bluetooth_mode2; + volatile unsigned int mac_pcu_txsifs; + volatile unsigned int mac_pcu_txop_x; + volatile unsigned int mac_pcu_txop_0_3; + volatile unsigned int mac_pcu_txop_4_7; + volatile unsigned int mac_pcu_txop_8_11; + volatile unsigned int mac_pcu_txop_12_15; + volatile unsigned int mac_pcu_logic_analyzer; + volatile unsigned int mac_pcu_logic_analyzer_32l; + volatile unsigned int mac_pcu_logic_analyzer_16u; + volatile unsigned int mac_pcu_phy_err_cnt_mask_cont; + volatile unsigned int mac_pcu_azimuth_mode; + volatile unsigned int mac_pcu_20_40_mode; + volatile unsigned int mac_pcu_rx_clear_diff_cnt; + volatile unsigned int mac_pcu_self_gen_antenna_mask; + volatile unsigned int mac_pcu_ba_bar_control; + volatile unsigned int mac_pcu_legacy_plcp_spoof; + volatile unsigned int mac_pcu_phy_error_mask_cont; + volatile unsigned int mac_pcu_tx_timer; + volatile unsigned int mac_pcu_txbuf_ctrl; + volatile unsigned int mac_pcu_misc_mode2; + volatile unsigned int mac_pcu_alt_aes_mute_mask; + volatile unsigned int mac_pcu_azimuth_time_stamp; + volatile unsigned int mac_pcu_max_cfp_dur; + volatile unsigned int mac_pcu_hcf_timeout; + volatile unsigned int mac_pcu_bluetooth_weights2; + volatile unsigned int mac_pcu_bluetooth_tsf_bt_active; + volatile unsigned int mac_pcu_bluetooth_tsf_bt_priority; + volatile unsigned int mac_pcu_bluetooth_mode3; + volatile unsigned int mac_pcu_bluetooth_mode4; + unsigned char pad0[148]; /* pad to 0x200 */ + volatile unsigned int mac_pcu_bt_bt[64]; + volatile unsigned int mac_pcu_bt_bt_async; + volatile unsigned int mac_pcu_bt_wl_1; + volatile unsigned int mac_pcu_bt_wl_2; + volatile unsigned int mac_pcu_bt_wl_3; + volatile unsigned int mac_pcu_bt_wl_4; + volatile unsigned int mac_pcu_coex_epta; + volatile unsigned int mac_pcu_coex_lnamaxgain1; + volatile unsigned int mac_pcu_coex_lnamaxgain2; + volatile unsigned int mac_pcu_coex_lnamaxgain3; + volatile unsigned int mac_pcu_coex_lnamaxgain4; + volatile unsigned int mac_pcu_basic_rate_set0; + volatile unsigned int mac_pcu_basic_rate_set1; + volatile unsigned int mac_pcu_basic_rate_set2; + volatile unsigned int mac_pcu_basic_rate_set3; + volatile unsigned int mac_pcu_rx_int_status0; + volatile unsigned int mac_pcu_rx_int_status1; + volatile unsigned int mac_pcu_rx_int_status2; + volatile unsigned int mac_pcu_rx_int_status3; + volatile unsigned int ht_half_gi_rate1; + volatile unsigned int ht_half_gi_rate2; + volatile unsigned int ht_full_gi_rate1; + volatile unsigned int ht_full_gi_rate2; + volatile unsigned int legacy_rate1; + volatile unsigned int legacy_rate2; + volatile unsigned int legacy_rate3; + volatile unsigned int rx_int_filter; + volatile unsigned int rx_int_overflow; + volatile unsigned int rx_filter_thresh; + volatile unsigned int rx_filter_thresh1; + volatile unsigned int rx_priority_thresh0; + volatile unsigned int rx_priority_thresh1; + volatile unsigned int rx_priority_thresh2; + volatile unsigned int rx_priority_thresh3; + volatile unsigned int rx_priority_offset0; + volatile unsigned int rx_priority_offset1; + volatile unsigned int rx_priority_offset2; + volatile unsigned int rx_priority_offset3; + volatile unsigned int rx_priority_offset4; + volatile unsigned int rx_priority_offset5; + volatile unsigned int mac_pcu_bssid2_l32; + volatile unsigned int mac_pcu_bssid2_u16; + volatile unsigned int mac_pcu_tsf1_status_l32; + volatile unsigned int mac_pcu_tsf1_status_u32; + volatile unsigned int mac_pcu_tsf2_status_l32; + volatile unsigned int mac_pcu_tsf2_status_u32; + unsigned char pad1[76]; /* pad to 0x400 */ + volatile unsigned int mac_pcu_txbuf_ba[64]; + unsigned char pad2[768]; /* pad to 0x800 */ + volatile unsigned int mac_pcu_key_cache_1[256]; + unsigned char pad3[3072]; /* pad to 0x1800 */ + volatile unsigned int mac_pcu_baseband_0[512]; + volatile unsigned int mac_pcu_baseband_1[2048]; + volatile unsigned int mac_pcu_baseband_2[1024]; + volatile unsigned int mac_pcu_baseband_3[1024]; + volatile unsigned int mac_pcu_buf[512]; +} mac_pcu_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MAC_PCU_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h new file mode 100644 index 000000000000..3af562156f6e --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h @@ -0,0 +1,37 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "mbox_wlan_host_reg.h" + + +#ifndef BT_HEADERS + + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h new file mode 100644 index 000000000000..cc67585e2e8b --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h @@ -0,0 +1,560 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "mbox_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS +#define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET +#define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB +#define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB +#define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK +#define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x) +#define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x) +#define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS +#define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET +#define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB +#define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB +#define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK +#define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) +#define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB +#define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB +#define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK +#define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x) +#define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x) +#define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS +#define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) +#define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB +#define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB +#define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) +#define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB +#define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB +#define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS +#define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB +#define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB +#define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK +#define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB +#define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB +#define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS +#define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB +#define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB +#define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK +#define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB +#define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB +#define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS +#define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB +#define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB +#define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK +#define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB +#define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB +#define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS +#define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB +#define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB +#define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK +#define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB +#define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB +#define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS +#define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB +#define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB +#define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK +#define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB +#define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB +#define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS +#define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB +#define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB +#define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK +#define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB +#define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB +#define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS +#define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB +#define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB +#define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK +#define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB +#define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB +#define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS +#define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB +#define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB +#define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK +#define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB +#define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB +#define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS +#define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) +#define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB +#define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB +#define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK +#define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x) +#define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x) +#define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS +#define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) +#define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB +#define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB +#define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK +#define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x) +#define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x) +#define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS +#define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET +#define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB +#define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB +#define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK +#define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x) +#define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x) +#define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS +#define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET +#define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB +#define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB +#define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK +#define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x) +#define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x) +#define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS +#define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET +#define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB +#define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB +#define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK +#define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x) +#define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x) +#define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS +#define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET +#define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB +#define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB +#define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK +#define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x) +#define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x) +#define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS +#define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET +#define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB +#define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB +#define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK +#define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) +#define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS +#define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET +#define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB +#define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB +#define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK +#define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) +#define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS +#define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET +#define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB +#define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB +#define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK +#define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x) +#define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x) +#define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS +#define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET +#define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB +#define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB +#define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK +#define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x) +#define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x) +#define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS +#define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET +#define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB +#define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB +#define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK +#define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x) +#define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x) +#define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS +#define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET +#define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB +#define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB +#define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK +#define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x) +#define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x) +#define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS +#define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET +#define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB +#define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB +#define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK +#define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x) +#define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x) +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS +#define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET +#define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB +#define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB +#define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK +#define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) +#define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) +#define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB +#define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB +#define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK +#define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) +#define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) +#define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB +#define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB +#define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK +#define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) +#define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS +#define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET +#define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB +#define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB +#define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK +#define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) +#define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) +#define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB +#define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB +#define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK +#define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) +#define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) +#define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB +#define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB +#define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK +#define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) +#define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) +#define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS +#define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET +#define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB +#define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB +#define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK +#define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) +#define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) +#define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB +#define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB +#define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK +#define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) +#define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) +#define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB +#define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB +#define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK +#define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) +#define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) +#define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS +#define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET +#define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB +#define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB +#define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK +#define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) +#define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) +#define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB +#define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB +#define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK +#define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) +#define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) +#define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS +#define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET +#define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB +#define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB +#define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK +#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x) +#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x) + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h new file mode 100644 index 000000000000..60855021c2b0 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h @@ -0,0 +1,522 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_WLAN_HOST_REG_REG_H_ +#define _MBOX_WLAN_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_INT_MSB 5 +#define HOST_INT_STATUS_INT_LSB 5 +#define HOST_INT_STATUS_INT_MASK 0x00000020 +#define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB) +#define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define HOST_INT_STATUS2_ADDRESS 0x00000406 +#define HOST_INT_STATUS2_OFFSET 0x00000406 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1 +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1 +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002 +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) +#define HOST_INT_STATUS2_GMBOX_DATA_MSB 0 +#define HOST_INT_STATUS2_GMBOX_DATA_LSB 0 +#define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001 +#define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB) +#define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK) + +#define GMBOX_RX_AVAIL_ADDRESS 0x00000407 +#define GMBOX_RX_AVAIL_OFFSET 0x00000407 +#define GMBOX_RX_AVAIL_BYTE_MSB 6 +#define GMBOX_RX_AVAIL_BYTE_LSB 0 +#define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f +#define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB) +#define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_INT_MSB 5 +#define INT_STATUS_ENABLE_INT_LSB 5 +#define INT_STATUS_ENABLE_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB) +#define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480 +#define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2 +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2 +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1 +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0 +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) + +#define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481 +#define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) +#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2 +#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2 +#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004 +#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB) +#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) +#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1 +#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1 +#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002 +#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB) +#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) +#define HOST_CTRL_SPI_STATUS_READY_MSB 0 +#define HOST_CTRL_SPI_STATUS_READY_LSB 0 +#define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001 +#define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB) +#define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CPU_DBG_SEL_ADDRESS 0x00000483 +#define CPU_DBG_SEL_OFFSET 0x00000483 +#define CPU_DBG_SEL_BIT_MSB 5 +#define CPU_DBG_SEL_BIT_LSB 0 +#define CPU_DBG_SEL_BIT_MASK 0x0000003f +#define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB) +#define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK) + +#define CPU_DBG_ADDRESS 0x00000484 +#define CPU_DBG_OFFSET 0x00000484 +#define CPU_DBG_DATA_MSB 7 +#define CPU_DBG_DATA_LSB 0 +#define CPU_DBG_DATA_MASK 0x000000ff +#define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB) +#define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK) + +#define INT_STATUS2_ENABLE_ADDRESS 0x00000488 +#define INT_STATUS2_ENABLE_OFFSET 0x00000488 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1 +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1 +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002 +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) +#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0 +#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0 +#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001 +#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB) +#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) + +#define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490 +#define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490 +#define GMBOX_RX_LOOKAHEAD_DATA_MSB 7 +#define GMBOX_RX_LOOKAHEAD_DATA_LSB 0 +#define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff +#define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB) +#define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK) + +#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498 +#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_wlan_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + volatile unsigned char host_int_status2; + volatile unsigned char gmbox_rx_avail; + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad1[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad2[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad3[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad4[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad5[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char host_ctrl_spi_config; + volatile unsigned char host_ctrl_spi_status; + volatile unsigned char non_assoc_sleep_en; + volatile unsigned char cpu_dbg_sel; + volatile unsigned char cpu_dbg[4]; + volatile unsigned char int_status2_enable; + unsigned char pad6[7]; /* pad to 0x490 */ + volatile unsigned char gmbox_rx_lookahead[8]; + volatile unsigned char gmbox_rx_lookahead_mux; + unsigned char pad7[359]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_wlan_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_WLAN_HOST_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h new file mode 100644 index 000000000000..e00270fc1450 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h @@ -0,0 +1,638 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_WLAN_REG_REG_H_ +#define _MBOX_WLAN_REG_REG_H_ + +#define WLAN_MBOX_FIFO_ADDRESS 0x00000000 +#define WLAN_MBOX_FIFO_OFFSET 0x00000000 +#define WLAN_MBOX_FIFO_DATA_MSB 19 +#define WLAN_MBOX_FIFO_DATA_LSB 0 +#define WLAN_MBOX_FIFO_DATA_MASK 0x000fffff +#define WLAN_MBOX_FIFO_DATA_GET(x) (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB) +#define WLAN_MBOX_FIFO_DATA_SET(x) (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK) + +#define WLAN_MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define WLAN_MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) +#define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) +#define WLAN_MBOX_FIFO_STATUS_FULL_MSB 15 +#define WLAN_MBOX_FIFO_STATUS_FULL_LSB 12 +#define WLAN_MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define WLAN_MBOX_FIFO_STATUS_FULL_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB) +#define WLAN_MBOX_FIFO_STATUS_FULL_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) + +#define WLAN_MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define WLAN_MBOX_DMA_POLICY_OFFSET 0x00000014 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX_INT_STATUS_ADDRESS 0x00000058 +#define WLAN_MBOX_INT_STATUS_OFFSET 0x00000058 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define WLAN_MBOX_INT_STATUS_HOST_MSB 7 +#define WLAN_MBOX_INT_STATUS_HOST_LSB 0 +#define WLAN_MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define WLAN_MBOX_INT_STATUS_HOST_GET(x) (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB) +#define WLAN_MBOX_INT_STATUS_HOST_SET(x) (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK) + +#define WLAN_MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define WLAN_MBOX_INT_ENABLE_OFFSET 0x0000005c +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define WLAN_MBOX_INT_ENABLE_HOST_MSB 7 +#define WLAN_MBOX_INT_ENABLE_HOST_LSB 0 +#define WLAN_MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define WLAN_MBOX_INT_ENABLE_HOST_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB) +#define WLAN_MBOX_INT_ENABLE_HOST_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK) + +#define WLAN_INT_HOST_ADDRESS 0x00000060 +#define WLAN_INT_HOST_OFFSET 0x00000060 +#define WLAN_INT_HOST_VECTOR_MSB 7 +#define WLAN_INT_HOST_VECTOR_LSB 0 +#define WLAN_INT_HOST_VECTOR_MASK 0x000000ff +#define WLAN_INT_HOST_VECTOR_GET(x) (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB) +#define WLAN_INT_HOST_VECTOR_SET(x) (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK) + +#define WLAN_LOCAL_COUNT_ADDRESS 0x00000080 +#define WLAN_LOCAL_COUNT_OFFSET 0x00000080 +#define WLAN_LOCAL_COUNT_VALUE_MSB 7 +#define WLAN_LOCAL_COUNT_VALUE_LSB 0 +#define WLAN_LOCAL_COUNT_VALUE_MASK 0x000000ff +#define WLAN_LOCAL_COUNT_VALUE_GET(x) (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB) +#define WLAN_LOCAL_COUNT_VALUE_SET(x) (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK) + +#define WLAN_COUNT_INC_ADDRESS 0x000000a0 +#define WLAN_COUNT_INC_OFFSET 0x000000a0 +#define WLAN_COUNT_INC_VALUE_MSB 7 +#define WLAN_COUNT_INC_VALUE_LSB 0 +#define WLAN_COUNT_INC_VALUE_MASK 0x000000ff +#define WLAN_COUNT_INC_VALUE_GET(x) (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB) +#define WLAN_COUNT_INC_VALUE_SET(x) (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK) + +#define WLAN_LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define WLAN_LOCAL_SCRATCH_OFFSET 0x000000c0 +#define WLAN_LOCAL_SCRATCH_VALUE_MSB 7 +#define WLAN_LOCAL_SCRATCH_VALUE_LSB 0 +#define WLAN_LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define WLAN_LOCAL_SCRATCH_VALUE_GET(x) (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB) +#define WLAN_LOCAL_SCRATCH_VALUE_SET(x) (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK) + +#define WLAN_USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define WLAN_USE_LOCAL_BUS_OFFSET 0x000000e0 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) +#define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) + +#define WLAN_SDIO_CONFIG_ADDRESS 0x000000e4 +#define WLAN_SDIO_CONFIG_OFFSET 0x000000e4 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) +#define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) + +#define WLAN_MBOX_DEBUG_ADDRESS 0x000000e8 +#define WLAN_MBOX_DEBUG_OFFSET 0x000000e8 +#define WLAN_MBOX_DEBUG_SEL_MSB 2 +#define WLAN_MBOX_DEBUG_SEL_LSB 0 +#define WLAN_MBOX_DEBUG_SEL_MASK 0x00000007 +#define WLAN_MBOX_DEBUG_SEL_GET(x) (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB) +#define WLAN_MBOX_DEBUG_SEL_SET(x) (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK) + +#define WLAN_MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define WLAN_MBOX_FIFO_RESET_OFFSET 0x000000ec +#define WLAN_MBOX_FIFO_RESET_INIT_MSB 0 +#define WLAN_MBOX_FIFO_RESET_INIT_LSB 0 +#define WLAN_MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define WLAN_MBOX_FIFO_RESET_INIT_GET(x) (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB) +#define WLAN_MBOX_FIFO_RESET_INIT_SET(x) (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK) + +#define WLAN_MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define WLAN_MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define WLAN_MBOX_TXFIFO_POP_DATA_MSB 0 +#define WLAN_MBOX_TXFIFO_POP_DATA_LSB 0 +#define WLAN_MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define WLAN_MBOX_TXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB) +#define WLAN_MBOX_TXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) + +#define WLAN_MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define WLAN_MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define WLAN_MBOX_RXFIFO_POP_DATA_MSB 0 +#define WLAN_MBOX_RXFIFO_POP_DATA_LSB 0 +#define WLAN_MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define WLAN_MBOX_RXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB) +#define WLAN_MBOX_RXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) + +#define WLAN_SDIO_DEBUG_ADDRESS 0x00000110 +#define WLAN_SDIO_DEBUG_OFFSET 0x00000110 +#define WLAN_SDIO_DEBUG_SEL_MSB 3 +#define WLAN_SDIO_DEBUG_SEL_LSB 0 +#define WLAN_SDIO_DEBUG_SEL_MASK 0x0000000f +#define WLAN_SDIO_DEBUG_SEL_GET(x) (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB) +#define WLAN_SDIO_DEBUG_SEL_SET(x) (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK) + +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000118 +#define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET 0x00000118 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS 0x00000120 +#define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET 0x00000120 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_GMBOX_INT_STATUS_ADDRESS 0x00000124 +#define WLAN_GMBOX_INT_STATUS_OFFSET 0x00000124 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB 6 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB 6 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000040 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB 5 +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB 5 +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000020 +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4 +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4 +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010 +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1 +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1 +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002 +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB 0 +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB 0 +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001 +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) + +#define WLAN_GMBOX_INT_ENABLE_ADDRESS 0x00000128 +#define WLAN_GMBOX_INT_ENABLE_OFFSET 0x00000128 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB 6 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB 6 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000040 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 5 +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 5 +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000020 +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4 +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4 +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010 +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1 +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1 +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002 +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0 +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0 +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001 +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) + +#define WLAN_HOST_IF_WINDOW_ADDRESS 0x00002000 +#define WLAN_HOST_IF_WINDOW_OFFSET 0x00002000 +#define WLAN_HOST_IF_WINDOW_DATA_MSB 7 +#define WLAN_HOST_IF_WINDOW_DATA_LSB 0 +#define WLAN_HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB) +#define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_wlan_reg_reg_s { + volatile unsigned int wlan_mbox_fifo[4]; + volatile unsigned int wlan_mbox_fifo_status; + volatile unsigned int wlan_mbox_dma_policy; + volatile unsigned int wlan_mbox0_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox0_dma_rx_control; + volatile unsigned int wlan_mbox0_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox0_dma_tx_control; + volatile unsigned int wlan_mbox1_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox1_dma_rx_control; + volatile unsigned int wlan_mbox1_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox1_dma_tx_control; + volatile unsigned int wlan_mbox2_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox2_dma_rx_control; + volatile unsigned int wlan_mbox2_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox2_dma_tx_control; + volatile unsigned int wlan_mbox3_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox3_dma_rx_control; + volatile unsigned int wlan_mbox3_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox3_dma_tx_control; + volatile unsigned int wlan_mbox_int_status; + volatile unsigned int wlan_mbox_int_enable; + volatile unsigned int wlan_int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int wlan_local_count[8]; + volatile unsigned int wlan_count_inc[8]; + volatile unsigned int wlan_local_scratch[8]; + volatile unsigned int wlan_use_local_bus; + volatile unsigned int wlan_sdio_config; + volatile unsigned int wlan_mbox_debug; + volatile unsigned int wlan_mbox_fifo_reset; + volatile unsigned int wlan_mbox_txfifo_pop[4]; + volatile unsigned int wlan_mbox_rxfifo_pop[4]; + volatile unsigned int wlan_sdio_debug; + volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base; + volatile unsigned int wlan_gmbox0_dma_rx_control; + volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base; + volatile unsigned int wlan_gmbox0_dma_tx_control; + volatile unsigned int wlan_gmbox_int_status; + volatile unsigned int wlan_gmbox_int_enable; + unsigned char pad1[7892]; /* pad to 0x2000 */ + volatile unsigned int wlan_host_if_window[2048]; +} mbox_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h new file mode 100644 index 000000000000..56ffda5b1a30 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h @@ -0,0 +1,564 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RDMA_REG_REG_H_ +#define _RDMA_REG_REG_H_ + +#define DMA_CONFIG_ADDRESS 0x00000000 +#define DMA_CONFIG_OFFSET 0x00000000 +#define DMA_CONFIG_WLBB_PWD_EN_MSB 4 +#define DMA_CONFIG_WLBB_PWD_EN_LSB 4 +#define DMA_CONFIG_WLBB_PWD_EN_MASK 0x00000010 +#define DMA_CONFIG_WLBB_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB) +#define DMA_CONFIG_WLBB_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK) +#define DMA_CONFIG_WLMAC_PWD_EN_MSB 3 +#define DMA_CONFIG_WLMAC_PWD_EN_LSB 3 +#define DMA_CONFIG_WLMAC_PWD_EN_MASK 0x00000008 +#define DMA_CONFIG_WLMAC_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB) +#define DMA_CONFIG_WLMAC_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK) +#define DMA_CONFIG_ENABLE_RETENTION_MSB 2 +#define DMA_CONFIG_ENABLE_RETENTION_LSB 2 +#define DMA_CONFIG_ENABLE_RETENTION_MASK 0x00000004 +#define DMA_CONFIG_ENABLE_RETENTION_GET(x) (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB) +#define DMA_CONFIG_ENABLE_RETENTION_SET(x) (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK) +#define DMA_CONFIG_RTC_PRIORITY_MSB 1 +#define DMA_CONFIG_RTC_PRIORITY_LSB 1 +#define DMA_CONFIG_RTC_PRIORITY_MASK 0x00000002 +#define DMA_CONFIG_RTC_PRIORITY_GET(x) (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB) +#define DMA_CONFIG_RTC_PRIORITY_SET(x) (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK) +#define DMA_CONFIG_DMA_TYPE_MSB 0 +#define DMA_CONFIG_DMA_TYPE_LSB 0 +#define DMA_CONFIG_DMA_TYPE_MASK 0x00000001 +#define DMA_CONFIG_DMA_TYPE_GET(x) (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB) +#define DMA_CONFIG_DMA_TYPE_SET(x) (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK) + +#define DMA_CONTROL_ADDRESS 0x00000004 +#define DMA_CONTROL_OFFSET 0x00000004 +#define DMA_CONTROL_START_MSB 1 +#define DMA_CONTROL_START_LSB 1 +#define DMA_CONTROL_START_MASK 0x00000002 +#define DMA_CONTROL_START_GET(x) (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB) +#define DMA_CONTROL_START_SET(x) (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK) +#define DMA_CONTROL_STOP_MSB 0 +#define DMA_CONTROL_STOP_LSB 0 +#define DMA_CONTROL_STOP_MASK 0x00000001 +#define DMA_CONTROL_STOP_GET(x) (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB) +#define DMA_CONTROL_STOP_SET(x) (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK) + +#define DMA_SRC_ADDRESS 0x00000008 +#define DMA_SRC_OFFSET 0x00000008 +#define DMA_SRC_ADDR_MSB 31 +#define DMA_SRC_ADDR_LSB 2 +#define DMA_SRC_ADDR_MASK 0xfffffffc +#define DMA_SRC_ADDR_GET(x) (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB) +#define DMA_SRC_ADDR_SET(x) (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK) + +#define DMA_DEST_ADDRESS 0x0000000c +#define DMA_DEST_OFFSET 0x0000000c +#define DMA_DEST_ADDR_MSB 31 +#define DMA_DEST_ADDR_LSB 2 +#define DMA_DEST_ADDR_MASK 0xfffffffc +#define DMA_DEST_ADDR_GET(x) (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB) +#define DMA_DEST_ADDR_SET(x) (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK) + +#define DMA_LENGTH_ADDRESS 0x00000010 +#define DMA_LENGTH_OFFSET 0x00000010 +#define DMA_LENGTH_WORDS_MSB 11 +#define DMA_LENGTH_WORDS_LSB 0 +#define DMA_LENGTH_WORDS_MASK 0x00000fff +#define DMA_LENGTH_WORDS_GET(x) (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB) +#define DMA_LENGTH_WORDS_SET(x) (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK) + +#define VMC_BASE_ADDRESS 0x00000014 +#define VMC_BASE_OFFSET 0x00000014 +#define VMC_BASE_ADDR_MSB 31 +#define VMC_BASE_ADDR_LSB 2 +#define VMC_BASE_ADDR_MASK 0xfffffffc +#define VMC_BASE_ADDR_GET(x) (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB) +#define VMC_BASE_ADDR_SET(x) (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK) + +#define INDIRECT_REG_ADDRESS 0x00000018 +#define INDIRECT_REG_OFFSET 0x00000018 +#define INDIRECT_REG_ID_MSB 31 +#define INDIRECT_REG_ID_LSB 2 +#define INDIRECT_REG_ID_MASK 0xfffffffc +#define INDIRECT_REG_ID_GET(x) (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB) +#define INDIRECT_REG_ID_SET(x) (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK) + +#define INDIRECT_RETURN_ADDRESS 0x0000001c +#define INDIRECT_RETURN_OFFSET 0x0000001c +#define INDIRECT_RETURN_ADDR_MSB 31 +#define INDIRECT_RETURN_ADDR_LSB 2 +#define INDIRECT_RETURN_ADDR_MASK 0xfffffffc +#define INDIRECT_RETURN_ADDR_GET(x) (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB) +#define INDIRECT_RETURN_ADDR_SET(x) (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK) + +#define RDMA_REGION_0__ADDRESS 0x00000020 +#define RDMA_REGION_0__OFFSET 0x00000020 +#define RDMA_REGION_0__ADDR_MSB 31 +#define RDMA_REGION_0__ADDR_LSB 13 +#define RDMA_REGION_0__ADDR_MASK 0xffffe000 +#define RDMA_REGION_0__ADDR_GET(x) (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB) +#define RDMA_REGION_0__ADDR_SET(x) (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK) +#define RDMA_REGION_0__LENGTH_MSB 12 +#define RDMA_REGION_0__LENGTH_LSB 2 +#define RDMA_REGION_0__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_0__LENGTH_GET(x) (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB) +#define RDMA_REGION_0__LENGTH_SET(x) (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK) +#define RDMA_REGION_0__INDI_MSB 1 +#define RDMA_REGION_0__INDI_LSB 1 +#define RDMA_REGION_0__INDI_MASK 0x00000002 +#define RDMA_REGION_0__INDI_GET(x) (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB) +#define RDMA_REGION_0__INDI_SET(x) (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK) +#define RDMA_REGION_0__NEXT_MSB 0 +#define RDMA_REGION_0__NEXT_LSB 0 +#define RDMA_REGION_0__NEXT_MASK 0x00000001 +#define RDMA_REGION_0__NEXT_GET(x) (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB) +#define RDMA_REGION_0__NEXT_SET(x) (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK) + +#define RDMA_REGION_1__ADDRESS 0x00000024 +#define RDMA_REGION_1__OFFSET 0x00000024 +#define RDMA_REGION_1__ADDR_MSB 31 +#define RDMA_REGION_1__ADDR_LSB 13 +#define RDMA_REGION_1__ADDR_MASK 0xffffe000 +#define RDMA_REGION_1__ADDR_GET(x) (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB) +#define RDMA_REGION_1__ADDR_SET(x) (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK) +#define RDMA_REGION_1__LENGTH_MSB 12 +#define RDMA_REGION_1__LENGTH_LSB 2 +#define RDMA_REGION_1__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_1__LENGTH_GET(x) (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB) +#define RDMA_REGION_1__LENGTH_SET(x) (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK) +#define RDMA_REGION_1__INDI_MSB 1 +#define RDMA_REGION_1__INDI_LSB 1 +#define RDMA_REGION_1__INDI_MASK 0x00000002 +#define RDMA_REGION_1__INDI_GET(x) (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB) +#define RDMA_REGION_1__INDI_SET(x) (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK) +#define RDMA_REGION_1__NEXT_MSB 0 +#define RDMA_REGION_1__NEXT_LSB 0 +#define RDMA_REGION_1__NEXT_MASK 0x00000001 +#define RDMA_REGION_1__NEXT_GET(x) (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB) +#define RDMA_REGION_1__NEXT_SET(x) (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK) + +#define RDMA_REGION_2__ADDRESS 0x00000028 +#define RDMA_REGION_2__OFFSET 0x00000028 +#define RDMA_REGION_2__ADDR_MSB 31 +#define RDMA_REGION_2__ADDR_LSB 13 +#define RDMA_REGION_2__ADDR_MASK 0xffffe000 +#define RDMA_REGION_2__ADDR_GET(x) (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB) +#define RDMA_REGION_2__ADDR_SET(x) (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK) +#define RDMA_REGION_2__LENGTH_MSB 12 +#define RDMA_REGION_2__LENGTH_LSB 2 +#define RDMA_REGION_2__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_2__LENGTH_GET(x) (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB) +#define RDMA_REGION_2__LENGTH_SET(x) (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK) +#define RDMA_REGION_2__INDI_MSB 1 +#define RDMA_REGION_2__INDI_LSB 1 +#define RDMA_REGION_2__INDI_MASK 0x00000002 +#define RDMA_REGION_2__INDI_GET(x) (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB) +#define RDMA_REGION_2__INDI_SET(x) (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK) +#define RDMA_REGION_2__NEXT_MSB 0 +#define RDMA_REGION_2__NEXT_LSB 0 +#define RDMA_REGION_2__NEXT_MASK 0x00000001 +#define RDMA_REGION_2__NEXT_GET(x) (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB) +#define RDMA_REGION_2__NEXT_SET(x) (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK) + +#define RDMA_REGION_3__ADDRESS 0x0000002c +#define RDMA_REGION_3__OFFSET 0x0000002c +#define RDMA_REGION_3__ADDR_MSB 31 +#define RDMA_REGION_3__ADDR_LSB 13 +#define RDMA_REGION_3__ADDR_MASK 0xffffe000 +#define RDMA_REGION_3__ADDR_GET(x) (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB) +#define RDMA_REGION_3__ADDR_SET(x) (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK) +#define RDMA_REGION_3__LENGTH_MSB 12 +#define RDMA_REGION_3__LENGTH_LSB 2 +#define RDMA_REGION_3__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_3__LENGTH_GET(x) (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB) +#define RDMA_REGION_3__LENGTH_SET(x) (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK) +#define RDMA_REGION_3__INDI_MSB 1 +#define RDMA_REGION_3__INDI_LSB 1 +#define RDMA_REGION_3__INDI_MASK 0x00000002 +#define RDMA_REGION_3__INDI_GET(x) (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB) +#define RDMA_REGION_3__INDI_SET(x) (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK) +#define RDMA_REGION_3__NEXT_MSB 0 +#define RDMA_REGION_3__NEXT_LSB 0 +#define RDMA_REGION_3__NEXT_MASK 0x00000001 +#define RDMA_REGION_3__NEXT_GET(x) (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB) +#define RDMA_REGION_3__NEXT_SET(x) (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK) + +#define RDMA_REGION_4__ADDRESS 0x00000030 +#define RDMA_REGION_4__OFFSET 0x00000030 +#define RDMA_REGION_4__ADDR_MSB 31 +#define RDMA_REGION_4__ADDR_LSB 13 +#define RDMA_REGION_4__ADDR_MASK 0xffffe000 +#define RDMA_REGION_4__ADDR_GET(x) (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB) +#define RDMA_REGION_4__ADDR_SET(x) (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK) +#define RDMA_REGION_4__LENGTH_MSB 12 +#define RDMA_REGION_4__LENGTH_LSB 2 +#define RDMA_REGION_4__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_4__LENGTH_GET(x) (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB) +#define RDMA_REGION_4__LENGTH_SET(x) (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK) +#define RDMA_REGION_4__INDI_MSB 1 +#define RDMA_REGION_4__INDI_LSB 1 +#define RDMA_REGION_4__INDI_MASK 0x00000002 +#define RDMA_REGION_4__INDI_GET(x) (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB) +#define RDMA_REGION_4__INDI_SET(x) (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK) +#define RDMA_REGION_4__NEXT_MSB 0 +#define RDMA_REGION_4__NEXT_LSB 0 +#define RDMA_REGION_4__NEXT_MASK 0x00000001 +#define RDMA_REGION_4__NEXT_GET(x) (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB) +#define RDMA_REGION_4__NEXT_SET(x) (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK) + +#define RDMA_REGION_5__ADDRESS 0x00000034 +#define RDMA_REGION_5__OFFSET 0x00000034 +#define RDMA_REGION_5__ADDR_MSB 31 +#define RDMA_REGION_5__ADDR_LSB 13 +#define RDMA_REGION_5__ADDR_MASK 0xffffe000 +#define RDMA_REGION_5__ADDR_GET(x) (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB) +#define RDMA_REGION_5__ADDR_SET(x) (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK) +#define RDMA_REGION_5__LENGTH_MSB 12 +#define RDMA_REGION_5__LENGTH_LSB 2 +#define RDMA_REGION_5__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_5__LENGTH_GET(x) (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB) +#define RDMA_REGION_5__LENGTH_SET(x) (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK) +#define RDMA_REGION_5__INDI_MSB 1 +#define RDMA_REGION_5__INDI_LSB 1 +#define RDMA_REGION_5__INDI_MASK 0x00000002 +#define RDMA_REGION_5__INDI_GET(x) (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB) +#define RDMA_REGION_5__INDI_SET(x) (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK) +#define RDMA_REGION_5__NEXT_MSB 0 +#define RDMA_REGION_5__NEXT_LSB 0 +#define RDMA_REGION_5__NEXT_MASK 0x00000001 +#define RDMA_REGION_5__NEXT_GET(x) (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB) +#define RDMA_REGION_5__NEXT_SET(x) (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK) + +#define RDMA_REGION_6__ADDRESS 0x00000038 +#define RDMA_REGION_6__OFFSET 0x00000038 +#define RDMA_REGION_6__ADDR_MSB 31 +#define RDMA_REGION_6__ADDR_LSB 13 +#define RDMA_REGION_6__ADDR_MASK 0xffffe000 +#define RDMA_REGION_6__ADDR_GET(x) (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB) +#define RDMA_REGION_6__ADDR_SET(x) (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK) +#define RDMA_REGION_6__LENGTH_MSB 12 +#define RDMA_REGION_6__LENGTH_LSB 2 +#define RDMA_REGION_6__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_6__LENGTH_GET(x) (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB) +#define RDMA_REGION_6__LENGTH_SET(x) (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK) +#define RDMA_REGION_6__INDI_MSB 1 +#define RDMA_REGION_6__INDI_LSB 1 +#define RDMA_REGION_6__INDI_MASK 0x00000002 +#define RDMA_REGION_6__INDI_GET(x) (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB) +#define RDMA_REGION_6__INDI_SET(x) (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK) +#define RDMA_REGION_6__NEXT_MSB 0 +#define RDMA_REGION_6__NEXT_LSB 0 +#define RDMA_REGION_6__NEXT_MASK 0x00000001 +#define RDMA_REGION_6__NEXT_GET(x) (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB) +#define RDMA_REGION_6__NEXT_SET(x) (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK) + +#define RDMA_REGION_7__ADDRESS 0x0000003c +#define RDMA_REGION_7__OFFSET 0x0000003c +#define RDMA_REGION_7__ADDR_MSB 31 +#define RDMA_REGION_7__ADDR_LSB 13 +#define RDMA_REGION_7__ADDR_MASK 0xffffe000 +#define RDMA_REGION_7__ADDR_GET(x) (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB) +#define RDMA_REGION_7__ADDR_SET(x) (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK) +#define RDMA_REGION_7__LENGTH_MSB 12 +#define RDMA_REGION_7__LENGTH_LSB 2 +#define RDMA_REGION_7__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_7__LENGTH_GET(x) (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB) +#define RDMA_REGION_7__LENGTH_SET(x) (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK) +#define RDMA_REGION_7__INDI_MSB 1 +#define RDMA_REGION_7__INDI_LSB 1 +#define RDMA_REGION_7__INDI_MASK 0x00000002 +#define RDMA_REGION_7__INDI_GET(x) (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB) +#define RDMA_REGION_7__INDI_SET(x) (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK) +#define RDMA_REGION_7__NEXT_MSB 0 +#define RDMA_REGION_7__NEXT_LSB 0 +#define RDMA_REGION_7__NEXT_MASK 0x00000001 +#define RDMA_REGION_7__NEXT_GET(x) (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB) +#define RDMA_REGION_7__NEXT_SET(x) (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK) + +#define RDMA_REGION_8__ADDRESS 0x00000040 +#define RDMA_REGION_8__OFFSET 0x00000040 +#define RDMA_REGION_8__ADDR_MSB 31 +#define RDMA_REGION_8__ADDR_LSB 13 +#define RDMA_REGION_8__ADDR_MASK 0xffffe000 +#define RDMA_REGION_8__ADDR_GET(x) (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB) +#define RDMA_REGION_8__ADDR_SET(x) (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK) +#define RDMA_REGION_8__LENGTH_MSB 12 +#define RDMA_REGION_8__LENGTH_LSB 2 +#define RDMA_REGION_8__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_8__LENGTH_GET(x) (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB) +#define RDMA_REGION_8__LENGTH_SET(x) (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK) +#define RDMA_REGION_8__INDI_MSB 1 +#define RDMA_REGION_8__INDI_LSB 1 +#define RDMA_REGION_8__INDI_MASK 0x00000002 +#define RDMA_REGION_8__INDI_GET(x) (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB) +#define RDMA_REGION_8__INDI_SET(x) (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK) +#define RDMA_REGION_8__NEXT_MSB 0 +#define RDMA_REGION_8__NEXT_LSB 0 +#define RDMA_REGION_8__NEXT_MASK 0x00000001 +#define RDMA_REGION_8__NEXT_GET(x) (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB) +#define RDMA_REGION_8__NEXT_SET(x) (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK) + +#define RDMA_REGION_9__ADDRESS 0x00000044 +#define RDMA_REGION_9__OFFSET 0x00000044 +#define RDMA_REGION_9__ADDR_MSB 31 +#define RDMA_REGION_9__ADDR_LSB 13 +#define RDMA_REGION_9__ADDR_MASK 0xffffe000 +#define RDMA_REGION_9__ADDR_GET(x) (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB) +#define RDMA_REGION_9__ADDR_SET(x) (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK) +#define RDMA_REGION_9__LENGTH_MSB 12 +#define RDMA_REGION_9__LENGTH_LSB 2 +#define RDMA_REGION_9__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_9__LENGTH_GET(x) (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB) +#define RDMA_REGION_9__LENGTH_SET(x) (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK) +#define RDMA_REGION_9__INDI_MSB 1 +#define RDMA_REGION_9__INDI_LSB 1 +#define RDMA_REGION_9__INDI_MASK 0x00000002 +#define RDMA_REGION_9__INDI_GET(x) (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB) +#define RDMA_REGION_9__INDI_SET(x) (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK) +#define RDMA_REGION_9__NEXT_MSB 0 +#define RDMA_REGION_9__NEXT_LSB 0 +#define RDMA_REGION_9__NEXT_MASK 0x00000001 +#define RDMA_REGION_9__NEXT_GET(x) (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB) +#define RDMA_REGION_9__NEXT_SET(x) (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK) + +#define RDMA_REGION_10__ADDRESS 0x00000048 +#define RDMA_REGION_10__OFFSET 0x00000048 +#define RDMA_REGION_10__ADDR_MSB 31 +#define RDMA_REGION_10__ADDR_LSB 13 +#define RDMA_REGION_10__ADDR_MASK 0xffffe000 +#define RDMA_REGION_10__ADDR_GET(x) (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB) +#define RDMA_REGION_10__ADDR_SET(x) (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK) +#define RDMA_REGION_10__LENGTH_MSB 12 +#define RDMA_REGION_10__LENGTH_LSB 2 +#define RDMA_REGION_10__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_10__LENGTH_GET(x) (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB) +#define RDMA_REGION_10__LENGTH_SET(x) (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK) +#define RDMA_REGION_10__INDI_MSB 1 +#define RDMA_REGION_10__INDI_LSB 1 +#define RDMA_REGION_10__INDI_MASK 0x00000002 +#define RDMA_REGION_10__INDI_GET(x) (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB) +#define RDMA_REGION_10__INDI_SET(x) (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK) +#define RDMA_REGION_10__NEXT_MSB 0 +#define RDMA_REGION_10__NEXT_LSB 0 +#define RDMA_REGION_10__NEXT_MASK 0x00000001 +#define RDMA_REGION_10__NEXT_GET(x) (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB) +#define RDMA_REGION_10__NEXT_SET(x) (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK) + +#define RDMA_REGION_11__ADDRESS 0x0000004c +#define RDMA_REGION_11__OFFSET 0x0000004c +#define RDMA_REGION_11__ADDR_MSB 31 +#define RDMA_REGION_11__ADDR_LSB 13 +#define RDMA_REGION_11__ADDR_MASK 0xffffe000 +#define RDMA_REGION_11__ADDR_GET(x) (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB) +#define RDMA_REGION_11__ADDR_SET(x) (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK) +#define RDMA_REGION_11__LENGTH_MSB 12 +#define RDMA_REGION_11__LENGTH_LSB 2 +#define RDMA_REGION_11__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_11__LENGTH_GET(x) (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB) +#define RDMA_REGION_11__LENGTH_SET(x) (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK) +#define RDMA_REGION_11__INDI_MSB 1 +#define RDMA_REGION_11__INDI_LSB 1 +#define RDMA_REGION_11__INDI_MASK 0x00000002 +#define RDMA_REGION_11__INDI_GET(x) (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB) +#define RDMA_REGION_11__INDI_SET(x) (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK) +#define RDMA_REGION_11__NEXT_MSB 0 +#define RDMA_REGION_11__NEXT_LSB 0 +#define RDMA_REGION_11__NEXT_MASK 0x00000001 +#define RDMA_REGION_11__NEXT_GET(x) (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB) +#define RDMA_REGION_11__NEXT_SET(x) (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK) + +#define RDMA_REGION_12__ADDRESS 0x00000050 +#define RDMA_REGION_12__OFFSET 0x00000050 +#define RDMA_REGION_12__ADDR_MSB 31 +#define RDMA_REGION_12__ADDR_LSB 13 +#define RDMA_REGION_12__ADDR_MASK 0xffffe000 +#define RDMA_REGION_12__ADDR_GET(x) (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB) +#define RDMA_REGION_12__ADDR_SET(x) (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK) +#define RDMA_REGION_12__LENGTH_MSB 12 +#define RDMA_REGION_12__LENGTH_LSB 2 +#define RDMA_REGION_12__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_12__LENGTH_GET(x) (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB) +#define RDMA_REGION_12__LENGTH_SET(x) (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK) +#define RDMA_REGION_12__INDI_MSB 1 +#define RDMA_REGION_12__INDI_LSB 1 +#define RDMA_REGION_12__INDI_MASK 0x00000002 +#define RDMA_REGION_12__INDI_GET(x) (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB) +#define RDMA_REGION_12__INDI_SET(x) (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK) +#define RDMA_REGION_12__NEXT_MSB 0 +#define RDMA_REGION_12__NEXT_LSB 0 +#define RDMA_REGION_12__NEXT_MASK 0x00000001 +#define RDMA_REGION_12__NEXT_GET(x) (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB) +#define RDMA_REGION_12__NEXT_SET(x) (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK) + +#define RDMA_REGION_13__ADDRESS 0x00000054 +#define RDMA_REGION_13__OFFSET 0x00000054 +#define RDMA_REGION_13__ADDR_MSB 31 +#define RDMA_REGION_13__ADDR_LSB 13 +#define RDMA_REGION_13__ADDR_MASK 0xffffe000 +#define RDMA_REGION_13__ADDR_GET(x) (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB) +#define RDMA_REGION_13__ADDR_SET(x) (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK) +#define RDMA_REGION_13__LENGTH_MSB 12 +#define RDMA_REGION_13__LENGTH_LSB 2 +#define RDMA_REGION_13__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_13__LENGTH_GET(x) (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB) +#define RDMA_REGION_13__LENGTH_SET(x) (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK) +#define RDMA_REGION_13__INDI_MSB 1 +#define RDMA_REGION_13__INDI_LSB 1 +#define RDMA_REGION_13__INDI_MASK 0x00000002 +#define RDMA_REGION_13__INDI_GET(x) (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB) +#define RDMA_REGION_13__INDI_SET(x) (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK) +#define RDMA_REGION_13__NEXT_MSB 0 +#define RDMA_REGION_13__NEXT_LSB 0 +#define RDMA_REGION_13__NEXT_MASK 0x00000001 +#define RDMA_REGION_13__NEXT_GET(x) (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB) +#define RDMA_REGION_13__NEXT_SET(x) (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK) + +#define RDMA_REGION_14__ADDRESS 0x00000058 +#define RDMA_REGION_14__OFFSET 0x00000058 +#define RDMA_REGION_14__ADDR_MSB 31 +#define RDMA_REGION_14__ADDR_LSB 13 +#define RDMA_REGION_14__ADDR_MASK 0xffffe000 +#define RDMA_REGION_14__ADDR_GET(x) (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB) +#define RDMA_REGION_14__ADDR_SET(x) (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK) +#define RDMA_REGION_14__LENGTH_MSB 12 +#define RDMA_REGION_14__LENGTH_LSB 2 +#define RDMA_REGION_14__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_14__LENGTH_GET(x) (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB) +#define RDMA_REGION_14__LENGTH_SET(x) (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK) +#define RDMA_REGION_14__INDI_MSB 1 +#define RDMA_REGION_14__INDI_LSB 1 +#define RDMA_REGION_14__INDI_MASK 0x00000002 +#define RDMA_REGION_14__INDI_GET(x) (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB) +#define RDMA_REGION_14__INDI_SET(x) (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK) +#define RDMA_REGION_14__NEXT_MSB 0 +#define RDMA_REGION_14__NEXT_LSB 0 +#define RDMA_REGION_14__NEXT_MASK 0x00000001 +#define RDMA_REGION_14__NEXT_GET(x) (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB) +#define RDMA_REGION_14__NEXT_SET(x) (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK) + +#define RDMA_REGION_15__ADDRESS 0x0000005c +#define RDMA_REGION_15__OFFSET 0x0000005c +#define RDMA_REGION_15__ADDR_MSB 31 +#define RDMA_REGION_15__ADDR_LSB 13 +#define RDMA_REGION_15__ADDR_MASK 0xffffe000 +#define RDMA_REGION_15__ADDR_GET(x) (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB) +#define RDMA_REGION_15__ADDR_SET(x) (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK) +#define RDMA_REGION_15__LENGTH_MSB 12 +#define RDMA_REGION_15__LENGTH_LSB 2 +#define RDMA_REGION_15__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_15__LENGTH_GET(x) (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB) +#define RDMA_REGION_15__LENGTH_SET(x) (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK) +#define RDMA_REGION_15__INDI_MSB 1 +#define RDMA_REGION_15__INDI_LSB 1 +#define RDMA_REGION_15__INDI_MASK 0x00000002 +#define RDMA_REGION_15__INDI_GET(x) (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB) +#define RDMA_REGION_15__INDI_SET(x) (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK) +#define RDMA_REGION_15__NEXT_MSB 0 +#define RDMA_REGION_15__NEXT_LSB 0 +#define RDMA_REGION_15__NEXT_MASK 0x00000001 +#define RDMA_REGION_15__NEXT_GET(x) (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB) +#define RDMA_REGION_15__NEXT_SET(x) (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK) + +#define DMA_STATUS_ADDRESS 0x00000060 +#define DMA_STATUS_OFFSET 0x00000060 +#define DMA_STATUS_ERROR_CODE_MSB 14 +#define DMA_STATUS_ERROR_CODE_LSB 4 +#define DMA_STATUS_ERROR_CODE_MASK 0x00007ff0 +#define DMA_STATUS_ERROR_CODE_GET(x) (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB) +#define DMA_STATUS_ERROR_CODE_SET(x) (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK) +#define DMA_STATUS_ERROR_MSB 3 +#define DMA_STATUS_ERROR_LSB 3 +#define DMA_STATUS_ERROR_MASK 0x00000008 +#define DMA_STATUS_ERROR_GET(x) (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB) +#define DMA_STATUS_ERROR_SET(x) (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK) +#define DMA_STATUS_DONE_MSB 2 +#define DMA_STATUS_DONE_LSB 2 +#define DMA_STATUS_DONE_MASK 0x00000004 +#define DMA_STATUS_DONE_GET(x) (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB) +#define DMA_STATUS_DONE_SET(x) (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK) +#define DMA_STATUS_STOPPED_MSB 1 +#define DMA_STATUS_STOPPED_LSB 1 +#define DMA_STATUS_STOPPED_MASK 0x00000002 +#define DMA_STATUS_STOPPED_GET(x) (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB) +#define DMA_STATUS_STOPPED_SET(x) (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK) +#define DMA_STATUS_RUNNING_MSB 0 +#define DMA_STATUS_RUNNING_LSB 0 +#define DMA_STATUS_RUNNING_MASK 0x00000001 +#define DMA_STATUS_RUNNING_GET(x) (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB) +#define DMA_STATUS_RUNNING_SET(x) (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK) + +#define DMA_INT_EN_ADDRESS 0x00000064 +#define DMA_INT_EN_OFFSET 0x00000064 +#define DMA_INT_EN_ERROR_ENA_MSB 3 +#define DMA_INT_EN_ERROR_ENA_LSB 3 +#define DMA_INT_EN_ERROR_ENA_MASK 0x00000008 +#define DMA_INT_EN_ERROR_ENA_GET(x) (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB) +#define DMA_INT_EN_ERROR_ENA_SET(x) (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK) +#define DMA_INT_EN_DONE_ENA_MSB 2 +#define DMA_INT_EN_DONE_ENA_LSB 2 +#define DMA_INT_EN_DONE_ENA_MASK 0x00000004 +#define DMA_INT_EN_DONE_ENA_GET(x) (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB) +#define DMA_INT_EN_DONE_ENA_SET(x) (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK) +#define DMA_INT_EN_STOPPED_ENA_MSB 1 +#define DMA_INT_EN_STOPPED_ENA_LSB 1 +#define DMA_INT_EN_STOPPED_ENA_MASK 0x00000002 +#define DMA_INT_EN_STOPPED_ENA_GET(x) (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB) +#define DMA_INT_EN_STOPPED_ENA_SET(x) (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rdma_reg_reg_s { + volatile unsigned int dma_config; + volatile unsigned int dma_control; + volatile unsigned int dma_src; + volatile unsigned int dma_dest; + volatile unsigned int dma_length; + volatile unsigned int vmc_base; + volatile unsigned int indirect_reg; + volatile unsigned int indirect_return; + volatile unsigned int rdma_region_0_; + volatile unsigned int rdma_region_1_; + volatile unsigned int rdma_region_2_; + volatile unsigned int rdma_region_3_; + volatile unsigned int rdma_region_4_; + volatile unsigned int rdma_region_5_; + volatile unsigned int rdma_region_6_; + volatile unsigned int rdma_region_7_; + volatile unsigned int rdma_region_8_; + volatile unsigned int rdma_region_9_; + volatile unsigned int rdma_region_10_; + volatile unsigned int rdma_region_11_; + volatile unsigned int rdma_region_12_; + volatile unsigned int rdma_region_13_; + volatile unsigned int rdma_region_14_; + volatile unsigned int rdma_region_15_; + volatile unsigned int dma_status; + volatile unsigned int dma_int_en; +} rdma_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RDMA_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h new file mode 100644 index 000000000000..0855de5f1400 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h @@ -0,0 +1,975 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "rtc_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS +#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET +#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB +#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB +#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK +#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) +#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) +#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB +#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB +#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK +#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) +#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) +#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB +#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB +#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK +#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) +#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) +#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB +#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB +#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB +#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB +#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) +#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB +#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB +#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK +#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x) +#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x) +#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB +#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB +#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK +#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x) +#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x) +#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB +#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB +#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK +#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x) +#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x) +#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB +#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB +#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK +#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) +#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB +#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB +#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK +#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) +#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB +#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB +#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK +#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) +#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB +#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB +#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK +#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x) +#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x) +#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB +#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB +#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK +#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x) +#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x) +#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB +#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB +#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK +#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x) +#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x) +#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS +#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET +#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB +#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB +#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK +#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x) +#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x) +#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS +#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET +#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB +#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB +#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK +#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x) +#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x) +#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS +#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET +#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB +#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB +#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK +#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x) +#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x) +#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS +#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET +#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB +#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB +#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK +#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x) +#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x) +#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB +#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB +#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK +#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x) +#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x) +#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB +#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB +#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK +#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x) +#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x) +#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS +#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET +#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB +#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB +#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) +#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB +#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB +#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) +#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB +#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB +#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK +#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x) +#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x) +#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB +#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB +#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK +#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x) +#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x) +#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB +#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB +#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK +#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x) +#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x) +#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB +#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB +#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK +#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x) +#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x) +#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB +#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB +#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK +#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x) +#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x) +#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS +#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET +#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB +#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB +#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK +#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x) +#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x) +#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS +#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET +#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB +#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB +#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK +#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x) +#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x) +#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS +#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET +#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB +#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB +#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK +#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x) +#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x) +#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS +#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET +#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB +#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB +#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK +#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x) +#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x) +#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS +#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET +#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB +#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB +#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK +#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) +#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) +#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB +#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB +#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK +#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) +#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) +#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS +#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET +#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB +#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB +#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK +#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x) +#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x) +#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS +#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET +#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB +#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB +#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK +#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x) +#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x) +#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS +#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET +#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB +#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB +#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK +#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x) +#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x) +#define WDT_ADDRESS WLAN_WDT_ADDRESS +#define WDT_OFFSET WLAN_WDT_OFFSET +#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB +#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB +#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK +#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x) +#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x) +#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS +#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET +#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB +#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB +#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK +#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x) +#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x) +#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS +#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET +#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB +#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB +#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK +#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x) +#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x) +#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS +#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET +#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB +#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB +#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK +#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x) +#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x) +#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB +#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB +#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK +#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x) +#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x) +#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB +#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB +#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK +#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) +#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) +#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB +#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB +#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK +#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x) +#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x) +#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB +#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB +#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK +#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x) +#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x) +#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB +#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB +#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK +#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x) +#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x) +#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB +#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB +#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK +#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x) +#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x) +#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB +#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB +#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK +#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x) +#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x) +#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB +#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB +#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK +#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x) +#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x) +#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB +#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB +#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK +#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x) +#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x) +#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB +#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB +#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK +#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x) +#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x) +#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB +#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB +#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK +#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x) +#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x) +#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB +#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB +#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK +#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x) +#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x) +#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB +#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB +#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK +#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x) +#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x) +#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB +#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB +#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK +#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x) +#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x) +#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB +#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB +#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK +#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x) +#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x) +#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB +#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB +#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK +#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x) +#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x) +#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB +#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB +#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK +#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x) +#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x) +#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB +#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB +#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK +#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x) +#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x) +#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB +#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB +#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK +#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x) +#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x) +#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB +#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB +#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK +#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x) +#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x) +#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB +#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB +#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK +#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x) +#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x) +#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS +#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET +#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB +#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB +#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK +#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x) +#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x) +#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS +#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET +#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB +#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB +#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK +#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x) +#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x) +#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS +#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET +#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB +#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB +#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK +#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB +#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB +#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK +#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x) +#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x) +#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS +#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET +#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB +#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB +#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) +#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS +#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET +#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB +#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB +#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK +#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x) +#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x) +#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS +#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET +#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB +#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB +#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK +#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x) +#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x) +#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS +#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET +#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB +#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB +#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK +#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB +#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB +#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK +#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x) +#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x) +#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS +#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET +#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB +#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB +#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) +#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS +#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET +#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB +#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB +#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK +#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x) +#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x) +#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS +#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET +#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB +#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB +#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK +#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x) +#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x) +#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS +#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET +#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB +#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB +#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK +#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB +#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB +#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK +#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x) +#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x) +#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS +#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET +#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB +#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB +#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) +#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS +#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET +#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB +#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB +#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK +#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x) +#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x) +#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS +#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET +#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB +#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB +#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK +#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x) +#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x) +#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS +#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET +#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB +#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB +#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK +#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB +#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB +#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK +#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x) +#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x) +#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS +#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET +#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB +#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB +#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) +#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS +#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET +#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB +#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB +#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK +#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x) +#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x) +#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS +#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET +#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB +#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB +#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK +#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x) +#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x) +#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS +#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET +#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB +#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB +#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK +#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x) +#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x) +#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS +#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET +#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB +#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB +#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK +#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) +#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) +#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB +#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB +#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK +#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x) +#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) +#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB +#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB +#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK +#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x) +#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x) +#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS +#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET +#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB +#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB +#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK +#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) +#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS +#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET +#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB +#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB +#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK +#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x) +#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x) +#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB +#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB +#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK +#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x) +#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x) +#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB +#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB +#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK +#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) +#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) +#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS +#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET +#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB +#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB +#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK +#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x) +#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x) +#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB +#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB +#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK +#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x) +#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x) +#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB +#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB +#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK +#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x) +#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x) +#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB +#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB +#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK +#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x) +#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x) +#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS +#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET +#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB +#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB +#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK +#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x) +#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x) +#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB +#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB +#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK +#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x) +#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x) +#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB +#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB +#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK +#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x) +#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x) +#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS +#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET +#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB +#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB +#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK +#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) +#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) +#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB +#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB +#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK +#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x) +#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x) +#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB +#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB +#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK +#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x) +#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x) +#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB +#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB +#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK +#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x) +#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x) +#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS +#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET +#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB +#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB +#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK +#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x) +#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x) +#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB +#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB +#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK +#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x) +#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x) +#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB +#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB +#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK +#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) +#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) +#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS +#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET +#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB +#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB +#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK +#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x) +#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x) +#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB +#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB +#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK +#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x) +#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x) +#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB +#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB +#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK +#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x) +#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x) +#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS +#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET +#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB +#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB +#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK +#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x) +#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x) +#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB +#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB +#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK +#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) +#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB +#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB +#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK +#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x) +#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x) +#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS +#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET +#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB +#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB +#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK +#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) +#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) +#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB +#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB +#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) +#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS +#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET +#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB +#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB +#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK +#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x) +#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x) +#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS +#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET +#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB +#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB +#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK +#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x) +#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x) +#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS +#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET +#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB +#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB +#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK +#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) +#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) +#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB +#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB +#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK +#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x) +#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x) +#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB +#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB +#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK +#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) +#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) +#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB +#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB +#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK +#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x) +#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x) +#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB +#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB +#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK +#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x) +#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x) +#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS +#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET +#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB +#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB +#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK +#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x) +#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x) +#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB +#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB +#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK +#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x) +#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x) +#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB +#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB +#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK +#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x) +#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x) +#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB +#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB +#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK +#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x) +#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x) +#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS +#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET +#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB +#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB +#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) +#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS +#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET +#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB +#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB +#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK +#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x) +#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x) +#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS +#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET +#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB +#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB +#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK +#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x) +#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x) +#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS +#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) +#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS +#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET +#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB +#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB +#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK +#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x) +#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x) +#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB +#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB +#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK +#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x) +#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x) +#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS +#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) +#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS +#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET +#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB +#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB +#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK +#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) +#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) +#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB +#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB +#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) +#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS +#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET +#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB +#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB +#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK +#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x) +#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x) +#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB +#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB +#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK +#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x) +#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x) +#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB +#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB +#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK +#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x) +#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x) +#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS +#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) +#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB +#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB +#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK +#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x) +#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x) +#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB +#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB +#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK +#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) +#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) +#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS +#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) +#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB +#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB +#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK +#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x) +#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x) +#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB +#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB +#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK +#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) +#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) +#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB +#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB +#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK +#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) +#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) +#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB +#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB +#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK +#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x) +#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x) +#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB +#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB +#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK +#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) +#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) +#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB +#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB +#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK +#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) +#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) +#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB +#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB +#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK +#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) +#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB +#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB +#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK +#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x) +#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x) +#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB +#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB +#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK +#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x) +#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x) +#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB +#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB +#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK +#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x) +#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x) +#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB +#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB +#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK +#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x) +#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x) +#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB +#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB +#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK +#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x) +#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x) +#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS +#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET +#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB +#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB +#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK +#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x) +#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x) +#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS +#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h new file mode 100644 index 000000000000..abf872650054 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h @@ -0,0 +1,2065 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RTC_WLAN_REG_REG_H_ +#define _RTC_WLAN_REG_REG_H_ + +#define WLAN_RESET_CONTROL_ADDRESS 0x00000000 +#define WLAN_RESET_CONTROL_OFFSET 0x00000000 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB 14 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB 14 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK 0x00004000 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) >> WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) +#define WLAN_RESET_CONTROL_BB_COLD_RST_MSB 13 +#define WLAN_RESET_CONTROL_BB_COLD_RST_LSB 13 +#define WLAN_RESET_CONTROL_BB_COLD_RST_MASK 0x00002000 +#define WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) >> WLAN_RESET_CONTROL_BB_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_COLD_RST_LSB) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_BB_WARM_RST_MSB 12 +#define WLAN_RESET_CONTROL_BB_WARM_RST_LSB 12 +#define WLAN_RESET_CONTROL_BB_WARM_RST_MASK 0x00001000 +#define WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) >> WLAN_RESET_CONTROL_BB_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_WARM_RST_LSB) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) >> WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) >> WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define WLAN_RESET_CONTROL_RST_OUT_MSB 9 +#define WLAN_RESET_CONTROL_RST_OUT_LSB 9 +#define WLAN_RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define WLAN_RESET_CONTROL_RST_OUT_GET(x) (((x) & WLAN_RESET_CONTROL_RST_OUT_MASK) >> WLAN_RESET_CONTROL_RST_OUT_LSB) +#define WLAN_RESET_CONTROL_RST_OUT_SET(x) (((x) << WLAN_RESET_CONTROL_RST_OUT_LSB) & WLAN_RESET_CONTROL_RST_OUT_MASK) +#define WLAN_RESET_CONTROL_COLD_RST_MSB 8 +#define WLAN_RESET_CONTROL_COLD_RST_LSB 8 +#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define WLAN_RESET_CONTROL_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_COLD_RST_MASK) >> WLAN_RESET_CONTROL_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_COLD_RST_LSB) & WLAN_RESET_CONTROL_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_WARM_RST_MSB 7 +#define WLAN_RESET_CONTROL_WARM_RST_LSB 7 +#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define WLAN_RESET_CONTROL_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_WARM_RST_MASK) >> WLAN_RESET_CONTROL_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_WARM_RST_LSB) & WLAN_RESET_CONTROL_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) >> WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) >> WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) >> WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_MBOX_RST_MSB 2 +#define WLAN_RESET_CONTROL_MBOX_RST_LSB 2 +#define WLAN_RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define WLAN_RESET_CONTROL_MBOX_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MBOX_RST_MASK) >> WLAN_RESET_CONTROL_MBOX_RST_LSB) +#define WLAN_RESET_CONTROL_MBOX_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MBOX_RST_LSB) & WLAN_RESET_CONTROL_MBOX_RST_MASK) +#define WLAN_RESET_CONTROL_UART_RST_MSB 1 +#define WLAN_RESET_CONTROL_UART_RST_LSB 1 +#define WLAN_RESET_CONTROL_UART_RST_MASK 0x00000002 +#define WLAN_RESET_CONTROL_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_UART_RST_MASK) >> WLAN_RESET_CONTROL_UART_RST_LSB) +#define WLAN_RESET_CONTROL_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_UART_RST_LSB) & WLAN_RESET_CONTROL_UART_RST_MASK) +#define WLAN_RESET_CONTROL_SI0_RST_MSB 0 +#define WLAN_RESET_CONTROL_SI0_RST_LSB 0 +#define WLAN_RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define WLAN_RESET_CONTROL_SI0_RST_GET(x) (((x) & WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB) +#define WLAN_RESET_CONTROL_SI0_RST_SET(x) (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK) + +#define WLAN_XTAL_CONTROL_ADDRESS 0x00000004 +#define WLAN_XTAL_CONTROL_OFFSET 0x00000004 +#define WLAN_XTAL_CONTROL_TCXO_MSB 0 +#define WLAN_XTAL_CONTROL_TCXO_LSB 0 +#define WLAN_XTAL_CONTROL_TCXO_MASK 0x00000001 +#define WLAN_XTAL_CONTROL_TCXO_GET(x) (((x) & WLAN_XTAL_CONTROL_TCXO_MASK) >> WLAN_XTAL_CONTROL_TCXO_LSB) +#define WLAN_XTAL_CONTROL_TCXO_SET(x) (((x) << WLAN_XTAL_CONTROL_TCXO_LSB) & WLAN_XTAL_CONTROL_TCXO_MASK) + +#define WLAN_TCXO_DETECT_ADDRESS 0x00000008 +#define WLAN_TCXO_DETECT_OFFSET 0x00000008 +#define WLAN_TCXO_DETECT_PRESENT_MSB 0 +#define WLAN_TCXO_DETECT_PRESENT_LSB 0 +#define WLAN_TCXO_DETECT_PRESENT_MASK 0x00000001 +#define WLAN_TCXO_DETECT_PRESENT_GET(x) (((x) & WLAN_TCXO_DETECT_PRESENT_MASK) >> WLAN_TCXO_DETECT_PRESENT_LSB) +#define WLAN_TCXO_DETECT_PRESENT_SET(x) (((x) << WLAN_TCXO_DETECT_PRESENT_LSB) & WLAN_TCXO_DETECT_PRESENT_MASK) + +#define WLAN_XTAL_TEST_ADDRESS 0x0000000c +#define WLAN_XTAL_TEST_OFFSET 0x0000000c +#define WLAN_XTAL_TEST_NOTCXODET_MSB 0 +#define WLAN_XTAL_TEST_NOTCXODET_LSB 0 +#define WLAN_XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define WLAN_XTAL_TEST_NOTCXODET_GET(x) (((x) & WLAN_XTAL_TEST_NOTCXODET_MASK) >> WLAN_XTAL_TEST_NOTCXODET_LSB) +#define WLAN_XTAL_TEST_NOTCXODET_SET(x) (((x) << WLAN_XTAL_TEST_NOTCXODET_LSB) & WLAN_XTAL_TEST_NOTCXODET_MASK) + +#define WLAN_QUADRATURE_ADDRESS 0x00000010 +#define WLAN_QUADRATURE_OFFSET 0x00000010 +#define WLAN_QUADRATURE_ADC_MSB 7 +#define WLAN_QUADRATURE_ADC_LSB 4 +#define WLAN_QUADRATURE_ADC_MASK 0x000000f0 +#define WLAN_QUADRATURE_ADC_GET(x) (((x) & WLAN_QUADRATURE_ADC_MASK) >> WLAN_QUADRATURE_ADC_LSB) +#define WLAN_QUADRATURE_ADC_SET(x) (((x) << WLAN_QUADRATURE_ADC_LSB) & WLAN_QUADRATURE_ADC_MASK) +#define WLAN_QUADRATURE_SEL_MSB 2 +#define WLAN_QUADRATURE_SEL_LSB 2 +#define WLAN_QUADRATURE_SEL_MASK 0x00000004 +#define WLAN_QUADRATURE_SEL_GET(x) (((x) & WLAN_QUADRATURE_SEL_MASK) >> WLAN_QUADRATURE_SEL_LSB) +#define WLAN_QUADRATURE_SEL_SET(x) (((x) << WLAN_QUADRATURE_SEL_LSB) & WLAN_QUADRATURE_SEL_MASK) +#define WLAN_QUADRATURE_DAC_MSB 1 +#define WLAN_QUADRATURE_DAC_LSB 0 +#define WLAN_QUADRATURE_DAC_MASK 0x00000003 +#define WLAN_QUADRATURE_DAC_GET(x) (((x) & WLAN_QUADRATURE_DAC_MASK) >> WLAN_QUADRATURE_DAC_LSB) +#define WLAN_QUADRATURE_DAC_SET(x) (((x) << WLAN_QUADRATURE_DAC_LSB) & WLAN_QUADRATURE_DAC_MASK) + +#define WLAN_PLL_CONTROL_ADDRESS 0x00000014 +#define WLAN_PLL_CONTROL_OFFSET 0x00000014 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) >> WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) >> WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) +#define WLAN_PLL_CONTROL_NOPWD_MSB 18 +#define WLAN_PLL_CONTROL_NOPWD_LSB 18 +#define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 +#define WLAN_PLL_CONTROL_NOPWD_GET(x) (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) +#define WLAN_PLL_CONTROL_NOPWD_SET(x) (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) +#define WLAN_PLL_CONTROL_UPDATING_MSB 17 +#define WLAN_PLL_CONTROL_UPDATING_LSB 17 +#define WLAN_PLL_CONTROL_UPDATING_MASK 0x00020000 +#define WLAN_PLL_CONTROL_UPDATING_GET(x) (((x) & WLAN_PLL_CONTROL_UPDATING_MASK) >> WLAN_PLL_CONTROL_UPDATING_LSB) +#define WLAN_PLL_CONTROL_UPDATING_SET(x) (((x) << WLAN_PLL_CONTROL_UPDATING_LSB) & WLAN_PLL_CONTROL_UPDATING_MASK) +#define WLAN_PLL_CONTROL_BYPASS_MSB 16 +#define WLAN_PLL_CONTROL_BYPASS_LSB 16 +#define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 +#define WLAN_PLL_CONTROL_BYPASS_GET(x) (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) +#define WLAN_PLL_CONTROL_BYPASS_SET(x) (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) +#define WLAN_PLL_CONTROL_REFDIV_MSB 15 +#define WLAN_PLL_CONTROL_REFDIV_LSB 12 +#define WLAN_PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define WLAN_PLL_CONTROL_REFDIV_GET(x) (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) +#define WLAN_PLL_CONTROL_REFDIV_SET(x) (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) +#define WLAN_PLL_CONTROL_DIV_MSB 9 +#define WLAN_PLL_CONTROL_DIV_LSB 0 +#define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff +#define WLAN_PLL_CONTROL_DIV_GET(x) (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) +#define WLAN_PLL_CONTROL_DIV_SET(x) (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) + +#define WLAN_PLL_SETTLE_ADDRESS 0x00000018 +#define WLAN_PLL_SETTLE_OFFSET 0x00000018 +#define WLAN_PLL_SETTLE_TIME_MSB 11 +#define WLAN_PLL_SETTLE_TIME_LSB 0 +#define WLAN_PLL_SETTLE_TIME_MASK 0x00000fff +#define WLAN_PLL_SETTLE_TIME_GET(x) (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) +#define WLAN_PLL_SETTLE_TIME_SET(x) (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) + +#define WLAN_XTAL_SETTLE_ADDRESS 0x0000001c +#define WLAN_XTAL_SETTLE_OFFSET 0x0000001c +#define WLAN_XTAL_SETTLE_TIME_MSB 7 +#define WLAN_XTAL_SETTLE_TIME_LSB 0 +#define WLAN_XTAL_SETTLE_TIME_MASK 0x000000ff +#define WLAN_XTAL_SETTLE_TIME_GET(x) (((x) & WLAN_XTAL_SETTLE_TIME_MASK) >> WLAN_XTAL_SETTLE_TIME_LSB) +#define WLAN_XTAL_SETTLE_TIME_SET(x) (((x) << WLAN_XTAL_SETTLE_TIME_LSB) & WLAN_XTAL_SETTLE_TIME_MASK) + +#define WLAN_CPU_CLOCK_ADDRESS 0x00000020 +#define WLAN_CPU_CLOCK_OFFSET 0x00000020 +#define WLAN_CPU_CLOCK_STANDARD_MSB 1 +#define WLAN_CPU_CLOCK_STANDARD_LSB 0 +#define WLAN_CPU_CLOCK_STANDARD_MASK 0x00000003 +#define WLAN_CPU_CLOCK_STANDARD_GET(x) (((x) & WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB) +#define WLAN_CPU_CLOCK_STANDARD_SET(x) (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK) + +#define WLAN_CLOCK_OUT_ADDRESS 0x00000024 +#define WLAN_CLOCK_OUT_OFFSET 0x00000024 +#define WLAN_CLOCK_OUT_SELECT_MSB 3 +#define WLAN_CLOCK_OUT_SELECT_LSB 0 +#define WLAN_CLOCK_OUT_SELECT_MASK 0x0000000f +#define WLAN_CLOCK_OUT_SELECT_GET(x) (((x) & WLAN_CLOCK_OUT_SELECT_MASK) >> WLAN_CLOCK_OUT_SELECT_LSB) +#define WLAN_CLOCK_OUT_SELECT_SET(x) (((x) << WLAN_CLOCK_OUT_SELECT_LSB) & WLAN_CLOCK_OUT_SELECT_MASK) + +#define WLAN_CLOCK_CONTROL_ADDRESS 0x00000028 +#define WLAN_CLOCK_CONTROL_OFFSET 0x00000028 +#define WLAN_CLOCK_CONTROL_LF_CLK32_MSB 2 +#define WLAN_CLOCK_CONTROL_LF_CLK32_LSB 2 +#define WLAN_CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) >> WLAN_CLOCK_CONTROL_LF_CLK32_LSB) +#define WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << WLAN_CLOCK_CONTROL_LF_CLK32_LSB) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) +#define WLAN_CLOCK_CONTROL_SI0_CLK_MSB 0 +#define WLAN_CLOCK_CONTROL_SI0_CLK_LSB 0 +#define WLAN_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB) +#define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) + +#define WLAN_BIAS_OVERRIDE_ADDRESS 0x0000002c +#define WLAN_BIAS_OVERRIDE_OFFSET 0x0000002c +#define WLAN_BIAS_OVERRIDE_ON_MSB 0 +#define WLAN_BIAS_OVERRIDE_ON_LSB 0 +#define WLAN_BIAS_OVERRIDE_ON_MASK 0x00000001 +#define WLAN_BIAS_OVERRIDE_ON_GET(x) (((x) & WLAN_BIAS_OVERRIDE_ON_MASK) >> WLAN_BIAS_OVERRIDE_ON_LSB) +#define WLAN_BIAS_OVERRIDE_ON_SET(x) (((x) << WLAN_BIAS_OVERRIDE_ON_LSB) & WLAN_BIAS_OVERRIDE_ON_MASK) + +#define WLAN_WDT_CONTROL_ADDRESS 0x00000030 +#define WLAN_WDT_CONTROL_OFFSET 0x00000030 +#define WLAN_WDT_CONTROL_ACTION_MSB 2 +#define WLAN_WDT_CONTROL_ACTION_LSB 0 +#define WLAN_WDT_CONTROL_ACTION_MASK 0x00000007 +#define WLAN_WDT_CONTROL_ACTION_GET(x) (((x) & WLAN_WDT_CONTROL_ACTION_MASK) >> WLAN_WDT_CONTROL_ACTION_LSB) +#define WLAN_WDT_CONTROL_ACTION_SET(x) (((x) << WLAN_WDT_CONTROL_ACTION_LSB) & WLAN_WDT_CONTROL_ACTION_MASK) + +#define WLAN_WDT_STATUS_ADDRESS 0x00000034 +#define WLAN_WDT_STATUS_OFFSET 0x00000034 +#define WLAN_WDT_STATUS_INTERRUPT_MSB 0 +#define WLAN_WDT_STATUS_INTERRUPT_LSB 0 +#define WLAN_WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_WDT_STATUS_INTERRUPT_GET(x) (((x) & WLAN_WDT_STATUS_INTERRUPT_MASK) >> WLAN_WDT_STATUS_INTERRUPT_LSB) +#define WLAN_WDT_STATUS_INTERRUPT_SET(x) (((x) << WLAN_WDT_STATUS_INTERRUPT_LSB) & WLAN_WDT_STATUS_INTERRUPT_MASK) + +#define WLAN_WDT_ADDRESS 0x00000038 +#define WLAN_WDT_OFFSET 0x00000038 +#define WLAN_WDT_TARGET_MSB 21 +#define WLAN_WDT_TARGET_LSB 0 +#define WLAN_WDT_TARGET_MASK 0x003fffff +#define WLAN_WDT_TARGET_GET(x) (((x) & WLAN_WDT_TARGET_MASK) >> WLAN_WDT_TARGET_LSB) +#define WLAN_WDT_TARGET_SET(x) (((x) << WLAN_WDT_TARGET_LSB) & WLAN_WDT_TARGET_MASK) + +#define WLAN_WDT_COUNT_ADDRESS 0x0000003c +#define WLAN_WDT_COUNT_OFFSET 0x0000003c +#define WLAN_WDT_COUNT_VALUE_MSB 21 +#define WLAN_WDT_COUNT_VALUE_LSB 0 +#define WLAN_WDT_COUNT_VALUE_MASK 0x003fffff +#define WLAN_WDT_COUNT_VALUE_GET(x) (((x) & WLAN_WDT_COUNT_VALUE_MASK) >> WLAN_WDT_COUNT_VALUE_LSB) +#define WLAN_WDT_COUNT_VALUE_SET(x) (((x) << WLAN_WDT_COUNT_VALUE_LSB) & WLAN_WDT_COUNT_VALUE_MASK) + +#define WLAN_WDT_RESET_ADDRESS 0x00000040 +#define WLAN_WDT_RESET_OFFSET 0x00000040 +#define WLAN_WDT_RESET_VALUE_MSB 0 +#define WLAN_WDT_RESET_VALUE_LSB 0 +#define WLAN_WDT_RESET_VALUE_MASK 0x00000001 +#define WLAN_WDT_RESET_VALUE_GET(x) (((x) & WLAN_WDT_RESET_VALUE_MASK) >> WLAN_WDT_RESET_VALUE_LSB) +#define WLAN_WDT_RESET_VALUE_SET(x) (((x) << WLAN_WDT_RESET_VALUE_LSB) & WLAN_WDT_RESET_VALUE_MASK) + +#define WLAN_INT_STATUS_ADDRESS 0x00000044 +#define WLAN_INT_STATUS_OFFSET 0x00000044 +#define WLAN_INT_STATUS_HCI_UART_MSB 21 +#define WLAN_INT_STATUS_HCI_UART_LSB 21 +#define WLAN_INT_STATUS_HCI_UART_MASK 0x00200000 +#define WLAN_INT_STATUS_HCI_UART_GET(x) (((x) & WLAN_INT_STATUS_HCI_UART_MASK) >> WLAN_INT_STATUS_HCI_UART_LSB) +#define WLAN_INT_STATUS_HCI_UART_SET(x) (((x) << WLAN_INT_STATUS_HCI_UART_LSB) & WLAN_INT_STATUS_HCI_UART_MASK) +#define WLAN_INT_STATUS_THERM_MSB 20 +#define WLAN_INT_STATUS_THERM_LSB 20 +#define WLAN_INT_STATUS_THERM_MASK 0x00100000 +#define WLAN_INT_STATUS_THERM_GET(x) (((x) & WLAN_INT_STATUS_THERM_MASK) >> WLAN_INT_STATUS_THERM_LSB) +#define WLAN_INT_STATUS_THERM_SET(x) (((x) << WLAN_INT_STATUS_THERM_LSB) & WLAN_INT_STATUS_THERM_MASK) +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB 19 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB 19 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK 0x00080000 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) (((x) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) >> WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) (((x) << WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) +#define WLAN_INT_STATUS_UART_MBOX_MSB 18 +#define WLAN_INT_STATUS_UART_MBOX_LSB 18 +#define WLAN_INT_STATUS_UART_MBOX_MASK 0x00040000 +#define WLAN_INT_STATUS_UART_MBOX_GET(x) (((x) & WLAN_INT_STATUS_UART_MBOX_MASK) >> WLAN_INT_STATUS_UART_MBOX_LSB) +#define WLAN_INT_STATUS_UART_MBOX_SET(x) (((x) << WLAN_INT_STATUS_UART_MBOX_LSB) & WLAN_INT_STATUS_UART_MBOX_MASK) +#define WLAN_INT_STATUS_GENERIC_MBOX_MSB 17 +#define WLAN_INT_STATUS_GENERIC_MBOX_LSB 17 +#define WLAN_INT_STATUS_GENERIC_MBOX_MASK 0x00020000 +#define WLAN_INT_STATUS_GENERIC_MBOX_GET(x) (((x) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) >> WLAN_INT_STATUS_GENERIC_MBOX_LSB) +#define WLAN_INT_STATUS_GENERIC_MBOX_SET(x) (((x) << WLAN_INT_STATUS_GENERIC_MBOX_LSB) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) +#define WLAN_INT_STATUS_RDMA_MSB 16 +#define WLAN_INT_STATUS_RDMA_LSB 16 +#define WLAN_INT_STATUS_RDMA_MASK 0x00010000 +#define WLAN_INT_STATUS_RDMA_GET(x) (((x) & WLAN_INT_STATUS_RDMA_MASK) >> WLAN_INT_STATUS_RDMA_LSB) +#define WLAN_INT_STATUS_RDMA_SET(x) (((x) << WLAN_INT_STATUS_RDMA_LSB) & WLAN_INT_STATUS_RDMA_MASK) +#define WLAN_INT_STATUS_BTCOEX_MSB 15 +#define WLAN_INT_STATUS_BTCOEX_LSB 15 +#define WLAN_INT_STATUS_BTCOEX_MASK 0x00008000 +#define WLAN_INT_STATUS_BTCOEX_GET(x) (((x) & WLAN_INT_STATUS_BTCOEX_MASK) >> WLAN_INT_STATUS_BTCOEX_LSB) +#define WLAN_INT_STATUS_BTCOEX_SET(x) (((x) << WLAN_INT_STATUS_BTCOEX_LSB) & WLAN_INT_STATUS_BTCOEX_MASK) +#define WLAN_INT_STATUS_RTC_POWER_MSB 14 +#define WLAN_INT_STATUS_RTC_POWER_LSB 14 +#define WLAN_INT_STATUS_RTC_POWER_MASK 0x00004000 +#define WLAN_INT_STATUS_RTC_POWER_GET(x) (((x) & WLAN_INT_STATUS_RTC_POWER_MASK) >> WLAN_INT_STATUS_RTC_POWER_LSB) +#define WLAN_INT_STATUS_RTC_POWER_SET(x) (((x) << WLAN_INT_STATUS_RTC_POWER_LSB) & WLAN_INT_STATUS_RTC_POWER_MASK) +#define WLAN_INT_STATUS_MAC_MSB 13 +#define WLAN_INT_STATUS_MAC_LSB 13 +#define WLAN_INT_STATUS_MAC_MASK 0x00002000 +#define WLAN_INT_STATUS_MAC_GET(x) (((x) & WLAN_INT_STATUS_MAC_MASK) >> WLAN_INT_STATUS_MAC_LSB) +#define WLAN_INT_STATUS_MAC_SET(x) (((x) << WLAN_INT_STATUS_MAC_LSB) & WLAN_INT_STATUS_MAC_MASK) +#define WLAN_INT_STATUS_MAILBOX_MSB 12 +#define WLAN_INT_STATUS_MAILBOX_LSB 12 +#define WLAN_INT_STATUS_MAILBOX_MASK 0x00001000 +#define WLAN_INT_STATUS_MAILBOX_GET(x) (((x) & WLAN_INT_STATUS_MAILBOX_MASK) >> WLAN_INT_STATUS_MAILBOX_LSB) +#define WLAN_INT_STATUS_MAILBOX_SET(x) (((x) << WLAN_INT_STATUS_MAILBOX_LSB) & WLAN_INT_STATUS_MAILBOX_MASK) +#define WLAN_INT_STATUS_RTC_ALARM_MSB 11 +#define WLAN_INT_STATUS_RTC_ALARM_LSB 11 +#define WLAN_INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define WLAN_INT_STATUS_RTC_ALARM_GET(x) (((x) & WLAN_INT_STATUS_RTC_ALARM_MASK) >> WLAN_INT_STATUS_RTC_ALARM_LSB) +#define WLAN_INT_STATUS_RTC_ALARM_SET(x) (((x) << WLAN_INT_STATUS_RTC_ALARM_LSB) & WLAN_INT_STATUS_RTC_ALARM_MASK) +#define WLAN_INT_STATUS_HF_TIMER_MSB 10 +#define WLAN_INT_STATUS_HF_TIMER_LSB 10 +#define WLAN_INT_STATUS_HF_TIMER_MASK 0x00000400 +#define WLAN_INT_STATUS_HF_TIMER_GET(x) (((x) & WLAN_INT_STATUS_HF_TIMER_MASK) >> WLAN_INT_STATUS_HF_TIMER_LSB) +#define WLAN_INT_STATUS_HF_TIMER_SET(x) (((x) << WLAN_INT_STATUS_HF_TIMER_LSB) & WLAN_INT_STATUS_HF_TIMER_MASK) +#define WLAN_INT_STATUS_LF_TIMER3_MSB 9 +#define WLAN_INT_STATUS_LF_TIMER3_LSB 9 +#define WLAN_INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define WLAN_INT_STATUS_LF_TIMER3_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER3_MASK) >> WLAN_INT_STATUS_LF_TIMER3_LSB) +#define WLAN_INT_STATUS_LF_TIMER3_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER3_LSB) & WLAN_INT_STATUS_LF_TIMER3_MASK) +#define WLAN_INT_STATUS_LF_TIMER2_MSB 8 +#define WLAN_INT_STATUS_LF_TIMER2_LSB 8 +#define WLAN_INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define WLAN_INT_STATUS_LF_TIMER2_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER2_MASK) >> WLAN_INT_STATUS_LF_TIMER2_LSB) +#define WLAN_INT_STATUS_LF_TIMER2_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER2_LSB) & WLAN_INT_STATUS_LF_TIMER2_MASK) +#define WLAN_INT_STATUS_LF_TIMER1_MSB 7 +#define WLAN_INT_STATUS_LF_TIMER1_LSB 7 +#define WLAN_INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define WLAN_INT_STATUS_LF_TIMER1_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER1_MASK) >> WLAN_INT_STATUS_LF_TIMER1_LSB) +#define WLAN_INT_STATUS_LF_TIMER1_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER1_LSB) & WLAN_INT_STATUS_LF_TIMER1_MASK) +#define WLAN_INT_STATUS_LF_TIMER0_MSB 6 +#define WLAN_INT_STATUS_LF_TIMER0_LSB 6 +#define WLAN_INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define WLAN_INT_STATUS_LF_TIMER0_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER0_MASK) >> WLAN_INT_STATUS_LF_TIMER0_LSB) +#define WLAN_INT_STATUS_LF_TIMER0_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER0_LSB) & WLAN_INT_STATUS_LF_TIMER0_MASK) +#define WLAN_INT_STATUS_KEYPAD_MSB 5 +#define WLAN_INT_STATUS_KEYPAD_LSB 5 +#define WLAN_INT_STATUS_KEYPAD_MASK 0x00000020 +#define WLAN_INT_STATUS_KEYPAD_GET(x) (((x) & WLAN_INT_STATUS_KEYPAD_MASK) >> WLAN_INT_STATUS_KEYPAD_LSB) +#define WLAN_INT_STATUS_KEYPAD_SET(x) (((x) << WLAN_INT_STATUS_KEYPAD_LSB) & WLAN_INT_STATUS_KEYPAD_MASK) +#define WLAN_INT_STATUS_SI_MSB 4 +#define WLAN_INT_STATUS_SI_LSB 4 +#define WLAN_INT_STATUS_SI_MASK 0x00000010 +#define WLAN_INT_STATUS_SI_GET(x) (((x) & WLAN_INT_STATUS_SI_MASK) >> WLAN_INT_STATUS_SI_LSB) +#define WLAN_INT_STATUS_SI_SET(x) (((x) << WLAN_INT_STATUS_SI_LSB) & WLAN_INT_STATUS_SI_MASK) +#define WLAN_INT_STATUS_GPIO_MSB 3 +#define WLAN_INT_STATUS_GPIO_LSB 3 +#define WLAN_INT_STATUS_GPIO_MASK 0x00000008 +#define WLAN_INT_STATUS_GPIO_GET(x) (((x) & WLAN_INT_STATUS_GPIO_MASK) >> WLAN_INT_STATUS_GPIO_LSB) +#define WLAN_INT_STATUS_GPIO_SET(x) (((x) << WLAN_INT_STATUS_GPIO_LSB) & WLAN_INT_STATUS_GPIO_MASK) +#define WLAN_INT_STATUS_UART_MSB 2 +#define WLAN_INT_STATUS_UART_LSB 2 +#define WLAN_INT_STATUS_UART_MASK 0x00000004 +#define WLAN_INT_STATUS_UART_GET(x) (((x) & WLAN_INT_STATUS_UART_MASK) >> WLAN_INT_STATUS_UART_LSB) +#define WLAN_INT_STATUS_UART_SET(x) (((x) << WLAN_INT_STATUS_UART_LSB) & WLAN_INT_STATUS_UART_MASK) +#define WLAN_INT_STATUS_ERROR_MSB 1 +#define WLAN_INT_STATUS_ERROR_LSB 1 +#define WLAN_INT_STATUS_ERROR_MASK 0x00000002 +#define WLAN_INT_STATUS_ERROR_GET(x) (((x) & WLAN_INT_STATUS_ERROR_MASK) >> WLAN_INT_STATUS_ERROR_LSB) +#define WLAN_INT_STATUS_ERROR_SET(x) (((x) << WLAN_INT_STATUS_ERROR_LSB) & WLAN_INT_STATUS_ERROR_MASK) +#define WLAN_INT_STATUS_WDT_INT_MSB 0 +#define WLAN_INT_STATUS_WDT_INT_LSB 0 +#define WLAN_INT_STATUS_WDT_INT_MASK 0x00000001 +#define WLAN_INT_STATUS_WDT_INT_GET(x) (((x) & WLAN_INT_STATUS_WDT_INT_MASK) >> WLAN_INT_STATUS_WDT_INT_LSB) +#define WLAN_INT_STATUS_WDT_INT_SET(x) (((x) << WLAN_INT_STATUS_WDT_INT_LSB) & WLAN_INT_STATUS_WDT_INT_MASK) + +#define WLAN_LF_TIMER0_ADDRESS 0x00000048 +#define WLAN_LF_TIMER0_OFFSET 0x00000048 +#define WLAN_LF_TIMER0_TARGET_MSB 31 +#define WLAN_LF_TIMER0_TARGET_LSB 0 +#define WLAN_LF_TIMER0_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER0_TARGET_GET(x) (((x) & WLAN_LF_TIMER0_TARGET_MASK) >> WLAN_LF_TIMER0_TARGET_LSB) +#define WLAN_LF_TIMER0_TARGET_SET(x) (((x) << WLAN_LF_TIMER0_TARGET_LSB) & WLAN_LF_TIMER0_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define WLAN_LF_TIMER_COUNT0_OFFSET 0x0000004c +#define WLAN_LF_TIMER_COUNT0_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT0_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT0_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) >> WLAN_LF_TIMER_COUNT0_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT0_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT0_VALUE_LSB) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define WLAN_LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL0_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL0_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL0_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) >> WLAN_LF_TIMER_CONTROL0_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL0_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_RESET_LSB) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define WLAN_LF_TIMER_STATUS0_OFFSET 0x00000054 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define WLAN_LF_TIMER1_ADDRESS 0x00000058 +#define WLAN_LF_TIMER1_OFFSET 0x00000058 +#define WLAN_LF_TIMER1_TARGET_MSB 31 +#define WLAN_LF_TIMER1_TARGET_LSB 0 +#define WLAN_LF_TIMER1_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER1_TARGET_GET(x) (((x) & WLAN_LF_TIMER1_TARGET_MASK) >> WLAN_LF_TIMER1_TARGET_LSB) +#define WLAN_LF_TIMER1_TARGET_SET(x) (((x) << WLAN_LF_TIMER1_TARGET_LSB) & WLAN_LF_TIMER1_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define WLAN_LF_TIMER_COUNT1_OFFSET 0x0000005c +#define WLAN_LF_TIMER_COUNT1_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT1_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT1_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) >> WLAN_LF_TIMER_COUNT1_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT1_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT1_VALUE_LSB) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define WLAN_LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL1_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL1_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL1_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) >> WLAN_LF_TIMER_CONTROL1_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL1_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_RESET_LSB) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define WLAN_LF_TIMER_STATUS1_OFFSET 0x00000064 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define WLAN_LF_TIMER2_ADDRESS 0x00000068 +#define WLAN_LF_TIMER2_OFFSET 0x00000068 +#define WLAN_LF_TIMER2_TARGET_MSB 31 +#define WLAN_LF_TIMER2_TARGET_LSB 0 +#define WLAN_LF_TIMER2_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER2_TARGET_GET(x) (((x) & WLAN_LF_TIMER2_TARGET_MASK) >> WLAN_LF_TIMER2_TARGET_LSB) +#define WLAN_LF_TIMER2_TARGET_SET(x) (((x) << WLAN_LF_TIMER2_TARGET_LSB) & WLAN_LF_TIMER2_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define WLAN_LF_TIMER_COUNT2_OFFSET 0x0000006c +#define WLAN_LF_TIMER_COUNT2_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT2_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT2_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) >> WLAN_LF_TIMER_COUNT2_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT2_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT2_VALUE_LSB) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define WLAN_LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL2_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL2_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL2_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) >> WLAN_LF_TIMER_CONTROL2_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL2_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_RESET_LSB) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define WLAN_LF_TIMER_STATUS2_OFFSET 0x00000074 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define WLAN_LF_TIMER3_ADDRESS 0x00000078 +#define WLAN_LF_TIMER3_OFFSET 0x00000078 +#define WLAN_LF_TIMER3_TARGET_MSB 31 +#define WLAN_LF_TIMER3_TARGET_LSB 0 +#define WLAN_LF_TIMER3_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER3_TARGET_GET(x) (((x) & WLAN_LF_TIMER3_TARGET_MASK) >> WLAN_LF_TIMER3_TARGET_LSB) +#define WLAN_LF_TIMER3_TARGET_SET(x) (((x) << WLAN_LF_TIMER3_TARGET_LSB) & WLAN_LF_TIMER3_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define WLAN_LF_TIMER_COUNT3_OFFSET 0x0000007c +#define WLAN_LF_TIMER_COUNT3_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT3_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT3_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) >> WLAN_LF_TIMER_COUNT3_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT3_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT3_VALUE_LSB) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define WLAN_LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL3_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL3_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL3_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) >> WLAN_LF_TIMER_CONTROL3_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL3_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_RESET_LSB) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define WLAN_LF_TIMER_STATUS3_OFFSET 0x00000084 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define WLAN_HF_TIMER_ADDRESS 0x00000088 +#define WLAN_HF_TIMER_OFFSET 0x00000088 +#define WLAN_HF_TIMER_TARGET_MSB 31 +#define WLAN_HF_TIMER_TARGET_LSB 12 +#define WLAN_HF_TIMER_TARGET_MASK 0xfffff000 +#define WLAN_HF_TIMER_TARGET_GET(x) (((x) & WLAN_HF_TIMER_TARGET_MASK) >> WLAN_HF_TIMER_TARGET_LSB) +#define WLAN_HF_TIMER_TARGET_SET(x) (((x) << WLAN_HF_TIMER_TARGET_LSB) & WLAN_HF_TIMER_TARGET_MASK) + +#define WLAN_HF_TIMER_COUNT_ADDRESS 0x0000008c +#define WLAN_HF_TIMER_COUNT_OFFSET 0x0000008c +#define WLAN_HF_TIMER_COUNT_VALUE_MSB 31 +#define WLAN_HF_TIMER_COUNT_VALUE_LSB 12 +#define WLAN_HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define WLAN_HF_TIMER_COUNT_VALUE_GET(x) (((x) & WLAN_HF_TIMER_COUNT_VALUE_MASK) >> WLAN_HF_TIMER_COUNT_VALUE_LSB) +#define WLAN_HF_TIMER_COUNT_VALUE_SET(x) (((x) << WLAN_HF_TIMER_COUNT_VALUE_LSB) & WLAN_HF_TIMER_COUNT_VALUE_MASK) + +#define WLAN_HF_LF_COUNT_ADDRESS 0x00000090 +#define WLAN_HF_LF_COUNT_OFFSET 0x00000090 +#define WLAN_HF_LF_COUNT_VALUE_MSB 31 +#define WLAN_HF_LF_COUNT_VALUE_LSB 0 +#define WLAN_HF_LF_COUNT_VALUE_MASK 0xffffffff +#define WLAN_HF_LF_COUNT_VALUE_GET(x) (((x) & WLAN_HF_LF_COUNT_VALUE_MASK) >> WLAN_HF_LF_COUNT_VALUE_LSB) +#define WLAN_HF_LF_COUNT_VALUE_SET(x) (((x) << WLAN_HF_LF_COUNT_VALUE_LSB) & WLAN_HF_LF_COUNT_VALUE_MASK) + +#define WLAN_HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define WLAN_HF_TIMER_CONTROL_OFFSET 0x00000094 +#define WLAN_HF_TIMER_CONTROL_ENABLE_MSB 3 +#define WLAN_HF_TIMER_CONTROL_ENABLE_LSB 3 +#define WLAN_HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) >> WLAN_HF_TIMER_CONTROL_ENABLE_LSB) +#define WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ENABLE_LSB) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) +#define WLAN_HF_TIMER_CONTROL_ON_MSB 2 +#define WLAN_HF_TIMER_CONTROL_ON_LSB 2 +#define WLAN_HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define WLAN_HF_TIMER_CONTROL_ON_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ON_MASK) >> WLAN_HF_TIMER_CONTROL_ON_LSB) +#define WLAN_HF_TIMER_CONTROL_ON_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ON_LSB) & WLAN_HF_TIMER_CONTROL_ON_MASK) +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define WLAN_HF_TIMER_CONTROL_RESET_MSB 0 +#define WLAN_HF_TIMER_CONTROL_RESET_LSB 0 +#define WLAN_HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define WLAN_HF_TIMER_CONTROL_RESET_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_RESET_MASK) >> WLAN_HF_TIMER_CONTROL_RESET_LSB) +#define WLAN_HF_TIMER_CONTROL_RESET_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_RESET_LSB) & WLAN_HF_TIMER_CONTROL_RESET_MASK) + +#define WLAN_HF_TIMER_STATUS_ADDRESS 0x00000098 +#define WLAN_HF_TIMER_STATUS_OFFSET 0x00000098 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) >> WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) +#define WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) + +#define WLAN_RTC_CONTROL_ADDRESS 0x0000009c +#define WLAN_RTC_CONTROL_OFFSET 0x0000009c +#define WLAN_RTC_CONTROL_ENABLE_MSB 2 +#define WLAN_RTC_CONTROL_ENABLE_LSB 2 +#define WLAN_RTC_CONTROL_ENABLE_MASK 0x00000004 +#define WLAN_RTC_CONTROL_ENABLE_GET(x) (((x) & WLAN_RTC_CONTROL_ENABLE_MASK) >> WLAN_RTC_CONTROL_ENABLE_LSB) +#define WLAN_RTC_CONTROL_ENABLE_SET(x) (((x) << WLAN_RTC_CONTROL_ENABLE_LSB) & WLAN_RTC_CONTROL_ENABLE_MASK) +#define WLAN_RTC_CONTROL_LOAD_RTC_MSB 1 +#define WLAN_RTC_CONTROL_LOAD_RTC_LSB 1 +#define WLAN_RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define WLAN_RTC_CONTROL_LOAD_RTC_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) >> WLAN_RTC_CONTROL_LOAD_RTC_LSB) +#define WLAN_RTC_CONTROL_LOAD_RTC_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_RTC_LSB) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) +#define WLAN_RTC_CONTROL_LOAD_ALARM_MSB 0 +#define WLAN_RTC_CONTROL_LOAD_ALARM_LSB 0 +#define WLAN_RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) >> WLAN_RTC_CONTROL_LOAD_ALARM_LSB) +#define WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_ALARM_LSB) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) + +#define WLAN_RTC_TIME_ADDRESS 0x000000a0 +#define WLAN_RTC_TIME_OFFSET 0x000000a0 +#define WLAN_RTC_TIME_WEEK_DAY_MSB 26 +#define WLAN_RTC_TIME_WEEK_DAY_LSB 24 +#define WLAN_RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define WLAN_RTC_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_TIME_WEEK_DAY_MASK) >> WLAN_RTC_TIME_WEEK_DAY_LSB) +#define WLAN_RTC_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_TIME_WEEK_DAY_LSB) & WLAN_RTC_TIME_WEEK_DAY_MASK) +#define WLAN_RTC_TIME_HOUR_MSB 21 +#define WLAN_RTC_TIME_HOUR_LSB 16 +#define WLAN_RTC_TIME_HOUR_MASK 0x003f0000 +#define WLAN_RTC_TIME_HOUR_GET(x) (((x) & WLAN_RTC_TIME_HOUR_MASK) >> WLAN_RTC_TIME_HOUR_LSB) +#define WLAN_RTC_TIME_HOUR_SET(x) (((x) << WLAN_RTC_TIME_HOUR_LSB) & WLAN_RTC_TIME_HOUR_MASK) +#define WLAN_RTC_TIME_MINUTE_MSB 14 +#define WLAN_RTC_TIME_MINUTE_LSB 8 +#define WLAN_RTC_TIME_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_TIME_MINUTE_MASK) >> WLAN_RTC_TIME_MINUTE_LSB) +#define WLAN_RTC_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_TIME_MINUTE_LSB) & WLAN_RTC_TIME_MINUTE_MASK) +#define WLAN_RTC_TIME_SECOND_MSB 6 +#define WLAN_RTC_TIME_SECOND_LSB 0 +#define WLAN_RTC_TIME_SECOND_MASK 0x0000007f +#define WLAN_RTC_TIME_SECOND_GET(x) (((x) & WLAN_RTC_TIME_SECOND_MASK) >> WLAN_RTC_TIME_SECOND_LSB) +#define WLAN_RTC_TIME_SECOND_SET(x) (((x) << WLAN_RTC_TIME_SECOND_LSB) & WLAN_RTC_TIME_SECOND_MASK) + +#define WLAN_RTC_DATE_ADDRESS 0x000000a4 +#define WLAN_RTC_DATE_OFFSET 0x000000a4 +#define WLAN_RTC_DATE_YEAR_MSB 23 +#define WLAN_RTC_DATE_YEAR_LSB 16 +#define WLAN_RTC_DATE_YEAR_MASK 0x00ff0000 +#define WLAN_RTC_DATE_YEAR_GET(x) (((x) & WLAN_RTC_DATE_YEAR_MASK) >> WLAN_RTC_DATE_YEAR_LSB) +#define WLAN_RTC_DATE_YEAR_SET(x) (((x) << WLAN_RTC_DATE_YEAR_LSB) & WLAN_RTC_DATE_YEAR_MASK) +#define WLAN_RTC_DATE_MONTH_MSB 12 +#define WLAN_RTC_DATE_MONTH_LSB 8 +#define WLAN_RTC_DATE_MONTH_MASK 0x00001f00 +#define WLAN_RTC_DATE_MONTH_GET(x) (((x) & WLAN_RTC_DATE_MONTH_MASK) >> WLAN_RTC_DATE_MONTH_LSB) +#define WLAN_RTC_DATE_MONTH_SET(x) (((x) << WLAN_RTC_DATE_MONTH_LSB) & WLAN_RTC_DATE_MONTH_MASK) +#define WLAN_RTC_DATE_MONTH_DAY_MSB 5 +#define WLAN_RTC_DATE_MONTH_DAY_LSB 0 +#define WLAN_RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define WLAN_RTC_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_DATE_MONTH_DAY_MASK) >> WLAN_RTC_DATE_MONTH_DAY_LSB) +#define WLAN_RTC_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_DATE_MONTH_DAY_LSB) & WLAN_RTC_DATE_MONTH_DAY_MASK) + +#define WLAN_RTC_SET_TIME_ADDRESS 0x000000a8 +#define WLAN_RTC_SET_TIME_OFFSET 0x000000a8 +#define WLAN_RTC_SET_TIME_WEEK_DAY_MSB 26 +#define WLAN_RTC_SET_TIME_WEEK_DAY_LSB 24 +#define WLAN_RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) >> WLAN_RTC_SET_TIME_WEEK_DAY_LSB) +#define WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_SET_TIME_WEEK_DAY_LSB) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) +#define WLAN_RTC_SET_TIME_HOUR_MSB 21 +#define WLAN_RTC_SET_TIME_HOUR_LSB 16 +#define WLAN_RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define WLAN_RTC_SET_TIME_HOUR_GET(x) (((x) & WLAN_RTC_SET_TIME_HOUR_MASK) >> WLAN_RTC_SET_TIME_HOUR_LSB) +#define WLAN_RTC_SET_TIME_HOUR_SET(x) (((x) << WLAN_RTC_SET_TIME_HOUR_LSB) & WLAN_RTC_SET_TIME_HOUR_MASK) +#define WLAN_RTC_SET_TIME_MINUTE_MSB 14 +#define WLAN_RTC_SET_TIME_MINUTE_LSB 8 +#define WLAN_RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_SET_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_SET_TIME_MINUTE_MASK) >> WLAN_RTC_SET_TIME_MINUTE_LSB) +#define WLAN_RTC_SET_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_SET_TIME_MINUTE_LSB) & WLAN_RTC_SET_TIME_MINUTE_MASK) +#define WLAN_RTC_SET_TIME_SECOND_MSB 6 +#define WLAN_RTC_SET_TIME_SECOND_LSB 0 +#define WLAN_RTC_SET_TIME_SECOND_MASK 0x0000007f +#define WLAN_RTC_SET_TIME_SECOND_GET(x) (((x) & WLAN_RTC_SET_TIME_SECOND_MASK) >> WLAN_RTC_SET_TIME_SECOND_LSB) +#define WLAN_RTC_SET_TIME_SECOND_SET(x) (((x) << WLAN_RTC_SET_TIME_SECOND_LSB) & WLAN_RTC_SET_TIME_SECOND_MASK) + +#define WLAN_RTC_SET_DATE_ADDRESS 0x000000ac +#define WLAN_RTC_SET_DATE_OFFSET 0x000000ac +#define WLAN_RTC_SET_DATE_YEAR_MSB 23 +#define WLAN_RTC_SET_DATE_YEAR_LSB 16 +#define WLAN_RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define WLAN_RTC_SET_DATE_YEAR_GET(x) (((x) & WLAN_RTC_SET_DATE_YEAR_MASK) >> WLAN_RTC_SET_DATE_YEAR_LSB) +#define WLAN_RTC_SET_DATE_YEAR_SET(x) (((x) << WLAN_RTC_SET_DATE_YEAR_LSB) & WLAN_RTC_SET_DATE_YEAR_MASK) +#define WLAN_RTC_SET_DATE_MONTH_MSB 12 +#define WLAN_RTC_SET_DATE_MONTH_LSB 8 +#define WLAN_RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define WLAN_RTC_SET_DATE_MONTH_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_MASK) >> WLAN_RTC_SET_DATE_MONTH_LSB) +#define WLAN_RTC_SET_DATE_MONTH_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_LSB) & WLAN_RTC_SET_DATE_MONTH_MASK) +#define WLAN_RTC_SET_DATE_MONTH_DAY_MSB 5 +#define WLAN_RTC_SET_DATE_MONTH_DAY_LSB 0 +#define WLAN_RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) >> WLAN_RTC_SET_DATE_MONTH_DAY_LSB) +#define WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_DAY_LSB) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) + +#define WLAN_RTC_SET_ALARM_ADDRESS 0x000000b0 +#define WLAN_RTC_SET_ALARM_OFFSET 0x000000b0 +#define WLAN_RTC_SET_ALARM_HOUR_MSB 21 +#define WLAN_RTC_SET_ALARM_HOUR_LSB 16 +#define WLAN_RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define WLAN_RTC_SET_ALARM_HOUR_GET(x) (((x) & WLAN_RTC_SET_ALARM_HOUR_MASK) >> WLAN_RTC_SET_ALARM_HOUR_LSB) +#define WLAN_RTC_SET_ALARM_HOUR_SET(x) (((x) << WLAN_RTC_SET_ALARM_HOUR_LSB) & WLAN_RTC_SET_ALARM_HOUR_MASK) +#define WLAN_RTC_SET_ALARM_MINUTE_MSB 14 +#define WLAN_RTC_SET_ALARM_MINUTE_LSB 8 +#define WLAN_RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_SET_ALARM_MINUTE_GET(x) (((x) & WLAN_RTC_SET_ALARM_MINUTE_MASK) >> WLAN_RTC_SET_ALARM_MINUTE_LSB) +#define WLAN_RTC_SET_ALARM_MINUTE_SET(x) (((x) << WLAN_RTC_SET_ALARM_MINUTE_LSB) & WLAN_RTC_SET_ALARM_MINUTE_MASK) +#define WLAN_RTC_SET_ALARM_SECOND_MSB 6 +#define WLAN_RTC_SET_ALARM_SECOND_LSB 0 +#define WLAN_RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define WLAN_RTC_SET_ALARM_SECOND_GET(x) (((x) & WLAN_RTC_SET_ALARM_SECOND_MASK) >> WLAN_RTC_SET_ALARM_SECOND_LSB) +#define WLAN_RTC_SET_ALARM_SECOND_SET(x) (((x) << WLAN_RTC_SET_ALARM_SECOND_LSB) & WLAN_RTC_SET_ALARM_SECOND_MASK) + +#define WLAN_RTC_CONFIG_ADDRESS 0x000000b4 +#define WLAN_RTC_CONFIG_OFFSET 0x000000b4 +#define WLAN_RTC_CONFIG_BCD_MSB 2 +#define WLAN_RTC_CONFIG_BCD_LSB 2 +#define WLAN_RTC_CONFIG_BCD_MASK 0x00000004 +#define WLAN_RTC_CONFIG_BCD_GET(x) (((x) & WLAN_RTC_CONFIG_BCD_MASK) >> WLAN_RTC_CONFIG_BCD_LSB) +#define WLAN_RTC_CONFIG_BCD_SET(x) (((x) << WLAN_RTC_CONFIG_BCD_LSB) & WLAN_RTC_CONFIG_BCD_MASK) +#define WLAN_RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) >> WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) +#define WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) +#define WLAN_RTC_CONFIG_DSE_MSB 0 +#define WLAN_RTC_CONFIG_DSE_LSB 0 +#define WLAN_RTC_CONFIG_DSE_MASK 0x00000001 +#define WLAN_RTC_CONFIG_DSE_GET(x) (((x) & WLAN_RTC_CONFIG_DSE_MASK) >> WLAN_RTC_CONFIG_DSE_LSB) +#define WLAN_RTC_CONFIG_DSE_SET(x) (((x) << WLAN_RTC_CONFIG_DSE_LSB) & WLAN_RTC_CONFIG_DSE_MASK) + +#define WLAN_RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define WLAN_RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define WLAN_RTC_ALARM_STATUS_ENABLE_MSB 1 +#define WLAN_RTC_ALARM_STATUS_ENABLE_LSB 1 +#define WLAN_RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) >> WLAN_RTC_ALARM_STATUS_ENABLE_LSB) +#define WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_ENABLE_LSB) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) >> WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define WLAN_UART_WAKEUP_ADDRESS 0x000000bc +#define WLAN_UART_WAKEUP_OFFSET 0x000000bc +#define WLAN_UART_WAKEUP_ENABLE_MSB 0 +#define WLAN_UART_WAKEUP_ENABLE_LSB 0 +#define WLAN_UART_WAKEUP_ENABLE_MASK 0x00000001 +#define WLAN_UART_WAKEUP_ENABLE_GET(x) (((x) & WLAN_UART_WAKEUP_ENABLE_MASK) >> WLAN_UART_WAKEUP_ENABLE_LSB) +#define WLAN_UART_WAKEUP_ENABLE_SET(x) (((x) << WLAN_UART_WAKEUP_ENABLE_LSB) & WLAN_UART_WAKEUP_ENABLE_MASK) + +#define WLAN_RESET_CAUSE_ADDRESS 0x000000c0 +#define WLAN_RESET_CAUSE_OFFSET 0x000000c0 +#define WLAN_RESET_CAUSE_LAST_MSB 2 +#define WLAN_RESET_CAUSE_LAST_LSB 0 +#define WLAN_RESET_CAUSE_LAST_MASK 0x00000007 +#define WLAN_RESET_CAUSE_LAST_GET(x) (((x) & WLAN_RESET_CAUSE_LAST_MASK) >> WLAN_RESET_CAUSE_LAST_LSB) +#define WLAN_RESET_CAUSE_LAST_SET(x) (((x) << WLAN_RESET_CAUSE_LAST_LSB) & WLAN_RESET_CAUSE_LAST_MASK) + +#define WLAN_SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define WLAN_SYSTEM_SLEEP_OFFSET 0x000000c4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_MSB 4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_LSB 4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) >> WLAN_SYSTEM_SLEEP_HOST_IF_LSB) +#define WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_HOST_IF_LSB) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) +#define WLAN_SYSTEM_SLEEP_MBOX_MSB 3 +#define WLAN_SYSTEM_SLEEP_MBOX_LSB 3 +#define WLAN_SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define WLAN_SYSTEM_SLEEP_MBOX_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MBOX_MASK) >> WLAN_SYSTEM_SLEEP_MBOX_LSB) +#define WLAN_SYSTEM_SLEEP_MBOX_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MBOX_LSB) & WLAN_SYSTEM_SLEEP_MBOX_MASK) +#define WLAN_SYSTEM_SLEEP_MAC_IF_MSB 2 +#define WLAN_SYSTEM_SLEEP_MAC_IF_LSB 2 +#define WLAN_SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) >> WLAN_SYSTEM_SLEEP_MAC_IF_LSB) +#define WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MAC_IF_LSB) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) +#define WLAN_SYSTEM_SLEEP_LIGHT_MSB 1 +#define WLAN_SYSTEM_SLEEP_LIGHT_LSB 1 +#define WLAN_SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define WLAN_SYSTEM_SLEEP_LIGHT_GET(x) (((x) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) >> WLAN_SYSTEM_SLEEP_LIGHT_LSB) +#define WLAN_SYSTEM_SLEEP_LIGHT_SET(x) (((x) << WLAN_SYSTEM_SLEEP_LIGHT_LSB) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) +#define WLAN_SYSTEM_SLEEP_DISABLE_MSB 0 +#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 +#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define WLAN_SYSTEM_SLEEP_DISABLE_GET(x) (((x) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB) +#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) + +#define WLAN_SDIO_WRAPPER_ADDRESS 0x000000c8 +#define WLAN_SDIO_WRAPPER_OFFSET 0x000000c8 +#define WLAN_SDIO_WRAPPER_SLEEP_MSB 3 +#define WLAN_SDIO_WRAPPER_SLEEP_LSB 3 +#define WLAN_SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define WLAN_SDIO_WRAPPER_SLEEP_GET(x) (((x) & WLAN_SDIO_WRAPPER_SLEEP_MASK) >> WLAN_SDIO_WRAPPER_SLEEP_LSB) +#define WLAN_SDIO_WRAPPER_SLEEP_SET(x) (((x) << WLAN_SDIO_WRAPPER_SLEEP_LSB) & WLAN_SDIO_WRAPPER_SLEEP_MASK) +#define WLAN_SDIO_WRAPPER_WAKEUP_MSB 2 +#define WLAN_SDIO_WRAPPER_WAKEUP_LSB 2 +#define WLAN_SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define WLAN_SDIO_WRAPPER_WAKEUP_GET(x) (((x) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) >> WLAN_SDIO_WRAPPER_WAKEUP_LSB) +#define WLAN_SDIO_WRAPPER_WAKEUP_SET(x) (((x) << WLAN_SDIO_WRAPPER_WAKEUP_LSB) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) +#define WLAN_SDIO_WRAPPER_SOC_ON_MSB 1 +#define WLAN_SDIO_WRAPPER_SOC_ON_LSB 1 +#define WLAN_SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define WLAN_SDIO_WRAPPER_SOC_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) >> WLAN_SDIO_WRAPPER_SOC_ON_LSB) +#define WLAN_SDIO_WRAPPER_SOC_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_SOC_ON_LSB) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) +#define WLAN_SDIO_WRAPPER_ON_MSB 0 +#define WLAN_SDIO_WRAPPER_ON_LSB 0 +#define WLAN_SDIO_WRAPPER_ON_MASK 0x00000001 +#define WLAN_SDIO_WRAPPER_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_ON_MASK) >> WLAN_SDIO_WRAPPER_ON_LSB) +#define WLAN_SDIO_WRAPPER_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_ON_LSB) & WLAN_SDIO_WRAPPER_ON_MASK) + +#define WLAN_MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define WLAN_MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) >> WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define WLAN_KEEP_AWAKE_ADDRESS 0x000000d0 +#define WLAN_KEEP_AWAKE_OFFSET 0x000000d0 +#define WLAN_KEEP_AWAKE_COUNT_MSB 7 +#define WLAN_KEEP_AWAKE_COUNT_LSB 0 +#define WLAN_KEEP_AWAKE_COUNT_MASK 0x000000ff +#define WLAN_KEEP_AWAKE_COUNT_GET(x) (((x) & WLAN_KEEP_AWAKE_COUNT_MASK) >> WLAN_KEEP_AWAKE_COUNT_LSB) +#define WLAN_KEEP_AWAKE_COUNT_SET(x) (((x) << WLAN_KEEP_AWAKE_COUNT_LSB) & WLAN_KEEP_AWAKE_COUNT_MASK) + +#define WLAN_LPO_CAL_TIME_ADDRESS 0x000000d4 +#define WLAN_LPO_CAL_TIME_OFFSET 0x000000d4 +#define WLAN_LPO_CAL_TIME_LENGTH_MSB 13 +#define WLAN_LPO_CAL_TIME_LENGTH_LSB 0 +#define WLAN_LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define WLAN_LPO_CAL_TIME_LENGTH_GET(x) (((x) & WLAN_LPO_CAL_TIME_LENGTH_MASK) >> WLAN_LPO_CAL_TIME_LENGTH_LSB) +#define WLAN_LPO_CAL_TIME_LENGTH_SET(x) (((x) << WLAN_LPO_CAL_TIME_LENGTH_LSB) & WLAN_LPO_CAL_TIME_LENGTH_MASK) + +#define WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define WLAN_LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define WLAN_LPO_CAL_ADDRESS 0x000000e0 +#define WLAN_LPO_CAL_OFFSET 0x000000e0 +#define WLAN_LPO_CAL_ENABLE_MSB 20 +#define WLAN_LPO_CAL_ENABLE_LSB 20 +#define WLAN_LPO_CAL_ENABLE_MASK 0x00100000 +#define WLAN_LPO_CAL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_ENABLE_MASK) >> WLAN_LPO_CAL_ENABLE_LSB) +#define WLAN_LPO_CAL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_ENABLE_LSB) & WLAN_LPO_CAL_ENABLE_MASK) +#define WLAN_LPO_CAL_COUNT_MSB 19 +#define WLAN_LPO_CAL_COUNT_LSB 0 +#define WLAN_LPO_CAL_COUNT_MASK 0x000fffff +#define WLAN_LPO_CAL_COUNT_GET(x) (((x) & WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB) +#define WLAN_LPO_CAL_COUNT_SET(x) (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK) + +#define WLAN_LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define WLAN_LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define WLAN_LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define WLAN_LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define WLAN_LPO_CAL_TEST_STATUS_READY_MSB 16 +#define WLAN_LPO_CAL_TEST_STATUS_READY_LSB 16 +#define WLAN_LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) >> WLAN_LPO_CAL_TEST_STATUS_READY_LSB) +#define WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_READY_LSB) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) >> WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define WLAN_CHIP_ID_ADDRESS 0x000000ec +#define WLAN_CHIP_ID_OFFSET 0x000000ec +#define WLAN_CHIP_ID_DEVICE_ID_MSB 31 +#define WLAN_CHIP_ID_DEVICE_ID_LSB 16 +#define WLAN_CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define WLAN_CHIP_ID_DEVICE_ID_GET(x) (((x) & WLAN_CHIP_ID_DEVICE_ID_MASK) >> WLAN_CHIP_ID_DEVICE_ID_LSB) +#define WLAN_CHIP_ID_DEVICE_ID_SET(x) (((x) << WLAN_CHIP_ID_DEVICE_ID_LSB) & WLAN_CHIP_ID_DEVICE_ID_MASK) +#define WLAN_CHIP_ID_CONFIG_ID_MSB 15 +#define WLAN_CHIP_ID_CONFIG_ID_LSB 4 +#define WLAN_CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define WLAN_CHIP_ID_CONFIG_ID_GET(x) (((x) & WLAN_CHIP_ID_CONFIG_ID_MASK) >> WLAN_CHIP_ID_CONFIG_ID_LSB) +#define WLAN_CHIP_ID_CONFIG_ID_SET(x) (((x) << WLAN_CHIP_ID_CONFIG_ID_LSB) & WLAN_CHIP_ID_CONFIG_ID_MASK) +#define WLAN_CHIP_ID_VERSION_ID_MSB 3 +#define WLAN_CHIP_ID_VERSION_ID_LSB 0 +#define WLAN_CHIP_ID_VERSION_ID_MASK 0x0000000f +#define WLAN_CHIP_ID_VERSION_ID_GET(x) (((x) & WLAN_CHIP_ID_VERSION_ID_MASK) >> WLAN_CHIP_ID_VERSION_ID_LSB) +#define WLAN_CHIP_ID_VERSION_ID_SET(x) (((x) << WLAN_CHIP_ID_VERSION_ID_LSB) & WLAN_CHIP_ID_VERSION_ID_MASK) + +#define WLAN_DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define WLAN_DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define WLAN_DERIVED_RTC_CLK_FORCE_MSB 17 +#define WLAN_DERIVED_RTC_CLK_FORCE_LSB 16 +#define WLAN_DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define WLAN_DERIVED_RTC_CLK_FORCE_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) >> WLAN_DERIVED_RTC_CLK_FORCE_LSB) +#define WLAN_DERIVED_RTC_CLK_FORCE_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_FORCE_LSB) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) +#define WLAN_DERIVED_RTC_CLK_PERIOD_MSB 15 +#define WLAN_DERIVED_RTC_CLK_PERIOD_LSB 1 +#define WLAN_DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) >> WLAN_DERIVED_RTC_CLK_PERIOD_LSB) +#define WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_PERIOD_LSB) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MSB 24 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB 24 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK 0x01000000 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MSB 23 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB 23 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK 0x00800000 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_GET(x) (((x) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) >> MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_SET(x) (((x) << MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MSB 22 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB 22 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK 0x00400000 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_GET(x) (((x) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) >> MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_SET(x) (((x) << MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) +#define MAC_PCU_SLP32_MODE_ENABLE_MSB 20 +#define MAC_PCU_SLP32_MODE_ENABLE_LSB 20 +#define MAC_PCU_SLP32_MODE_ENABLE_MASK 0x00100000 +#define MAC_PCU_SLP32_MODE_ENABLE_GET(x) (((x) & MAC_PCU_SLP32_MODE_ENABLE_MASK) >> MAC_PCU_SLP32_MODE_ENABLE_LSB) +#define MAC_PCU_SLP32_MODE_ENABLE_SET(x) (((x) << MAC_PCU_SLP32_MODE_ENABLE_LSB) & MAC_PCU_SLP32_MODE_ENABLE_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define WLAN_POWER_REG_ADDRESS 0x0000010c +#define WLAN_POWER_REG_OFFSET 0x0000010c +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB 15 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB 15 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK 0x00008000 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) (((x) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) >> WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) (((x) << WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) +#define WLAN_POWER_REG_DEBUG_EN_MSB 14 +#define WLAN_POWER_REG_DEBUG_EN_LSB 14 +#define WLAN_POWER_REG_DEBUG_EN_MASK 0x00004000 +#define WLAN_POWER_REG_DEBUG_EN_GET(x) (((x) & WLAN_POWER_REG_DEBUG_EN_MASK) >> WLAN_POWER_REG_DEBUG_EN_LSB) +#define WLAN_POWER_REG_DEBUG_EN_SET(x) (((x) << WLAN_POWER_REG_DEBUG_EN_LSB) & WLAN_POWER_REG_DEBUG_EN_MASK) +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB 13 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB 13 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK 0x00002000 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB 12 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB 12 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK 0x00001000 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) +#define WLAN_POWER_REG_VLVL_MSB 11 +#define WLAN_POWER_REG_VLVL_LSB 8 +#define WLAN_POWER_REG_VLVL_MASK 0x00000f00 +#define WLAN_POWER_REG_VLVL_GET(x) (((x) & WLAN_POWER_REG_VLVL_MASK) >> WLAN_POWER_REG_VLVL_LSB) +#define WLAN_POWER_REG_VLVL_SET(x) (((x) << WLAN_POWER_REG_VLVL_LSB) & WLAN_POWER_REG_VLVL_MASK) +#define WLAN_POWER_REG_CPU_INT_ENABLE_MSB 7 +#define WLAN_POWER_REG_CPU_INT_ENABLE_LSB 7 +#define WLAN_POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) >> WLAN_POWER_REG_CPU_INT_ENABLE_LSB) +#define WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << WLAN_POWER_REG_CPU_INT_ENABLE_LSB) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) +#define WLAN_POWER_REG_WLAN_ISO_DIS_MSB 6 +#define WLAN_POWER_REG_WLAN_ISO_DIS_LSB 6 +#define WLAN_POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) >> WLAN_POWER_REG_WLAN_ISO_DIS_LSB) +#define WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_DIS_LSB) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) +#define WLAN_POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) >> WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) +#define WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) +#define WLAN_POWER_REG_RADIO_PWD_EN_MSB 4 +#define WLAN_POWER_REG_RADIO_PWD_EN_LSB 4 +#define WLAN_POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define WLAN_POWER_REG_RADIO_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) >> WLAN_POWER_REG_RADIO_PWD_EN_LSB) +#define WLAN_POWER_REG_RADIO_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_RADIO_PWD_EN_LSB) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) +#define WLAN_POWER_REG_SOC_ISO_EN_MSB 3 +#define WLAN_POWER_REG_SOC_ISO_EN_LSB 3 +#define WLAN_POWER_REG_SOC_ISO_EN_MASK 0x00000008 +#define WLAN_POWER_REG_SOC_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_SOC_ISO_EN_MASK) >> WLAN_POWER_REG_SOC_ISO_EN_LSB) +#define WLAN_POWER_REG_SOC_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_SOC_ISO_EN_LSB) & WLAN_POWER_REG_SOC_ISO_EN_MASK) +#define WLAN_POWER_REG_WLAN_ISO_EN_MSB 2 +#define WLAN_POWER_REG_WLAN_ISO_EN_LSB 2 +#define WLAN_POWER_REG_WLAN_ISO_EN_MASK 0x00000004 +#define WLAN_POWER_REG_WLAN_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) >> WLAN_POWER_REG_WLAN_ISO_EN_LSB) +#define WLAN_POWER_REG_WLAN_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_EN_LSB) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) +#define WLAN_POWER_REG_WLAN_PWD_EN_MSB 1 +#define WLAN_POWER_REG_WLAN_PWD_EN_LSB 1 +#define WLAN_POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define WLAN_POWER_REG_WLAN_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) +#define WLAN_POWER_REG_POWER_EN_MSB 0 +#define WLAN_POWER_REG_POWER_EN_LSB 0 +#define WLAN_POWER_REG_POWER_EN_MASK 0x00000001 +#define WLAN_POWER_REG_POWER_EN_GET(x) (((x) & WLAN_POWER_REG_POWER_EN_MASK) >> WLAN_POWER_REG_POWER_EN_LSB) +#define WLAN_POWER_REG_POWER_EN_SET(x) (((x) << WLAN_POWER_REG_POWER_EN_LSB) & WLAN_POWER_REG_POWER_EN_MASK) + +#define WLAN_CORE_CLK_CTRL_ADDRESS 0x00000110 +#define WLAN_CORE_CLK_CTRL_OFFSET 0x00000110 +#define WLAN_CORE_CLK_CTRL_DIV_MSB 2 +#define WLAN_CORE_CLK_CTRL_DIV_LSB 0 +#define WLAN_CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define WLAN_CORE_CLK_CTRL_DIV_GET(x) (((x) & WLAN_CORE_CLK_CTRL_DIV_MASK) >> WLAN_CORE_CLK_CTRL_DIV_LSB) +#define WLAN_CORE_CLK_CTRL_DIV_SET(x) (((x) << WLAN_CORE_CLK_CTRL_DIV_LSB) & WLAN_CORE_CLK_CTRL_DIV_MASK) + +#define WLAN_GPIO_WAKEUP_CONTROL_ADDRESS 0x00000114 +#define WLAN_GPIO_WAKEUP_CONTROL_OFFSET 0x00000114 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) + +#define HT_ADDRESS 0x00000118 +#define HT_OFFSET 0x00000118 +#define HT_MODE_MSB 0 +#define HT_MODE_LSB 0 +#define HT_MODE_MASK 0x00000001 +#define HT_MODE_GET(x) (((x) & HT_MODE_MASK) >> HT_MODE_LSB) +#define HT_MODE_SET(x) (((x) << HT_MODE_LSB) & HT_MODE_MASK) + +#define MAC_PCU_TSF_L32_ADDRESS 0x0000011c +#define MAC_PCU_TSF_L32_OFFSET 0x0000011c +#define MAC_PCU_TSF_L32_VALUE_MSB 31 +#define MAC_PCU_TSF_L32_VALUE_LSB 0 +#define MAC_PCU_TSF_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF_L32_VALUE_MASK) >> MAC_PCU_TSF_L32_VALUE_LSB) +#define MAC_PCU_TSF_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF_L32_VALUE_LSB) & MAC_PCU_TSF_L32_VALUE_MASK) + +#define MAC_PCU_TSF_U32_ADDRESS 0x00000120 +#define MAC_PCU_TSF_U32_OFFSET 0x00000120 +#define MAC_PCU_TSF_U32_VALUE_MSB 31 +#define MAC_PCU_TSF_U32_VALUE_LSB 0 +#define MAC_PCU_TSF_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF_U32_VALUE_MASK) >> MAC_PCU_TSF_U32_VALUE_LSB) +#define MAC_PCU_TSF_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF_U32_VALUE_LSB) & MAC_PCU_TSF_U32_VALUE_MASK) + +#define MAC_PCU_WBTIMER_ADDRESS 0x00000124 +#define MAC_PCU_WBTIMER_OFFSET 0x00000124 +#define MAC_PCU_WBTIMER_VALUE_MSB 31 +#define MAC_PCU_WBTIMER_VALUE_LSB 0 +#define MAC_PCU_WBTIMER_VALUE_MASK 0xffffffff +#define MAC_PCU_WBTIMER_VALUE_GET(x) (((x) & MAC_PCU_WBTIMER_VALUE_MASK) >> MAC_PCU_WBTIMER_VALUE_LSB) +#define MAC_PCU_WBTIMER_VALUE_SET(x) (((x) << MAC_PCU_WBTIMER_VALUE_LSB) & MAC_PCU_WBTIMER_VALUE_MASK) + +#define MAC_PCU_GENERIC_TIMERS_ADDRESS 0x00000140 +#define MAC_PCU_GENERIC_TIMERS_OFFSET 0x00000140 +#define MAC_PCU_GENERIC_TIMERS_DATA_MSB 31 +#define MAC_PCU_GENERIC_TIMERS_DATA_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_DATA_MASK 0xffffffff +#define MAC_PCU_GENERIC_TIMERS_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS_DATA_LSB) +#define MAC_PCU_GENERIC_TIMERS_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_DATA_LSB) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE_ADDRESS 0x00000180 +#define MAC_PCU_GENERIC_TIMERS_MODE_OFFSET 0x00000180 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MSB 15 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK 0x0000ffff +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) + +#define MAC_PCU_GENERIC_TIMERS2_ADDRESS 0x000001c0 +#define MAC_PCU_GENERIC_TIMERS2_OFFSET 0x000001c0 +#define MAC_PCU_GENERIC_TIMERS2_DATA_MSB 31 +#define MAC_PCU_GENERIC_TIMERS2_DATA_LSB 0 +#define MAC_PCU_GENERIC_TIMERS2_DATA_MASK 0xffffffff +#define MAC_PCU_GENERIC_TIMERS2_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS2_DATA_LSB) +#define MAC_PCU_GENERIC_TIMERS2_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS2_DATA_LSB) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE2_ADDRESS 0x00000200 +#define MAC_PCU_GENERIC_TIMERS_MODE2_OFFSET 0x00000200 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MSB 15 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK 0x0000ffff +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) + +#define MAC_PCU_SLP1_ADDRESS 0x00000204 +#define MAC_PCU_SLP1_OFFSET 0x00000204 +#define MAC_PCU_SLP1_ASSUME_DTIM_MSB 19 +#define MAC_PCU_SLP1_ASSUME_DTIM_LSB 19 +#define MAC_PCU_SLP1_ASSUME_DTIM_MASK 0x00080000 +#define MAC_PCU_SLP1_ASSUME_DTIM_GET(x) (((x) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) >> MAC_PCU_SLP1_ASSUME_DTIM_LSB) +#define MAC_PCU_SLP1_ASSUME_DTIM_SET(x) (((x) << MAC_PCU_SLP1_ASSUME_DTIM_LSB) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) +#define MAC_PCU_SLP1_CAB_TIMEOUT_MSB 15 +#define MAC_PCU_SLP1_CAB_TIMEOUT_LSB 0 +#define MAC_PCU_SLP1_CAB_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_SLP1_CAB_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) >> MAC_PCU_SLP1_CAB_TIMEOUT_LSB) +#define MAC_PCU_SLP1_CAB_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP1_CAB_TIMEOUT_LSB) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) + +#define MAC_PCU_SLP2_ADDRESS 0x00000208 +#define MAC_PCU_SLP2_OFFSET 0x00000208 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_MSB 15 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_LSB 0 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_SLP2_BEACON_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) >> MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) +#define MAC_PCU_SLP2_BEACON_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) + +#define MAC_PCU_RESET_TSF_ADDRESS 0x0000020c +#define MAC_PCU_RESET_TSF_OFFSET 0x0000020c +#define MAC_PCU_RESET_TSF_ONE_SHOT2_MSB 25 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_LSB 25 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_MASK 0x02000000 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) +#define MAC_PCU_RESET_TSF_ONE_SHOT2_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) +#define MAC_PCU_RESET_TSF_ONE_SHOT_MSB 24 +#define MAC_PCU_RESET_TSF_ONE_SHOT_LSB 24 +#define MAC_PCU_RESET_TSF_ONE_SHOT_MASK 0x01000000 +#define MAC_PCU_RESET_TSF_ONE_SHOT_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT_LSB) +#define MAC_PCU_RESET_TSF_ONE_SHOT_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) + +#define MAC_PCU_TSF_ADD_PLL_ADDRESS 0x00000210 +#define MAC_PCU_TSF_ADD_PLL_OFFSET 0x00000210 +#define MAC_PCU_TSF_ADD_PLL_VALUE_MSB 7 +#define MAC_PCU_TSF_ADD_PLL_VALUE_LSB 0 +#define MAC_PCU_TSF_ADD_PLL_VALUE_MASK 0x000000ff +#define MAC_PCU_TSF_ADD_PLL_VALUE_GET(x) (((x) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) >> MAC_PCU_TSF_ADD_PLL_VALUE_LSB) +#define MAC_PCU_TSF_ADD_PLL_VALUE_SET(x) (((x) << MAC_PCU_TSF_ADD_PLL_VALUE_LSB) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) + +#define SLEEP_RETENTION_ADDRESS 0x00000214 +#define SLEEP_RETENTION_OFFSET 0x00000214 +#define SLEEP_RETENTION_TIME_MSB 9 +#define SLEEP_RETENTION_TIME_LSB 2 +#define SLEEP_RETENTION_TIME_MASK 0x000003fc +#define SLEEP_RETENTION_TIME_GET(x) (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB) +#define SLEEP_RETENTION_TIME_SET(x) (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK) +#define SLEEP_RETENTION_MODE_MSB 1 +#define SLEEP_RETENTION_MODE_LSB 1 +#define SLEEP_RETENTION_MODE_MASK 0x00000002 +#define SLEEP_RETENTION_MODE_GET(x) (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB) +#define SLEEP_RETENTION_MODE_SET(x) (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK) +#define SLEEP_RETENTION_ENABLE_MSB 0 +#define SLEEP_RETENTION_ENABLE_LSB 0 +#define SLEEP_RETENTION_ENABLE_MASK 0x00000001 +#define SLEEP_RETENTION_ENABLE_GET(x) (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB) +#define SLEEP_RETENTION_ENABLE_SET(x) (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK) + +#define BTCOEXCTRL_ADDRESS 0x00000218 +#define BTCOEXCTRL_OFFSET 0x00000218 +#define BTCOEXCTRL_WBTIMER_ENABLE_MSB 26 +#define BTCOEXCTRL_WBTIMER_ENABLE_LSB 26 +#define BTCOEXCTRL_WBTIMER_ENABLE_MASK 0x04000000 +#define BTCOEXCTRL_WBTIMER_ENABLE_GET(x) (((x) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) >> BTCOEXCTRL_WBTIMER_ENABLE_LSB) +#define BTCOEXCTRL_WBTIMER_ENABLE_SET(x) (((x) << BTCOEXCTRL_WBTIMER_ENABLE_LSB) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) +#define BTCOEXCTRL_WBSYNC_ON_BEACON_MSB 25 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_LSB 25 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_MASK 0x02000000 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_GET(x) (((x) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) >> BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) +#define BTCOEXCTRL_WBSYNC_ON_BEACON_SET(x) (((x) << BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) +#define BTCOEXCTRL_PTA_MODE_MSB 24 +#define BTCOEXCTRL_PTA_MODE_LSB 23 +#define BTCOEXCTRL_PTA_MODE_MASK 0x01800000 +#define BTCOEXCTRL_PTA_MODE_GET(x) (((x) & BTCOEXCTRL_PTA_MODE_MASK) >> BTCOEXCTRL_PTA_MODE_LSB) +#define BTCOEXCTRL_PTA_MODE_SET(x) (((x) << BTCOEXCTRL_PTA_MODE_LSB) & BTCOEXCTRL_PTA_MODE_MASK) +#define BTCOEXCTRL_FREQ_TIME_MSB 22 +#define BTCOEXCTRL_FREQ_TIME_LSB 18 +#define BTCOEXCTRL_FREQ_TIME_MASK 0x007c0000 +#define BTCOEXCTRL_FREQ_TIME_GET(x) (((x) & BTCOEXCTRL_FREQ_TIME_MASK) >> BTCOEXCTRL_FREQ_TIME_LSB) +#define BTCOEXCTRL_FREQ_TIME_SET(x) (((x) << BTCOEXCTRL_FREQ_TIME_LSB) & BTCOEXCTRL_FREQ_TIME_MASK) +#define BTCOEXCTRL_PRIORITY_TIME_MSB 17 +#define BTCOEXCTRL_PRIORITY_TIME_LSB 12 +#define BTCOEXCTRL_PRIORITY_TIME_MASK 0x0003f000 +#define BTCOEXCTRL_PRIORITY_TIME_GET(x) (((x) & BTCOEXCTRL_PRIORITY_TIME_MASK) >> BTCOEXCTRL_PRIORITY_TIME_LSB) +#define BTCOEXCTRL_PRIORITY_TIME_SET(x) (((x) << BTCOEXCTRL_PRIORITY_TIME_LSB) & BTCOEXCTRL_PRIORITY_TIME_MASK) +#define BTCOEXCTRL_SYNC_DET_EN_MSB 11 +#define BTCOEXCTRL_SYNC_DET_EN_LSB 11 +#define BTCOEXCTRL_SYNC_DET_EN_MASK 0x00000800 +#define BTCOEXCTRL_SYNC_DET_EN_GET(x) (((x) & BTCOEXCTRL_SYNC_DET_EN_MASK) >> BTCOEXCTRL_SYNC_DET_EN_LSB) +#define BTCOEXCTRL_SYNC_DET_EN_SET(x) (((x) << BTCOEXCTRL_SYNC_DET_EN_LSB) & BTCOEXCTRL_SYNC_DET_EN_MASK) +#define BTCOEXCTRL_IDLE_CNT_EN_MSB 10 +#define BTCOEXCTRL_IDLE_CNT_EN_LSB 10 +#define BTCOEXCTRL_IDLE_CNT_EN_MASK 0x00000400 +#define BTCOEXCTRL_IDLE_CNT_EN_GET(x) (((x) & BTCOEXCTRL_IDLE_CNT_EN_MASK) >> BTCOEXCTRL_IDLE_CNT_EN_LSB) +#define BTCOEXCTRL_IDLE_CNT_EN_SET(x) (((x) << BTCOEXCTRL_IDLE_CNT_EN_LSB) & BTCOEXCTRL_IDLE_CNT_EN_MASK) +#define BTCOEXCTRL_FRAME_CNT_EN_MSB 9 +#define BTCOEXCTRL_FRAME_CNT_EN_LSB 9 +#define BTCOEXCTRL_FRAME_CNT_EN_MASK 0x00000200 +#define BTCOEXCTRL_FRAME_CNT_EN_GET(x) (((x) & BTCOEXCTRL_FRAME_CNT_EN_MASK) >> BTCOEXCTRL_FRAME_CNT_EN_LSB) +#define BTCOEXCTRL_FRAME_CNT_EN_SET(x) (((x) << BTCOEXCTRL_FRAME_CNT_EN_LSB) & BTCOEXCTRL_FRAME_CNT_EN_MASK) +#define BTCOEXCTRL_CLK_CNT_EN_MSB 8 +#define BTCOEXCTRL_CLK_CNT_EN_LSB 8 +#define BTCOEXCTRL_CLK_CNT_EN_MASK 0x00000100 +#define BTCOEXCTRL_CLK_CNT_EN_GET(x) (((x) & BTCOEXCTRL_CLK_CNT_EN_MASK) >> BTCOEXCTRL_CLK_CNT_EN_LSB) +#define BTCOEXCTRL_CLK_CNT_EN_SET(x) (((x) << BTCOEXCTRL_CLK_CNT_EN_LSB) & BTCOEXCTRL_CLK_CNT_EN_MASK) +#define BTCOEXCTRL_GAP_MSB 7 +#define BTCOEXCTRL_GAP_LSB 0 +#define BTCOEXCTRL_GAP_MASK 0x000000ff +#define BTCOEXCTRL_GAP_GET(x) (((x) & BTCOEXCTRL_GAP_MASK) >> BTCOEXCTRL_GAP_LSB) +#define BTCOEXCTRL_GAP_SET(x) (((x) << BTCOEXCTRL_GAP_LSB) & BTCOEXCTRL_GAP_MASK) + +#define WBSYNC_PRIORITY1_ADDRESS 0x0000021c +#define WBSYNC_PRIORITY1_OFFSET 0x0000021c +#define WBSYNC_PRIORITY1_BITMAP_MSB 31 +#define WBSYNC_PRIORITY1_BITMAP_LSB 0 +#define WBSYNC_PRIORITY1_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY1_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY1_BITMAP_MASK) >> WBSYNC_PRIORITY1_BITMAP_LSB) +#define WBSYNC_PRIORITY1_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY1_BITMAP_LSB) & WBSYNC_PRIORITY1_BITMAP_MASK) + +#define WBSYNC_PRIORITY2_ADDRESS 0x00000220 +#define WBSYNC_PRIORITY2_OFFSET 0x00000220 +#define WBSYNC_PRIORITY2_BITMAP_MSB 31 +#define WBSYNC_PRIORITY2_BITMAP_LSB 0 +#define WBSYNC_PRIORITY2_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY2_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY2_BITMAP_MASK) >> WBSYNC_PRIORITY2_BITMAP_LSB) +#define WBSYNC_PRIORITY2_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY2_BITMAP_LSB) & WBSYNC_PRIORITY2_BITMAP_MASK) + +#define WBSYNC_PRIORITY3_ADDRESS 0x00000224 +#define WBSYNC_PRIORITY3_OFFSET 0x00000224 +#define WBSYNC_PRIORITY3_BITMAP_MSB 31 +#define WBSYNC_PRIORITY3_BITMAP_LSB 0 +#define WBSYNC_PRIORITY3_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY3_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY3_BITMAP_MASK) >> WBSYNC_PRIORITY3_BITMAP_LSB) +#define WBSYNC_PRIORITY3_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY3_BITMAP_LSB) & WBSYNC_PRIORITY3_BITMAP_MASK) + +#define BTCOEX0_ADDRESS 0x00000228 +#define BTCOEX0_OFFSET 0x00000228 +#define BTCOEX0_SYNC_DUR_MSB 7 +#define BTCOEX0_SYNC_DUR_LSB 0 +#define BTCOEX0_SYNC_DUR_MASK 0x000000ff +#define BTCOEX0_SYNC_DUR_GET(x) (((x) & BTCOEX0_SYNC_DUR_MASK) >> BTCOEX0_SYNC_DUR_LSB) +#define BTCOEX0_SYNC_DUR_SET(x) (((x) << BTCOEX0_SYNC_DUR_LSB) & BTCOEX0_SYNC_DUR_MASK) + +#define BTCOEX1_ADDRESS 0x0000022c +#define BTCOEX1_OFFSET 0x0000022c +#define BTCOEX1_CLK_THRES_MSB 20 +#define BTCOEX1_CLK_THRES_LSB 0 +#define BTCOEX1_CLK_THRES_MASK 0x001fffff +#define BTCOEX1_CLK_THRES_GET(x) (((x) & BTCOEX1_CLK_THRES_MASK) >> BTCOEX1_CLK_THRES_LSB) +#define BTCOEX1_CLK_THRES_SET(x) (((x) << BTCOEX1_CLK_THRES_LSB) & BTCOEX1_CLK_THRES_MASK) + +#define BTCOEX2_ADDRESS 0x00000230 +#define BTCOEX2_OFFSET 0x00000230 +#define BTCOEX2_FRAME_THRES_MSB 7 +#define BTCOEX2_FRAME_THRES_LSB 0 +#define BTCOEX2_FRAME_THRES_MASK 0x000000ff +#define BTCOEX2_FRAME_THRES_GET(x) (((x) & BTCOEX2_FRAME_THRES_MASK) >> BTCOEX2_FRAME_THRES_LSB) +#define BTCOEX2_FRAME_THRES_SET(x) (((x) << BTCOEX2_FRAME_THRES_LSB) & BTCOEX2_FRAME_THRES_MASK) + +#define BTCOEX3_ADDRESS 0x00000234 +#define BTCOEX3_OFFSET 0x00000234 +#define BTCOEX3_CLK_CNT_MSB 20 +#define BTCOEX3_CLK_CNT_LSB 0 +#define BTCOEX3_CLK_CNT_MASK 0x001fffff +#define BTCOEX3_CLK_CNT_GET(x) (((x) & BTCOEX3_CLK_CNT_MASK) >> BTCOEX3_CLK_CNT_LSB) +#define BTCOEX3_CLK_CNT_SET(x) (((x) << BTCOEX3_CLK_CNT_LSB) & BTCOEX3_CLK_CNT_MASK) + +#define BTCOEX4_ADDRESS 0x00000238 +#define BTCOEX4_OFFSET 0x00000238 +#define BTCOEX4_FRAME_CNT_MSB 7 +#define BTCOEX4_FRAME_CNT_LSB 0 +#define BTCOEX4_FRAME_CNT_MASK 0x000000ff +#define BTCOEX4_FRAME_CNT_GET(x) (((x) & BTCOEX4_FRAME_CNT_MASK) >> BTCOEX4_FRAME_CNT_LSB) +#define BTCOEX4_FRAME_CNT_SET(x) (((x) << BTCOEX4_FRAME_CNT_LSB) & BTCOEX4_FRAME_CNT_MASK) + +#define BTCOEX5_ADDRESS 0x0000023c +#define BTCOEX5_OFFSET 0x0000023c +#define BTCOEX5_IDLE_CNT_MSB 15 +#define BTCOEX5_IDLE_CNT_LSB 0 +#define BTCOEX5_IDLE_CNT_MASK 0x0000ffff +#define BTCOEX5_IDLE_CNT_GET(x) (((x) & BTCOEX5_IDLE_CNT_MASK) >> BTCOEX5_IDLE_CNT_LSB) +#define BTCOEX5_IDLE_CNT_SET(x) (((x) << BTCOEX5_IDLE_CNT_LSB) & BTCOEX5_IDLE_CNT_MASK) + +#define BTCOEX6_ADDRESS 0x00000240 +#define BTCOEX6_OFFSET 0x00000240 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MSB 31 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB 0 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK 0xffffffff +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_GET(x) (((x) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) >> BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_SET(x) (((x) << BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) + +#define LOCK_ADDRESS 0x00000244 +#define LOCK_OFFSET 0x00000244 +#define LOCK_TLOCK_SLAVE_MSB 31 +#define LOCK_TLOCK_SLAVE_LSB 24 +#define LOCK_TLOCK_SLAVE_MASK 0xff000000 +#define LOCK_TLOCK_SLAVE_GET(x) (((x) & LOCK_TLOCK_SLAVE_MASK) >> LOCK_TLOCK_SLAVE_LSB) +#define LOCK_TLOCK_SLAVE_SET(x) (((x) << LOCK_TLOCK_SLAVE_LSB) & LOCK_TLOCK_SLAVE_MASK) +#define LOCK_TUNLOCK_SLAVE_MSB 23 +#define LOCK_TUNLOCK_SLAVE_LSB 16 +#define LOCK_TUNLOCK_SLAVE_MASK 0x00ff0000 +#define LOCK_TUNLOCK_SLAVE_GET(x) (((x) & LOCK_TUNLOCK_SLAVE_MASK) >> LOCK_TUNLOCK_SLAVE_LSB) +#define LOCK_TUNLOCK_SLAVE_SET(x) (((x) << LOCK_TUNLOCK_SLAVE_LSB) & LOCK_TUNLOCK_SLAVE_MASK) +#define LOCK_TLOCK_MASTER_MSB 15 +#define LOCK_TLOCK_MASTER_LSB 8 +#define LOCK_TLOCK_MASTER_MASK 0x0000ff00 +#define LOCK_TLOCK_MASTER_GET(x) (((x) & LOCK_TLOCK_MASTER_MASK) >> LOCK_TLOCK_MASTER_LSB) +#define LOCK_TLOCK_MASTER_SET(x) (((x) << LOCK_TLOCK_MASTER_LSB) & LOCK_TLOCK_MASTER_MASK) +#define LOCK_TUNLOCK_MASTER_MSB 7 +#define LOCK_TUNLOCK_MASTER_LSB 0 +#define LOCK_TUNLOCK_MASTER_MASK 0x000000ff +#define LOCK_TUNLOCK_MASTER_GET(x) (((x) & LOCK_TUNLOCK_MASTER_MASK) >> LOCK_TUNLOCK_MASTER_LSB) +#define LOCK_TUNLOCK_MASTER_SET(x) (((x) << LOCK_TUNLOCK_MASTER_LSB) & LOCK_TUNLOCK_MASTER_MASK) + +#define NOLOCK_PRIORITY_ADDRESS 0x00000248 +#define NOLOCK_PRIORITY_OFFSET 0x00000248 +#define NOLOCK_PRIORITY_BITMAP_MSB 31 +#define NOLOCK_PRIORITY_BITMAP_LSB 0 +#define NOLOCK_PRIORITY_BITMAP_MASK 0xffffffff +#define NOLOCK_PRIORITY_BITMAP_GET(x) (((x) & NOLOCK_PRIORITY_BITMAP_MASK) >> NOLOCK_PRIORITY_BITMAP_LSB) +#define NOLOCK_PRIORITY_BITMAP_SET(x) (((x) << NOLOCK_PRIORITY_BITMAP_LSB) & NOLOCK_PRIORITY_BITMAP_MASK) + +#define WBSYNC_ADDRESS 0x0000024c +#define WBSYNC_OFFSET 0x0000024c +#define WBSYNC_BTCLOCK_MSB 31 +#define WBSYNC_BTCLOCK_LSB 0 +#define WBSYNC_BTCLOCK_MASK 0xffffffff +#define WBSYNC_BTCLOCK_GET(x) (((x) & WBSYNC_BTCLOCK_MASK) >> WBSYNC_BTCLOCK_LSB) +#define WBSYNC_BTCLOCK_SET(x) (((x) << WBSYNC_BTCLOCK_LSB) & WBSYNC_BTCLOCK_MASK) + +#define WBSYNC1_ADDRESS 0x00000250 +#define WBSYNC1_OFFSET 0x00000250 +#define WBSYNC1_BTCLOCK_MSB 31 +#define WBSYNC1_BTCLOCK_LSB 0 +#define WBSYNC1_BTCLOCK_MASK 0xffffffff +#define WBSYNC1_BTCLOCK_GET(x) (((x) & WBSYNC1_BTCLOCK_MASK) >> WBSYNC1_BTCLOCK_LSB) +#define WBSYNC1_BTCLOCK_SET(x) (((x) << WBSYNC1_BTCLOCK_LSB) & WBSYNC1_BTCLOCK_MASK) + +#define WBSYNC2_ADDRESS 0x00000254 +#define WBSYNC2_OFFSET 0x00000254 +#define WBSYNC2_BTCLOCK_MSB 31 +#define WBSYNC2_BTCLOCK_LSB 0 +#define WBSYNC2_BTCLOCK_MASK 0xffffffff +#define WBSYNC2_BTCLOCK_GET(x) (((x) & WBSYNC2_BTCLOCK_MASK) >> WBSYNC2_BTCLOCK_LSB) +#define WBSYNC2_BTCLOCK_SET(x) (((x) << WBSYNC2_BTCLOCK_LSB) & WBSYNC2_BTCLOCK_MASK) + +#define WBSYNC3_ADDRESS 0x00000258 +#define WBSYNC3_OFFSET 0x00000258 +#define WBSYNC3_BTCLOCK_MSB 31 +#define WBSYNC3_BTCLOCK_LSB 0 +#define WBSYNC3_BTCLOCK_MASK 0xffffffff +#define WBSYNC3_BTCLOCK_GET(x) (((x) & WBSYNC3_BTCLOCK_MASK) >> WBSYNC3_BTCLOCK_LSB) +#define WBSYNC3_BTCLOCK_SET(x) (((x) << WBSYNC3_BTCLOCK_LSB) & WBSYNC3_BTCLOCK_MASK) + +#define WB_TIMER_TARGET_ADDRESS 0x0000025c +#define WB_TIMER_TARGET_OFFSET 0x0000025c +#define WB_TIMER_TARGET_VALUE_MSB 31 +#define WB_TIMER_TARGET_VALUE_LSB 0 +#define WB_TIMER_TARGET_VALUE_MASK 0xffffffff +#define WB_TIMER_TARGET_VALUE_GET(x) (((x) & WB_TIMER_TARGET_VALUE_MASK) >> WB_TIMER_TARGET_VALUE_LSB) +#define WB_TIMER_TARGET_VALUE_SET(x) (((x) << WB_TIMER_TARGET_VALUE_LSB) & WB_TIMER_TARGET_VALUE_MASK) + +#define WB_TIMER_SLOP_ADDRESS 0x00000260 +#define WB_TIMER_SLOP_OFFSET 0x00000260 +#define WB_TIMER_SLOP_VALUE_MSB 9 +#define WB_TIMER_SLOP_VALUE_LSB 0 +#define WB_TIMER_SLOP_VALUE_MASK 0x000003ff +#define WB_TIMER_SLOP_VALUE_GET(x) (((x) & WB_TIMER_SLOP_VALUE_MASK) >> WB_TIMER_SLOP_VALUE_LSB) +#define WB_TIMER_SLOP_VALUE_SET(x) (((x) << WB_TIMER_SLOP_VALUE_LSB) & WB_TIMER_SLOP_VALUE_MASK) + +#define BTCOEX_INT_EN_ADDRESS 0x00000264 +#define BTCOEX_INT_EN_OFFSET 0x00000264 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MSB 11 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB 11 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK 0x00000800 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) +#define BTCOEX_INT_EN_I2C_TX_FAILED_MSB 10 +#define BTCOEX_INT_EN_I2C_TX_FAILED_LSB 10 +#define BTCOEX_INT_EN_I2C_TX_FAILED_MASK 0x00000400 +#define BTCOEX_INT_EN_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) >> BTCOEX_INT_EN_I2C_TX_FAILED_LSB) +#define BTCOEX_INT_EN_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_EN_I2C_TX_FAILED_LSB) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) +#define BTCOEX_INT_EN_I2C_MESG_SENT_MSB 9 +#define BTCOEX_INT_EN_I2C_MESG_SENT_LSB 9 +#define BTCOEX_INT_EN_I2C_MESG_SENT_MASK 0x00000200 +#define BTCOEX_INT_EN_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) >> BTCOEX_INT_EN_I2C_MESG_SENT_LSB) +#define BTCOEX_INT_EN_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_EN_I2C_MESG_SENT_LSB) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) +#define BTCOEX_INT_EN_ST_MESG_RECV_MSB 8 +#define BTCOEX_INT_EN_ST_MESG_RECV_LSB 8 +#define BTCOEX_INT_EN_ST_MESG_RECV_MASK 0x00000100 +#define BTCOEX_INT_EN_ST_MESG_RECV_GET(x) (((x) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) >> BTCOEX_INT_EN_ST_MESG_RECV_LSB) +#define BTCOEX_INT_EN_ST_MESG_RECV_SET(x) (((x) << BTCOEX_INT_EN_ST_MESG_RECV_LSB) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) +#define BTCOEX_INT_EN_WB_TIMER_MSB 7 +#define BTCOEX_INT_EN_WB_TIMER_LSB 7 +#define BTCOEX_INT_EN_WB_TIMER_MASK 0x00000080 +#define BTCOEX_INT_EN_WB_TIMER_GET(x) (((x) & BTCOEX_INT_EN_WB_TIMER_MASK) >> BTCOEX_INT_EN_WB_TIMER_LSB) +#define BTCOEX_INT_EN_WB_TIMER_SET(x) (((x) << BTCOEX_INT_EN_WB_TIMER_LSB) & BTCOEX_INT_EN_WB_TIMER_MASK) +#define BTCOEX_INT_EN_NOSYNC_MSB 4 +#define BTCOEX_INT_EN_NOSYNC_LSB 4 +#define BTCOEX_INT_EN_NOSYNC_MASK 0x00000010 +#define BTCOEX_INT_EN_NOSYNC_GET(x) (((x) & BTCOEX_INT_EN_NOSYNC_MASK) >> BTCOEX_INT_EN_NOSYNC_LSB) +#define BTCOEX_INT_EN_NOSYNC_SET(x) (((x) << BTCOEX_INT_EN_NOSYNC_LSB) & BTCOEX_INT_EN_NOSYNC_MASK) +#define BTCOEX_INT_EN_SYNC_MSB 3 +#define BTCOEX_INT_EN_SYNC_LSB 3 +#define BTCOEX_INT_EN_SYNC_MASK 0x00000008 +#define BTCOEX_INT_EN_SYNC_GET(x) (((x) & BTCOEX_INT_EN_SYNC_MASK) >> BTCOEX_INT_EN_SYNC_LSB) +#define BTCOEX_INT_EN_SYNC_SET(x) (((x) << BTCOEX_INT_EN_SYNC_LSB) & BTCOEX_INT_EN_SYNC_MASK) +#define BTCOEX_INT_EN_END_MSB 2 +#define BTCOEX_INT_EN_END_LSB 2 +#define BTCOEX_INT_EN_END_MASK 0x00000004 +#define BTCOEX_INT_EN_END_GET(x) (((x) & BTCOEX_INT_EN_END_MASK) >> BTCOEX_INT_EN_END_LSB) +#define BTCOEX_INT_EN_END_SET(x) (((x) << BTCOEX_INT_EN_END_LSB) & BTCOEX_INT_EN_END_MASK) +#define BTCOEX_INT_EN_FRAME_CNT_MSB 1 +#define BTCOEX_INT_EN_FRAME_CNT_LSB 1 +#define BTCOEX_INT_EN_FRAME_CNT_MASK 0x00000002 +#define BTCOEX_INT_EN_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_EN_FRAME_CNT_MASK) >> BTCOEX_INT_EN_FRAME_CNT_LSB) +#define BTCOEX_INT_EN_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_EN_FRAME_CNT_LSB) & BTCOEX_INT_EN_FRAME_CNT_MASK) +#define BTCOEX_INT_EN_CLK_CNT_MSB 0 +#define BTCOEX_INT_EN_CLK_CNT_LSB 0 +#define BTCOEX_INT_EN_CLK_CNT_MASK 0x00000001 +#define BTCOEX_INT_EN_CLK_CNT_GET(x) (((x) & BTCOEX_INT_EN_CLK_CNT_MASK) >> BTCOEX_INT_EN_CLK_CNT_LSB) +#define BTCOEX_INT_EN_CLK_CNT_SET(x) (((x) << BTCOEX_INT_EN_CLK_CNT_LSB) & BTCOEX_INT_EN_CLK_CNT_MASK) + +#define BTCOEX_INT_STAT_ADDRESS 0x00000268 +#define BTCOEX_INT_STAT_OFFSET 0x00000268 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MSB 11 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB 11 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK 0x00000800 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) +#define BTCOEX_INT_STAT_I2C_TX_FAILED_MSB 10 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_LSB 10 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_MASK 0x00000400 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) >> BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) +#define BTCOEX_INT_STAT_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) +#define BTCOEX_INT_STAT_I2C_MESG_SENT_MSB 9 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_LSB 9 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_MASK 0x00000200 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) >> BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) +#define BTCOEX_INT_STAT_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) +#define BTCOEX_INT_STAT_I2C_MESG_RECV_MSB 8 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_LSB 8 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_MASK 0x00000100 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) >> BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) +#define BTCOEX_INT_STAT_I2C_MESG_RECV_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) +#define BTCOEX_INT_STAT_WB_TIMER_MSB 7 +#define BTCOEX_INT_STAT_WB_TIMER_LSB 7 +#define BTCOEX_INT_STAT_WB_TIMER_MASK 0x00000080 +#define BTCOEX_INT_STAT_WB_TIMER_GET(x) (((x) & BTCOEX_INT_STAT_WB_TIMER_MASK) >> BTCOEX_INT_STAT_WB_TIMER_LSB) +#define BTCOEX_INT_STAT_WB_TIMER_SET(x) (((x) << BTCOEX_INT_STAT_WB_TIMER_LSB) & BTCOEX_INT_STAT_WB_TIMER_MASK) +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MSB 6 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB 6 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK 0x00000040 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) +#define BTCOEX_INT_STAT_BTPRIORITY_MSB 5 +#define BTCOEX_INT_STAT_BTPRIORITY_LSB 5 +#define BTCOEX_INT_STAT_BTPRIORITY_MASK 0x00000020 +#define BTCOEX_INT_STAT_BTPRIORITY_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_LSB) +#define BTCOEX_INT_STAT_BTPRIORITY_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_LSB) & BTCOEX_INT_STAT_BTPRIORITY_MASK) +#define BTCOEX_INT_STAT_NOSYNC_MSB 4 +#define BTCOEX_INT_STAT_NOSYNC_LSB 4 +#define BTCOEX_INT_STAT_NOSYNC_MASK 0x00000010 +#define BTCOEX_INT_STAT_NOSYNC_GET(x) (((x) & BTCOEX_INT_STAT_NOSYNC_MASK) >> BTCOEX_INT_STAT_NOSYNC_LSB) +#define BTCOEX_INT_STAT_NOSYNC_SET(x) (((x) << BTCOEX_INT_STAT_NOSYNC_LSB) & BTCOEX_INT_STAT_NOSYNC_MASK) +#define BTCOEX_INT_STAT_SYNC_MSB 3 +#define BTCOEX_INT_STAT_SYNC_LSB 3 +#define BTCOEX_INT_STAT_SYNC_MASK 0x00000008 +#define BTCOEX_INT_STAT_SYNC_GET(x) (((x) & BTCOEX_INT_STAT_SYNC_MASK) >> BTCOEX_INT_STAT_SYNC_LSB) +#define BTCOEX_INT_STAT_SYNC_SET(x) (((x) << BTCOEX_INT_STAT_SYNC_LSB) & BTCOEX_INT_STAT_SYNC_MASK) +#define BTCOEX_INT_STAT_END_MSB 2 +#define BTCOEX_INT_STAT_END_LSB 2 +#define BTCOEX_INT_STAT_END_MASK 0x00000004 +#define BTCOEX_INT_STAT_END_GET(x) (((x) & BTCOEX_INT_STAT_END_MASK) >> BTCOEX_INT_STAT_END_LSB) +#define BTCOEX_INT_STAT_END_SET(x) (((x) << BTCOEX_INT_STAT_END_LSB) & BTCOEX_INT_STAT_END_MASK) +#define BTCOEX_INT_STAT_FRAME_CNT_MSB 1 +#define BTCOEX_INT_STAT_FRAME_CNT_LSB 1 +#define BTCOEX_INT_STAT_FRAME_CNT_MASK 0x00000002 +#define BTCOEX_INT_STAT_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_STAT_FRAME_CNT_MASK) >> BTCOEX_INT_STAT_FRAME_CNT_LSB) +#define BTCOEX_INT_STAT_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_STAT_FRAME_CNT_LSB) & BTCOEX_INT_STAT_FRAME_CNT_MASK) +#define BTCOEX_INT_STAT_CLK_CNT_MSB 0 +#define BTCOEX_INT_STAT_CLK_CNT_LSB 0 +#define BTCOEX_INT_STAT_CLK_CNT_MASK 0x00000001 +#define BTCOEX_INT_STAT_CLK_CNT_GET(x) (((x) & BTCOEX_INT_STAT_CLK_CNT_MASK) >> BTCOEX_INT_STAT_CLK_CNT_LSB) +#define BTCOEX_INT_STAT_CLK_CNT_SET(x) (((x) << BTCOEX_INT_STAT_CLK_CNT_LSB) & BTCOEX_INT_STAT_CLK_CNT_MASK) + +#define BTPRIORITY_INT_EN_ADDRESS 0x0000026c +#define BTPRIORITY_INT_EN_OFFSET 0x0000026c +#define BTPRIORITY_INT_EN_BITMAP_MSB 31 +#define BTPRIORITY_INT_EN_BITMAP_LSB 0 +#define BTPRIORITY_INT_EN_BITMAP_MASK 0xffffffff +#define BTPRIORITY_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_INT_EN_BITMAP_MASK) >> BTPRIORITY_INT_EN_BITMAP_LSB) +#define BTPRIORITY_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_INT_EN_BITMAP_LSB) & BTPRIORITY_INT_EN_BITMAP_MASK) + +#define BTPRIORITY_INT_STAT_ADDRESS 0x00000270 +#define BTPRIORITY_INT_STAT_OFFSET 0x00000270 +#define BTPRIORITY_INT_STAT_BITMAP_MSB 31 +#define BTPRIORITY_INT_STAT_BITMAP_LSB 0 +#define BTPRIORITY_INT_STAT_BITMAP_MASK 0xffffffff +#define BTPRIORITY_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_INT_STAT_BITMAP_MASK) >> BTPRIORITY_INT_STAT_BITMAP_LSB) +#define BTPRIORITY_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_INT_STAT_BITMAP_LSB) & BTPRIORITY_INT_STAT_BITMAP_MASK) + +#define BTPRIORITY_STOMP_INT_EN_ADDRESS 0x00000274 +#define BTPRIORITY_STOMP_INT_EN_OFFSET 0x00000274 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_MSB 31 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_LSB 0 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_MASK 0xffffffff +#define BTPRIORITY_STOMP_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) +#define BTPRIORITY_STOMP_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) + +#define BTPRIORITY_STOMP_INT_STAT_ADDRESS 0x00000278 +#define BTPRIORITY_STOMP_INT_STAT_OFFSET 0x00000278 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MSB 31 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB 0 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK 0xffffffff +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) + +#define MAC_PCU_BMISS_TIMEOUT_ADDRESS 0x0000027c +#define MAC_PCU_BMISS_TIMEOUT_OFFSET 0x0000027c +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_BMISS_TIMEOUT_VALUE_MSB 23 +#define MAC_PCU_BMISS_TIMEOUT_VALUE_LSB 0 +#define MAC_PCU_BMISS_TIMEOUT_VALUE_MASK 0x00ffffff +#define MAC_PCU_BMISS_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) >> MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) +#define MAC_PCU_BMISS_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) + +#define MAC_PCU_CAB_AWAKE_ADDRESS 0x00000280 +#define MAC_PCU_CAB_AWAKE_OFFSET 0x00000280 +#define MAC_PCU_CAB_AWAKE_ENABLE_MSB 16 +#define MAC_PCU_CAB_AWAKE_ENABLE_LSB 16 +#define MAC_PCU_CAB_AWAKE_ENABLE_MASK 0x00010000 +#define MAC_PCU_CAB_AWAKE_ENABLE_GET(x) (((x) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) >> MAC_PCU_CAB_AWAKE_ENABLE_LSB) +#define MAC_PCU_CAB_AWAKE_ENABLE_SET(x) (((x) << MAC_PCU_CAB_AWAKE_ENABLE_LSB) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) +#define MAC_PCU_CAB_AWAKE_DURATION_MSB 15 +#define MAC_PCU_CAB_AWAKE_DURATION_LSB 0 +#define MAC_PCU_CAB_AWAKE_DURATION_MASK 0x0000ffff +#define MAC_PCU_CAB_AWAKE_DURATION_GET(x) (((x) & MAC_PCU_CAB_AWAKE_DURATION_MASK) >> MAC_PCU_CAB_AWAKE_DURATION_LSB) +#define MAC_PCU_CAB_AWAKE_DURATION_SET(x) (((x) << MAC_PCU_CAB_AWAKE_DURATION_LSB) & MAC_PCU_CAB_AWAKE_DURATION_MASK) + +#define LP_PERF_COUNTER_ADDRESS 0x00000284 +#define LP_PERF_COUNTER_OFFSET 0x00000284 +#define LP_PERF_COUNTER_EN_MSB 0 +#define LP_PERF_COUNTER_EN_LSB 0 +#define LP_PERF_COUNTER_EN_MASK 0x00000001 +#define LP_PERF_COUNTER_EN_GET(x) (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB) +#define LP_PERF_COUNTER_EN_SET(x) (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK) + +#define LP_PERF_LIGHT_SLEEP_ADDRESS 0x00000288 +#define LP_PERF_LIGHT_SLEEP_OFFSET 0x00000288 +#define LP_PERF_LIGHT_SLEEP_CNT_MSB 31 +#define LP_PERF_LIGHT_SLEEP_CNT_LSB 0 +#define LP_PERF_LIGHT_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_LIGHT_SLEEP_CNT_GET(x) (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB) +#define LP_PERF_LIGHT_SLEEP_CNT_SET(x) (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK) + +#define LP_PERF_DEEP_SLEEP_ADDRESS 0x0000028c +#define LP_PERF_DEEP_SLEEP_OFFSET 0x0000028c +#define LP_PERF_DEEP_SLEEP_CNT_MSB 31 +#define LP_PERF_DEEP_SLEEP_CNT_LSB 0 +#define LP_PERF_DEEP_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_DEEP_SLEEP_CNT_GET(x) (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB) +#define LP_PERF_DEEP_SLEEP_CNT_SET(x) (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK) + +#define LP_PERF_ON_ADDRESS 0x00000290 +#define LP_PERF_ON_OFFSET 0x00000290 +#define LP_PERF_ON_CNT_MSB 31 +#define LP_PERF_ON_CNT_LSB 0 +#define LP_PERF_ON_CNT_MASK 0xffffffff +#define LP_PERF_ON_CNT_GET(x) (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB) +#define LP_PERF_ON_CNT_SET(x) (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK) + +#define ST_64_BIT_ADDRESS 0x00000294 +#define ST_64_BIT_OFFSET 0x00000294 +#define ST_64_BIT_TIMEOUT_MSB 26 +#define ST_64_BIT_TIMEOUT_LSB 9 +#define ST_64_BIT_TIMEOUT_MASK 0x07fffe00 +#define ST_64_BIT_TIMEOUT_GET(x) (((x) & ST_64_BIT_TIMEOUT_MASK) >> ST_64_BIT_TIMEOUT_LSB) +#define ST_64_BIT_TIMEOUT_SET(x) (((x) << ST_64_BIT_TIMEOUT_LSB) & ST_64_BIT_TIMEOUT_MASK) +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MSB 8 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB 8 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK 0x00000100 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_GET(x) (((x) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) >> ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_SET(x) (((x) << ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) +#define ST_64_BIT_DRIVE_MODE_MSB 7 +#define ST_64_BIT_DRIVE_MODE_LSB 7 +#define ST_64_BIT_DRIVE_MODE_MASK 0x00000080 +#define ST_64_BIT_DRIVE_MODE_GET(x) (((x) & ST_64_BIT_DRIVE_MODE_MASK) >> ST_64_BIT_DRIVE_MODE_LSB) +#define ST_64_BIT_DRIVE_MODE_SET(x) (((x) << ST_64_BIT_DRIVE_MODE_LSB) & ST_64_BIT_DRIVE_MODE_MASK) +#define ST_64_BIT_CLOCK_GATE_MSB 6 +#define ST_64_BIT_CLOCK_GATE_LSB 6 +#define ST_64_BIT_CLOCK_GATE_MASK 0x00000040 +#define ST_64_BIT_CLOCK_GATE_GET(x) (((x) & ST_64_BIT_CLOCK_GATE_MASK) >> ST_64_BIT_CLOCK_GATE_LSB) +#define ST_64_BIT_CLOCK_GATE_SET(x) (((x) << ST_64_BIT_CLOCK_GATE_LSB) & ST_64_BIT_CLOCK_GATE_MASK) +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MSB 5 +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB 1 +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK 0x0000003e +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_GET(x) (((x) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) >> ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_SET(x) (((x) << ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) +#define ST_64_BIT_MODE_MSB 0 +#define ST_64_BIT_MODE_LSB 0 +#define ST_64_BIT_MODE_MASK 0x00000001 +#define ST_64_BIT_MODE_GET(x) (((x) & ST_64_BIT_MODE_MASK) >> ST_64_BIT_MODE_LSB) +#define ST_64_BIT_MODE_SET(x) (((x) << ST_64_BIT_MODE_LSB) & ST_64_BIT_MODE_MASK) + +#define MESSAGE_WR_ADDRESS 0x00000298 +#define MESSAGE_WR_OFFSET 0x00000298 +#define MESSAGE_WR_TYPE_MSB 31 +#define MESSAGE_WR_TYPE_LSB 0 +#define MESSAGE_WR_TYPE_MASK 0xffffffff +#define MESSAGE_WR_TYPE_GET(x) (((x) & MESSAGE_WR_TYPE_MASK) >> MESSAGE_WR_TYPE_LSB) +#define MESSAGE_WR_TYPE_SET(x) (((x) << MESSAGE_WR_TYPE_LSB) & MESSAGE_WR_TYPE_MASK) + +#define MESSAGE_WR_P_ADDRESS 0x0000029c +#define MESSAGE_WR_P_OFFSET 0x0000029c +#define MESSAGE_WR_P_PARAMETER_MSB 31 +#define MESSAGE_WR_P_PARAMETER_LSB 0 +#define MESSAGE_WR_P_PARAMETER_MASK 0xffffffff +#define MESSAGE_WR_P_PARAMETER_GET(x) (((x) & MESSAGE_WR_P_PARAMETER_MASK) >> MESSAGE_WR_P_PARAMETER_LSB) +#define MESSAGE_WR_P_PARAMETER_SET(x) (((x) << MESSAGE_WR_P_PARAMETER_LSB) & MESSAGE_WR_P_PARAMETER_MASK) + +#define MESSAGE_RD_ADDRESS 0x000002a0 +#define MESSAGE_RD_OFFSET 0x000002a0 +#define MESSAGE_RD_TYPE_MSB 31 +#define MESSAGE_RD_TYPE_LSB 0 +#define MESSAGE_RD_TYPE_MASK 0xffffffff +#define MESSAGE_RD_TYPE_GET(x) (((x) & MESSAGE_RD_TYPE_MASK) >> MESSAGE_RD_TYPE_LSB) +#define MESSAGE_RD_TYPE_SET(x) (((x) << MESSAGE_RD_TYPE_LSB) & MESSAGE_RD_TYPE_MASK) + +#define MESSAGE_RD_P_ADDRESS 0x000002a4 +#define MESSAGE_RD_P_OFFSET 0x000002a4 +#define MESSAGE_RD_P_PARAMETER_MSB 31 +#define MESSAGE_RD_P_PARAMETER_LSB 0 +#define MESSAGE_RD_P_PARAMETER_MASK 0xffffffff +#define MESSAGE_RD_P_PARAMETER_GET(x) (((x) & MESSAGE_RD_P_PARAMETER_MASK) >> MESSAGE_RD_P_PARAMETER_LSB) +#define MESSAGE_RD_P_PARAMETER_SET(x) (((x) << MESSAGE_RD_P_PARAMETER_LSB) & MESSAGE_RD_P_PARAMETER_MASK) + +#define CHIP_MODE_ADDRESS 0x000002a8 +#define CHIP_MODE_OFFSET 0x000002a8 +#define CHIP_MODE_BIT_MSB 1 +#define CHIP_MODE_BIT_LSB 0 +#define CHIP_MODE_BIT_MASK 0x00000003 +#define CHIP_MODE_BIT_GET(x) (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB) +#define CHIP_MODE_BIT_SET(x) (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK) + +#define CLK_REQ_FALL_EDGE_ADDRESS 0x000002ac +#define CLK_REQ_FALL_EDGE_OFFSET 0x000002ac +#define CLK_REQ_FALL_EDGE_EN_MSB 31 +#define CLK_REQ_FALL_EDGE_EN_LSB 31 +#define CLK_REQ_FALL_EDGE_EN_MASK 0x80000000 +#define CLK_REQ_FALL_EDGE_EN_GET(x) (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB) +#define CLK_REQ_FALL_EDGE_EN_SET(x) (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK) +#define CLK_REQ_FALL_EDGE_DELAY_MSB 7 +#define CLK_REQ_FALL_EDGE_DELAY_LSB 0 +#define CLK_REQ_FALL_EDGE_DELAY_MASK 0x000000ff +#define CLK_REQ_FALL_EDGE_DELAY_GET(x) (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB) +#define CLK_REQ_FALL_EDGE_DELAY_SET(x) (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK) + +#define OTP_ADDRESS 0x000002b0 +#define OTP_OFFSET 0x000002b0 +#define OTP_LDO25_EN_MSB 1 +#define OTP_LDO25_EN_LSB 1 +#define OTP_LDO25_EN_MASK 0x00000002 +#define OTP_LDO25_EN_GET(x) (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB) +#define OTP_LDO25_EN_SET(x) (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK) +#define OTP_VDD12_EN_MSB 0 +#define OTP_VDD12_EN_LSB 0 +#define OTP_VDD12_EN_MASK 0x00000001 +#define OTP_VDD12_EN_GET(x) (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB) +#define OTP_VDD12_EN_SET(x) (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK) + +#define OTP_STATUS_ADDRESS 0x000002b4 +#define OTP_STATUS_OFFSET 0x000002b4 +#define OTP_STATUS_LDO25_EN_READY_MSB 1 +#define OTP_STATUS_LDO25_EN_READY_LSB 1 +#define OTP_STATUS_LDO25_EN_READY_MASK 0x00000002 +#define OTP_STATUS_LDO25_EN_READY_GET(x) (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB) +#define OTP_STATUS_LDO25_EN_READY_SET(x) (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK) +#define OTP_STATUS_VDD12_EN_READY_MSB 0 +#define OTP_STATUS_VDD12_EN_READY_LSB 0 +#define OTP_STATUS_VDD12_EN_READY_MASK 0x00000001 +#define OTP_STATUS_VDD12_EN_READY_GET(x) (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB) +#define OTP_STATUS_VDD12_EN_READY_SET(x) (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK) + +#define PMU_ADDRESS 0x000002b8 +#define PMU_OFFSET 0x000002b8 +#define PMU_REG_WAKEUP_TIME_SEL_MSB 1 +#define PMU_REG_WAKEUP_TIME_SEL_LSB 0 +#define PMU_REG_WAKEUP_TIME_SEL_MASK 0x00000003 +#define PMU_REG_WAKEUP_TIME_SEL_GET(x) (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB) +#define PMU_REG_WAKEUP_TIME_SEL_SET(x) (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK) + +#define PMU_CONFIG_ADDRESS 0x000002c0 +#define PMU_CONFIG_OFFSET 0x000002c0 +#define PMU_CONFIG_VALUE_MSB 15 +#define PMU_CONFIG_VALUE_LSB 0 +#define PMU_CONFIG_VALUE_MASK 0x0000ffff +#define PMU_CONFIG_VALUE_GET(x) (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB) +#define PMU_CONFIG_VALUE_SET(x) (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK) + +#define PMU_BYPASS_ADDRESS 0x000002c8 +#define PMU_BYPASS_OFFSET 0x000002c8 +#define PMU_BYPASS_SWREG_MSB 2 +#define PMU_BYPASS_SWREG_LSB 2 +#define PMU_BYPASS_SWREG_MASK 0x00000004 +#define PMU_BYPASS_SWREG_GET(x) (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB) +#define PMU_BYPASS_SWREG_SET(x) (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK) +#define PMU_BYPASS_DREG_MSB 1 +#define PMU_BYPASS_DREG_LSB 1 +#define PMU_BYPASS_DREG_MASK 0x00000002 +#define PMU_BYPASS_DREG_GET(x) (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB) +#define PMU_BYPASS_DREG_SET(x) (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK) +#define PMU_BYPASS_PAREG_MSB 0 +#define PMU_BYPASS_PAREG_LSB 0 +#define PMU_BYPASS_PAREG_MASK 0x00000001 +#define PMU_BYPASS_PAREG_GET(x) (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB) +#define PMU_BYPASS_PAREG_SET(x) (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK) + +#define MAC_PCU_TSF2_L32_ADDRESS 0x000002cc +#define MAC_PCU_TSF2_L32_OFFSET 0x000002cc +#define MAC_PCU_TSF2_L32_VALUE_MSB 31 +#define MAC_PCU_TSF2_L32_VALUE_LSB 0 +#define MAC_PCU_TSF2_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_L32_VALUE_MASK) >> MAC_PCU_TSF2_L32_VALUE_LSB) +#define MAC_PCU_TSF2_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_L32_VALUE_LSB) & MAC_PCU_TSF2_L32_VALUE_MASK) + +#define MAC_PCU_TSF2_U32_ADDRESS 0x000002d0 +#define MAC_PCU_TSF2_U32_OFFSET 0x000002d0 +#define MAC_PCU_TSF2_U32_VALUE_MSB 31 +#define MAC_PCU_TSF2_U32_VALUE_LSB 0 +#define MAC_PCU_TSF2_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_U32_VALUE_MASK) >> MAC_PCU_TSF2_U32_VALUE_LSB) +#define MAC_PCU_TSF2_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_U32_VALUE_LSB) & MAC_PCU_TSF2_U32_VALUE_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE3_ADDRESS 0x000002d4 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OFFSET 0x000002d4 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MSB 27 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB 24 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK 0x0f000000 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MSB 19 +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK 0x000fffff +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) + +#define MAC_PCU_DIRECT_CONNECT_ADDRESS 0x000002d8 +#define MAC_PCU_DIRECT_CONNECT_OFFSET 0x000002d8 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MSB 2 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB 2 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK 0x00000004 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MSB 1 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB 1 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK 0x00000002 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MSB 0 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB 0 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK 0x00000001 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) + +#define THERM_CTRL1_ADDRESS 0x000002dc +#define THERM_CTRL1_OFFSET 0x000002dc +#define THERM_CTRL1_BYPASS_MSB 16 +#define THERM_CTRL1_BYPASS_LSB 16 +#define THERM_CTRL1_BYPASS_MASK 0x00010000 +#define THERM_CTRL1_BYPASS_GET(x) (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB) +#define THERM_CTRL1_BYPASS_SET(x) (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK) +#define THERM_CTRL1_WIDTH_ARBITOR_MSB 15 +#define THERM_CTRL1_WIDTH_ARBITOR_LSB 12 +#define THERM_CTRL1_WIDTH_ARBITOR_MASK 0x0000f000 +#define THERM_CTRL1_WIDTH_ARBITOR_GET(x) (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB) +#define THERM_CTRL1_WIDTH_ARBITOR_SET(x) (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK) +#define THERM_CTRL1_WIDTH_MSB 11 +#define THERM_CTRL1_WIDTH_LSB 5 +#define THERM_CTRL1_WIDTH_MASK 0x00000fe0 +#define THERM_CTRL1_WIDTH_GET(x) (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB) +#define THERM_CTRL1_WIDTH_SET(x) (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK) +#define THERM_CTRL1_TYPE_MSB 4 +#define THERM_CTRL1_TYPE_LSB 3 +#define THERM_CTRL1_TYPE_MASK 0x00000018 +#define THERM_CTRL1_TYPE_GET(x) (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB) +#define THERM_CTRL1_TYPE_SET(x) (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK) +#define THERM_CTRL1_MEASURE_MSB 2 +#define THERM_CTRL1_MEASURE_LSB 2 +#define THERM_CTRL1_MEASURE_MASK 0x00000004 +#define THERM_CTRL1_MEASURE_GET(x) (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB) +#define THERM_CTRL1_MEASURE_SET(x) (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK) +#define THERM_CTRL1_INT_EN_MSB 1 +#define THERM_CTRL1_INT_EN_LSB 1 +#define THERM_CTRL1_INT_EN_MASK 0x00000002 +#define THERM_CTRL1_INT_EN_GET(x) (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB) +#define THERM_CTRL1_INT_EN_SET(x) (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK) +#define THERM_CTRL1_INT_STATUS_MSB 0 +#define THERM_CTRL1_INT_STATUS_LSB 0 +#define THERM_CTRL1_INT_STATUS_MASK 0x00000001 +#define THERM_CTRL1_INT_STATUS_GET(x) (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB) +#define THERM_CTRL1_INT_STATUS_SET(x) (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK) + +#define THERM_CTRL2_ADDRESS 0x000002e0 +#define THERM_CTRL2_OFFSET 0x000002e0 +#define THERM_CTRL2_ADC_OFF_MSB 25 +#define THERM_CTRL2_ADC_OFF_LSB 25 +#define THERM_CTRL2_ADC_OFF_MASK 0x02000000 +#define THERM_CTRL2_ADC_OFF_GET(x) (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB) +#define THERM_CTRL2_ADC_OFF_SET(x) (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK) +#define THERM_CTRL2_ADC_ON_MSB 24 +#define THERM_CTRL2_ADC_ON_LSB 24 +#define THERM_CTRL2_ADC_ON_MASK 0x01000000 +#define THERM_CTRL2_ADC_ON_GET(x) (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB) +#define THERM_CTRL2_ADC_ON_SET(x) (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK) +#define THERM_CTRL2_SAMPLE_MSB 23 +#define THERM_CTRL2_SAMPLE_LSB 16 +#define THERM_CTRL2_SAMPLE_MASK 0x00ff0000 +#define THERM_CTRL2_SAMPLE_GET(x) (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB) +#define THERM_CTRL2_SAMPLE_SET(x) (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK) +#define THERM_CTRL2_HIGH_MSB 15 +#define THERM_CTRL2_HIGH_LSB 8 +#define THERM_CTRL2_HIGH_MASK 0x0000ff00 +#define THERM_CTRL2_HIGH_GET(x) (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB) +#define THERM_CTRL2_HIGH_SET(x) (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK) +#define THERM_CTRL2_LOW_MSB 7 +#define THERM_CTRL2_LOW_LSB 0 +#define THERM_CTRL2_LOW_MASK 0x000000ff +#define THERM_CTRL2_LOW_GET(x) (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB) +#define THERM_CTRL2_LOW_SET(x) (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK) + +#define THERM_CTRL3_ADDRESS 0x000002e4 +#define THERM_CTRL3_OFFSET 0x000002e4 +#define THERM_CTRL3_ADC_GAIN_MSB 16 +#define THERM_CTRL3_ADC_GAIN_LSB 8 +#define THERM_CTRL3_ADC_GAIN_MASK 0x0001ff00 +#define THERM_CTRL3_ADC_GAIN_GET(x) (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB) +#define THERM_CTRL3_ADC_GAIN_SET(x) (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK) +#define THERM_CTRL3_ADC_OFFSET_MSB 7 +#define THERM_CTRL3_ADC_OFFSET_LSB 0 +#define THERM_CTRL3_ADC_OFFSET_MASK 0x000000ff +#define THERM_CTRL3_ADC_OFFSET_GET(x) (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB) +#define THERM_CTRL3_ADC_OFFSET_SET(x) (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rtc_wlan_reg_reg_s { + volatile unsigned int wlan_reset_control; + volatile unsigned int wlan_xtal_control; + volatile unsigned int wlan_tcxo_detect; + volatile unsigned int wlan_xtal_test; + volatile unsigned int wlan_quadrature; + volatile unsigned int wlan_pll_control; + volatile unsigned int wlan_pll_settle; + volatile unsigned int wlan_xtal_settle; + volatile unsigned int wlan_cpu_clock; + volatile unsigned int wlan_clock_out; + volatile unsigned int wlan_clock_control; + volatile unsigned int wlan_bias_override; + volatile unsigned int wlan_wdt_control; + volatile unsigned int wlan_wdt_status; + volatile unsigned int wlan_wdt; + volatile unsigned int wlan_wdt_count; + volatile unsigned int wlan_wdt_reset; + volatile unsigned int wlan_int_status; + volatile unsigned int wlan_lf_timer0; + volatile unsigned int wlan_lf_timer_count0; + volatile unsigned int wlan_lf_timer_control0; + volatile unsigned int wlan_lf_timer_status0; + volatile unsigned int wlan_lf_timer1; + volatile unsigned int wlan_lf_timer_count1; + volatile unsigned int wlan_lf_timer_control1; + volatile unsigned int wlan_lf_timer_status1; + volatile unsigned int wlan_lf_timer2; + volatile unsigned int wlan_lf_timer_count2; + volatile unsigned int wlan_lf_timer_control2; + volatile unsigned int wlan_lf_timer_status2; + volatile unsigned int wlan_lf_timer3; + volatile unsigned int wlan_lf_timer_count3; + volatile unsigned int wlan_lf_timer_control3; + volatile unsigned int wlan_lf_timer_status3; + volatile unsigned int wlan_hf_timer; + volatile unsigned int wlan_hf_timer_count; + volatile unsigned int wlan_hf_lf_count; + volatile unsigned int wlan_hf_timer_control; + volatile unsigned int wlan_hf_timer_status; + volatile unsigned int wlan_rtc_control; + volatile unsigned int wlan_rtc_time; + volatile unsigned int wlan_rtc_date; + volatile unsigned int wlan_rtc_set_time; + volatile unsigned int wlan_rtc_set_date; + volatile unsigned int wlan_rtc_set_alarm; + volatile unsigned int wlan_rtc_config; + volatile unsigned int wlan_rtc_alarm_status; + volatile unsigned int wlan_uart_wakeup; + volatile unsigned int wlan_reset_cause; + volatile unsigned int wlan_system_sleep; + volatile unsigned int wlan_sdio_wrapper; + volatile unsigned int wlan_mac_sleep_control; + volatile unsigned int wlan_keep_awake; + volatile unsigned int wlan_lpo_cal_time; + volatile unsigned int wlan_lpo_init_dividend_int; + volatile unsigned int wlan_lpo_init_dividend_fraction; + volatile unsigned int wlan_lpo_cal; + volatile unsigned int wlan_lpo_cal_test_control; + volatile unsigned int wlan_lpo_cal_test_status; + volatile unsigned int wlan_chip_id; + volatile unsigned int wlan_derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int wlan_power_reg; + volatile unsigned int wlan_core_clk_ctrl; + volatile unsigned int wlan_gpio_wakeup_control; + volatile unsigned int ht; + volatile unsigned int mac_pcu_tsf_l32; + volatile unsigned int mac_pcu_tsf_u32; + volatile unsigned int mac_pcu_wbtimer; + unsigned char pad0[24]; /* pad to 0x140 */ + volatile unsigned int mac_pcu_generic_timers[16]; + volatile unsigned int mac_pcu_generic_timers_mode; + unsigned char pad1[60]; /* pad to 0x1c0 */ + volatile unsigned int mac_pcu_generic_timers2[16]; + volatile unsigned int mac_pcu_generic_timers_mode2; + volatile unsigned int mac_pcu_slp1; + volatile unsigned int mac_pcu_slp2; + volatile unsigned int mac_pcu_reset_tsf; + volatile unsigned int mac_pcu_tsf_add_pll; + volatile unsigned int sleep_retention; + volatile unsigned int btcoexctrl; + volatile unsigned int wbsync_priority1; + volatile unsigned int wbsync_priority2; + volatile unsigned int wbsync_priority3; + volatile unsigned int btcoex0; + volatile unsigned int btcoex1; + volatile unsigned int btcoex2; + volatile unsigned int btcoex3; + volatile unsigned int btcoex4; + volatile unsigned int btcoex5; + volatile unsigned int btcoex6; + volatile unsigned int lock; + volatile unsigned int nolock_priority; + volatile unsigned int wbsync; + volatile unsigned int wbsync1; + volatile unsigned int wbsync2; + volatile unsigned int wbsync3; + volatile unsigned int wb_timer_target; + volatile unsigned int wb_timer_slop; + volatile unsigned int btcoex_int_en; + volatile unsigned int btcoex_int_stat; + volatile unsigned int btpriority_int_en; + volatile unsigned int btpriority_int_stat; + volatile unsigned int btpriority_stomp_int_en; + volatile unsigned int btpriority_stomp_int_stat; + volatile unsigned int mac_pcu_bmiss_timeout; + volatile unsigned int mac_pcu_cab_awake; + volatile unsigned int lp_perf_counter; + volatile unsigned int lp_perf_light_sleep; + volatile unsigned int lp_perf_deep_sleep; + volatile unsigned int lp_perf_on; + volatile unsigned int st_64_bit; + volatile unsigned int message_wr; + volatile unsigned int message_wr_p; + volatile unsigned int message_rd; + volatile unsigned int message_rd_p; + volatile unsigned int chip_mode; + volatile unsigned int clk_req_fall_edge; + volatile unsigned int otp; + volatile unsigned int otp_status; + volatile unsigned int pmu; + unsigned char pad2[4]; /* pad to 0x2c0 */ + volatile unsigned int pmu_config[2]; + volatile unsigned int pmu_bypass; + volatile unsigned int mac_pcu_tsf2_l32; + volatile unsigned int mac_pcu_tsf2_u32; + volatile unsigned int mac_pcu_generic_timers_mode3; + volatile unsigned int mac_pcu_direct_connect; + volatile unsigned int therm_ctrl1; + volatile unsigned int therm_ctrl2; + volatile unsigned int therm_ctrl3; +} rtc_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h new file mode 100644 index 000000000000..2cd2e3cadbbc --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h @@ -0,0 +1,209 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s { + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h new file mode 100644 index 000000000000..a8eccaf6d745 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h @@ -0,0 +1,260 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define UART_DATA_ADDRESS 0x00000000 +#define UART_DATA_OFFSET 0x00000000 +#define UART_DATA_TX_CSR_MSB 9 +#define UART_DATA_TX_CSR_LSB 9 +#define UART_DATA_TX_CSR_MASK 0x00000200 +#define UART_DATA_TX_CSR_GET(x) (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB) +#define UART_DATA_TX_CSR_SET(x) (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK) +#define UART_DATA_RX_CSR_MSB 8 +#define UART_DATA_RX_CSR_LSB 8 +#define UART_DATA_RX_CSR_MASK 0x00000100 +#define UART_DATA_RX_CSR_GET(x) (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB) +#define UART_DATA_RX_CSR_SET(x) (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK) +#define UART_DATA_TXRX_DATA_MSB 7 +#define UART_DATA_TXRX_DATA_LSB 0 +#define UART_DATA_TXRX_DATA_MASK 0x000000ff +#define UART_DATA_TXRX_DATA_GET(x) (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB) +#define UART_DATA_TXRX_DATA_SET(x) (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK) + +#define UART_CONTROL_ADDRESS 0x00000004 +#define UART_CONTROL_OFFSET 0x00000004 +#define UART_CONTROL_RX_BUSY_MSB 15 +#define UART_CONTROL_RX_BUSY_LSB 15 +#define UART_CONTROL_RX_BUSY_MASK 0x00008000 +#define UART_CONTROL_RX_BUSY_GET(x) (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB) +#define UART_CONTROL_RX_BUSY_SET(x) (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK) +#define UART_CONTROL_TX_BUSY_MSB 14 +#define UART_CONTROL_TX_BUSY_LSB 14 +#define UART_CONTROL_TX_BUSY_MASK 0x00004000 +#define UART_CONTROL_TX_BUSY_GET(x) (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB) +#define UART_CONTROL_TX_BUSY_SET(x) (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK) +#define UART_CONTROL_HOST_INT_ENABLE_MSB 13 +#define UART_CONTROL_HOST_INT_ENABLE_LSB 13 +#define UART_CONTROL_HOST_INT_ENABLE_MASK 0x00002000 +#define UART_CONTROL_HOST_INT_ENABLE_GET(x) (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB) +#define UART_CONTROL_HOST_INT_ENABLE_SET(x) (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK) +#define UART_CONTROL_HOST_INT_MSB 12 +#define UART_CONTROL_HOST_INT_LSB 12 +#define UART_CONTROL_HOST_INT_MASK 0x00001000 +#define UART_CONTROL_HOST_INT_GET(x) (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB) +#define UART_CONTROL_HOST_INT_SET(x) (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK) +#define UART_CONTROL_TX_BREAK_MSB 11 +#define UART_CONTROL_TX_BREAK_LSB 11 +#define UART_CONTROL_TX_BREAK_MASK 0x00000800 +#define UART_CONTROL_TX_BREAK_GET(x) (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB) +#define UART_CONTROL_TX_BREAK_SET(x) (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK) +#define UART_CONTROL_RX_BREAK_MSB 10 +#define UART_CONTROL_RX_BREAK_LSB 10 +#define UART_CONTROL_RX_BREAK_MASK 0x00000400 +#define UART_CONTROL_RX_BREAK_GET(x) (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB) +#define UART_CONTROL_RX_BREAK_SET(x) (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK) +#define UART_CONTROL_SERIAL_TX_READY_MSB 9 +#define UART_CONTROL_SERIAL_TX_READY_LSB 9 +#define UART_CONTROL_SERIAL_TX_READY_MASK 0x00000200 +#define UART_CONTROL_SERIAL_TX_READY_GET(x) (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB) +#define UART_CONTROL_SERIAL_TX_READY_SET(x) (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK) +#define UART_CONTROL_TX_READY_ORIDE_MSB 8 +#define UART_CONTROL_TX_READY_ORIDE_LSB 8 +#define UART_CONTROL_TX_READY_ORIDE_MASK 0x00000100 +#define UART_CONTROL_TX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB) +#define UART_CONTROL_TX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK) +#define UART_CONTROL_RX_READY_ORIDE_MSB 7 +#define UART_CONTROL_RX_READY_ORIDE_LSB 7 +#define UART_CONTROL_RX_READY_ORIDE_MASK 0x00000080 +#define UART_CONTROL_RX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB) +#define UART_CONTROL_RX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK) +#define UART_CONTROL_DMA_ENABLE_MSB 6 +#define UART_CONTROL_DMA_ENABLE_LSB 6 +#define UART_CONTROL_DMA_ENABLE_MASK 0x00000040 +#define UART_CONTROL_DMA_ENABLE_GET(x) (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB) +#define UART_CONTROL_DMA_ENABLE_SET(x) (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK) +#define UART_CONTROL_FLOW_ENABLE_MSB 5 +#define UART_CONTROL_FLOW_ENABLE_LSB 5 +#define UART_CONTROL_FLOW_ENABLE_MASK 0x00000020 +#define UART_CONTROL_FLOW_ENABLE_GET(x) (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB) +#define UART_CONTROL_FLOW_ENABLE_SET(x) (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK) +#define UART_CONTROL_FLOW_INVERT_MSB 4 +#define UART_CONTROL_FLOW_INVERT_LSB 4 +#define UART_CONTROL_FLOW_INVERT_MASK 0x00000010 +#define UART_CONTROL_FLOW_INVERT_GET(x) (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB) +#define UART_CONTROL_FLOW_INVERT_SET(x) (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK) +#define UART_CONTROL_IFC_ENABLE_MSB 3 +#define UART_CONTROL_IFC_ENABLE_LSB 3 +#define UART_CONTROL_IFC_ENABLE_MASK 0x00000008 +#define UART_CONTROL_IFC_ENABLE_GET(x) (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB) +#define UART_CONTROL_IFC_ENABLE_SET(x) (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK) +#define UART_CONTROL_IFC_DCE_MSB 2 +#define UART_CONTROL_IFC_DCE_LSB 2 +#define UART_CONTROL_IFC_DCE_MASK 0x00000004 +#define UART_CONTROL_IFC_DCE_GET(x) (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB) +#define UART_CONTROL_IFC_DCE_SET(x) (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK) +#define UART_CONTROL_PARITY_ENABLE_MSB 1 +#define UART_CONTROL_PARITY_ENABLE_LSB 1 +#define UART_CONTROL_PARITY_ENABLE_MASK 0x00000002 +#define UART_CONTROL_PARITY_ENABLE_GET(x) (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB) +#define UART_CONTROL_PARITY_ENABLE_SET(x) (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK) +#define UART_CONTROL_PARITY_EVEN_MSB 0 +#define UART_CONTROL_PARITY_EVEN_LSB 0 +#define UART_CONTROL_PARITY_EVEN_MASK 0x00000001 +#define UART_CONTROL_PARITY_EVEN_GET(x) (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB) +#define UART_CONTROL_PARITY_EVEN_SET(x) (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK) + +#define UART_CLKDIV_ADDRESS 0x00000008 +#define UART_CLKDIV_OFFSET 0x00000008 +#define UART_CLKDIV_CLK_SCALE_MSB 23 +#define UART_CLKDIV_CLK_SCALE_LSB 16 +#define UART_CLKDIV_CLK_SCALE_MASK 0x00ff0000 +#define UART_CLKDIV_CLK_SCALE_GET(x) (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB) +#define UART_CLKDIV_CLK_SCALE_SET(x) (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK) +#define UART_CLKDIV_CLK_STEP_MSB 15 +#define UART_CLKDIV_CLK_STEP_LSB 0 +#define UART_CLKDIV_CLK_STEP_MASK 0x0000ffff +#define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB) +#define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK) + +#define UART_INT_ADDRESS 0x0000000c +#define UART_INT_OFFSET 0x0000000c +#define UART_INT_TX_EMPTY_INT_MSB 9 +#define UART_INT_TX_EMPTY_INT_LSB 9 +#define UART_INT_TX_EMPTY_INT_MASK 0x00000200 +#define UART_INT_TX_EMPTY_INT_GET(x) (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB) +#define UART_INT_TX_EMPTY_INT_SET(x) (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK) +#define UART_INT_RX_FULL_INT_MSB 8 +#define UART_INT_RX_FULL_INT_LSB 8 +#define UART_INT_RX_FULL_INT_MASK 0x00000100 +#define UART_INT_RX_FULL_INT_GET(x) (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB) +#define UART_INT_RX_FULL_INT_SET(x) (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK) +#define UART_INT_RX_BREAK_OFF_INT_MSB 7 +#define UART_INT_RX_BREAK_OFF_INT_LSB 7 +#define UART_INT_RX_BREAK_OFF_INT_MASK 0x00000080 +#define UART_INT_RX_BREAK_OFF_INT_GET(x) (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB) +#define UART_INT_RX_BREAK_OFF_INT_SET(x) (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK) +#define UART_INT_RX_BREAK_ON_INT_MSB 6 +#define UART_INT_RX_BREAK_ON_INT_LSB 6 +#define UART_INT_RX_BREAK_ON_INT_MASK 0x00000040 +#define UART_INT_RX_BREAK_ON_INT_GET(x) (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB) +#define UART_INT_RX_BREAK_ON_INT_SET(x) (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK) +#define UART_INT_RX_PARITY_ERR_INT_MSB 5 +#define UART_INT_RX_PARITY_ERR_INT_LSB 5 +#define UART_INT_RX_PARITY_ERR_INT_MASK 0x00000020 +#define UART_INT_RX_PARITY_ERR_INT_GET(x) (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB) +#define UART_INT_RX_PARITY_ERR_INT_SET(x) (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK) +#define UART_INT_TX_OFLOW_ERR_INT_MSB 4 +#define UART_INT_TX_OFLOW_ERR_INT_LSB 4 +#define UART_INT_TX_OFLOW_ERR_INT_MASK 0x00000010 +#define UART_INT_TX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB) +#define UART_INT_TX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK) +#define UART_INT_RX_OFLOW_ERR_INT_MSB 3 +#define UART_INT_RX_OFLOW_ERR_INT_LSB 3 +#define UART_INT_RX_OFLOW_ERR_INT_MASK 0x00000008 +#define UART_INT_RX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB) +#define UART_INT_RX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK) +#define UART_INT_RX_FRAMING_ERR_INT_MSB 2 +#define UART_INT_RX_FRAMING_ERR_INT_LSB 2 +#define UART_INT_RX_FRAMING_ERR_INT_MASK 0x00000004 +#define UART_INT_RX_FRAMING_ERR_INT_GET(x) (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB) +#define UART_INT_RX_FRAMING_ERR_INT_SET(x) (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK) +#define UART_INT_TX_READY_INT_MSB 1 +#define UART_INT_TX_READY_INT_LSB 1 +#define UART_INT_TX_READY_INT_MASK 0x00000002 +#define UART_INT_TX_READY_INT_GET(x) (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB) +#define UART_INT_TX_READY_INT_SET(x) (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK) +#define UART_INT_RX_VALID_INT_MSB 0 +#define UART_INT_RX_VALID_INT_LSB 0 +#define UART_INT_RX_VALID_INT_MASK 0x00000001 +#define UART_INT_RX_VALID_INT_GET(x) (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB) +#define UART_INT_RX_VALID_INT_SET(x) (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK) + +#define UART_INT_EN_ADDRESS 0x00000010 +#define UART_INT_EN_OFFSET 0x00000010 +#define UART_INT_EN_TX_EMPTY_INT_EN_MSB 9 +#define UART_INT_EN_TX_EMPTY_INT_EN_LSB 9 +#define UART_INT_EN_TX_EMPTY_INT_EN_MASK 0x00000200 +#define UART_INT_EN_TX_EMPTY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB) +#define UART_INT_EN_TX_EMPTY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) +#define UART_INT_EN_RX_FULL_INT_EN_MSB 8 +#define UART_INT_EN_RX_FULL_INT_EN_LSB 8 +#define UART_INT_EN_RX_FULL_INT_EN_MASK 0x00000100 +#define UART_INT_EN_RX_FULL_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB) +#define UART_INT_EN_RX_FULL_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK) +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB 7 +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB 7 +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK 0x00000080 +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) +#define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB 6 +#define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB 6 +#define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK 0x00000040 +#define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) +#define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB 5 +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB 5 +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK 0x00000020 +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB 4 +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB 4 +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK 0x00000010 +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB 3 +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB 3 +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK 0x00000008 +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB 2 +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB 2 +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK 0x00000004 +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) +#define UART_INT_EN_TX_READY_INT_EN_MSB 1 +#define UART_INT_EN_TX_READY_INT_EN_LSB 1 +#define UART_INT_EN_TX_READY_INT_EN_MASK 0x00000002 +#define UART_INT_EN_TX_READY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB) +#define UART_INT_EN_TX_READY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK) +#define UART_INT_EN_RX_VALID_INT_EN_MSB 0 +#define UART_INT_EN_RX_VALID_INT_EN_LSB 0 +#define UART_INT_EN_RX_VALID_INT_EN_MASK 0x00000001 +#define UART_INT_EN_RX_VALID_INT_EN_GET(x) (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB) +#define UART_INT_EN_RX_VALID_INT_EN_SET(x) (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s { + volatile unsigned int uart_data; + volatile unsigned int uart_control; + volatile unsigned int uart_clkdiv; + volatile unsigned int uart_int; + volatile unsigned int uart_int_en; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h new file mode 100644 index 000000000000..b233cbc513bc --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h @@ -0,0 +1,37 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "umbox_wlan_reg.h" + + +#ifndef BT_HEADERS + + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h new file mode 100644 index 000000000000..4737a2805b2f --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h @@ -0,0 +1,322 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UMBOX_WLAN_REG_REG_H_ +#define _UMBOX_WLAN_REG_REG_H_ + +#define UMBOX_FIFO_ADDRESS 0x00000000 +#define UMBOX_FIFO_OFFSET 0x00000000 +#define UMBOX_FIFO_DATA_MSB 8 +#define UMBOX_FIFO_DATA_LSB 0 +#define UMBOX_FIFO_DATA_MASK 0x000001ff +#define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB) +#define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK) + +#define UMBOX_FIFO_STATUS_ADDRESS 0x00000008 +#define UMBOX_FIFO_STATUS_OFFSET 0x00000008 +#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3 +#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3 +#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008 +#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB) +#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) +#define UMBOX_FIFO_STATUS_TX_FULL_MSB 2 +#define UMBOX_FIFO_STATUS_TX_FULL_LSB 2 +#define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004 +#define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB) +#define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK) +#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1 +#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1 +#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002 +#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB) +#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) +#define UMBOX_FIFO_STATUS_RX_FULL_MSB 0 +#define UMBOX_FIFO_STATUS_RX_FULL_LSB 0 +#define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001 +#define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB) +#define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK) + +#define UMBOX_DMA_POLICY_ADDRESS 0x0000000c +#define UMBOX_DMA_POLICY_OFFSET 0x0000000c +#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define UMBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define UMBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB) +#define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK) +#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define UMBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define UMBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB) +#define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK) + +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014 +#define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014 +#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define UMBOX0_DMA_RX_CONTROL_START_MSB 1 +#define UMBOX0_DMA_RX_CONTROL_START_LSB 1 +#define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB) +#define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK) +#define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB) +#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c +#define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c +#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define UMBOX0_DMA_TX_CONTROL_START_MSB 1 +#define UMBOX0_DMA_TX_CONTROL_START_LSB 1 +#define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB) +#define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK) +#define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB) +#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020 +#define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) +#define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7 +#define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0 +#define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB) +#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) + +#define UMBOX_INT_STATUS_ADDRESS 0x00000024 +#define UMBOX_INT_STATUS_OFFSET 0x00000024 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8 +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8 +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100 +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7 +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7 +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080 +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6 +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6 +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040 +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5 +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5 +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020 +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4 +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4 +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010 +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) +#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3 +#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3 +#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008 +#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2 +#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2 +#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004 +#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1 +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1 +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002 +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0 +#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0 +#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001 +#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) + +#define UMBOX_INT_ENABLE_ADDRESS 0x00000028 +#define UMBOX_INT_ENABLE_OFFSET 0x00000028 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8 +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8 +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100 +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7 +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7 +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080 +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6 +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6 +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040 +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5 +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5 +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020 +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4 +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4 +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010 +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) +#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3 +#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3 +#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008 +#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2 +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2 +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004 +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1 +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1 +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002 +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0 +#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0 +#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001 +#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) + +#define UMBOX_DEBUG_ADDRESS 0x0000002c +#define UMBOX_DEBUG_OFFSET 0x0000002c +#define UMBOX_DEBUG_SEL_MSB 2 +#define UMBOX_DEBUG_SEL_LSB 0 +#define UMBOX_DEBUG_SEL_MASK 0x00000007 +#define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB) +#define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK) + +#define UMBOX_FIFO_RESET_ADDRESS 0x00000030 +#define UMBOX_FIFO_RESET_OFFSET 0x00000030 +#define UMBOX_FIFO_RESET_INIT_MSB 0 +#define UMBOX_FIFO_RESET_INIT_LSB 0 +#define UMBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB) +#define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK) + +#define UMBOX_HCI_FRAMER_ADDRESS 0x00000034 +#define UMBOX_HCI_FRAMER_OFFSET 0x00000034 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) +#define UMBOX_HCI_FRAMER_ENABLE_MSB 5 +#define UMBOX_HCI_FRAMER_ENABLE_LSB 5 +#define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020 +#define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB) +#define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK) +#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4 +#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4 +#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010 +#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) +#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) +#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3 +#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3 +#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008 +#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB) +#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) +#define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2 +#define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2 +#define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004 +#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB) +#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) +#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1 +#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0 +#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003 +#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) +#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct umbox_wlan_reg_reg_s { + volatile unsigned int umbox_fifo[2]; + volatile unsigned int umbox_fifo_status; + volatile unsigned int umbox_dma_policy; + volatile unsigned int umbox0_dma_rx_descriptor_base; + volatile unsigned int umbox0_dma_rx_control; + volatile unsigned int umbox0_dma_tx_descriptor_base; + volatile unsigned int umbox0_dma_tx_control; + volatile unsigned int umbox_fifo_timeout; + volatile unsigned int umbox_int_status; + volatile unsigned int umbox_int_enable; + volatile unsigned int umbox_debug; + volatile unsigned int umbox_fifo_reset; + volatile unsigned int umbox_hci_framer; +} umbox_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UMBOX_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h new file mode 100644 index 000000000000..c3d8088a5554 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h @@ -0,0 +1,167 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "vmc_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define MC_BCAM_VALID_ADDRESS WLAN_MC_BCAM_VALID_ADDRESS +#define MC_BCAM_VALID_OFFSET WLAN_MC_BCAM_VALID_OFFSET +#define MC_BCAM_VALID_BIT_MSB WLAN_MC_BCAM_VALID_BIT_MSB +#define MC_BCAM_VALID_BIT_LSB WLAN_MC_BCAM_VALID_BIT_LSB +#define MC_BCAM_VALID_BIT_MASK WLAN_MC_BCAM_VALID_BIT_MASK +#define MC_BCAM_VALID_BIT_GET(x) WLAN_MC_BCAM_VALID_BIT_GET(x) +#define MC_BCAM_VALID_BIT_SET(x) WLAN_MC_BCAM_VALID_BIT_SET(x) +#define MC_BCAM_COMPARE_ADDRESS WLAN_MC_BCAM_COMPARE_ADDRESS +#define MC_BCAM_COMPARE_OFFSET WLAN_MC_BCAM_COMPARE_OFFSET +#define MC_BCAM_COMPARE_KEY_MSB WLAN_MC_BCAM_COMPARE_KEY_MSB +#define MC_BCAM_COMPARE_KEY_LSB WLAN_MC_BCAM_COMPARE_KEY_LSB +#define MC_BCAM_COMPARE_KEY_MASK WLAN_MC_BCAM_COMPARE_KEY_MASK +#define MC_BCAM_COMPARE_KEY_GET(x) WLAN_MC_BCAM_COMPARE_KEY_GET(x) +#define MC_BCAM_COMPARE_KEY_SET(x) WLAN_MC_BCAM_COMPARE_KEY_SET(x) +#define MC_BCAM_TARGET_ADDRESS WLAN_MC_BCAM_TARGET_ADDRESS +#define MC_BCAM_TARGET_OFFSET WLAN_MC_BCAM_TARGET_OFFSET +#define MC_BCAM_TARGET_INST_MSB WLAN_MC_BCAM_TARGET_INST_MSB +#define MC_BCAM_TARGET_INST_LSB WLAN_MC_BCAM_TARGET_INST_LSB +#define MC_BCAM_TARGET_INST_MASK WLAN_MC_BCAM_TARGET_INST_MASK +#define MC_BCAM_TARGET_INST_GET(x) WLAN_MC_BCAM_TARGET_INST_GET(x) +#define MC_BCAM_TARGET_INST_SET(x) WLAN_MC_BCAM_TARGET_INST_SET(x) +#define APB_ADDR_ERROR_CONTROL_ADDRESS WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS +#define APB_ADDR_ERROR_CONTROL_OFFSET WLAN_APB_ADDR_ERROR_CONTROL_OFFSET +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) +#define APB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB +#define APB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB +#define APB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK +#define APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) +#define APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) +#define APB_ADDR_ERROR_STATUS_ADDRESS WLAN_APB_ADDR_ERROR_STATUS_ADDRESS +#define APB_ADDR_ERROR_STATUS_OFFSET WLAN_APB_ADDR_ERROR_STATUS_OFFSET +#define APB_ADDR_ERROR_STATUS_WRITE_MSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB +#define APB_ADDR_ERROR_STATUS_WRITE_LSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB +#define APB_ADDR_ERROR_STATUS_WRITE_MASK WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK +#define APB_ADDR_ERROR_STATUS_WRITE_GET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) +#define APB_ADDR_ERROR_STATUS_WRITE_SET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) +#define APB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB +#define APB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB +#define APB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK +#define APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) +#define APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) +#define AHB_ADDR_ERROR_CONTROL_ADDRESS WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS +#define AHB_ADDR_ERROR_CONTROL_OFFSET WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET +#define AHB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB +#define AHB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB +#define AHB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK +#define AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) +#define AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) +#define AHB_ADDR_ERROR_STATUS_ADDRESS WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS +#define AHB_ADDR_ERROR_STATUS_OFFSET WLAN_AHB_ADDR_ERROR_STATUS_OFFSET +#define AHB_ADDR_ERROR_STATUS_MAC_MSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB +#define AHB_ADDR_ERROR_STATUS_MAC_LSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB +#define AHB_ADDR_ERROR_STATUS_MAC_MASK WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK +#define AHB_ADDR_ERROR_STATUS_MAC_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) +#define AHB_ADDR_ERROR_STATUS_MAC_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) +#define AHB_ADDR_ERROR_STATUS_MBOX_MSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB +#define AHB_ADDR_ERROR_STATUS_MBOX_LSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB +#define AHB_ADDR_ERROR_STATUS_MBOX_MASK WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK +#define AHB_ADDR_ERROR_STATUS_MBOX_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) +#define AHB_ADDR_ERROR_STATUS_MBOX_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) +#define AHB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB +#define AHB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB +#define AHB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK +#define AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) +#define AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) +#define BCAM_CONFLICT_ERROR_ADDRESS WLAN_BCAM_CONFLICT_ERROR_ADDRESS +#define BCAM_CONFLICT_ERROR_OFFSET WLAN_BCAM_CONFLICT_ERROR_OFFSET +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) +#define CPU_PERF_CNT_ADDRESS WLAN_CPU_PERF_CNT_ADDRESS +#define CPU_PERF_CNT_OFFSET WLAN_CPU_PERF_CNT_OFFSET +#define CPU_PERF_CNT_EN_MSB WLAN_CPU_PERF_CNT_EN_MSB +#define CPU_PERF_CNT_EN_LSB WLAN_CPU_PERF_CNT_EN_LSB +#define CPU_PERF_CNT_EN_MASK WLAN_CPU_PERF_CNT_EN_MASK +#define CPU_PERF_CNT_EN_GET(x) WLAN_CPU_PERF_CNT_EN_GET(x) +#define CPU_PERF_CNT_EN_SET(x) WLAN_CPU_PERF_CNT_EN_SET(x) +#define CPU_INST_FETCH_ADDRESS WLAN_CPU_INST_FETCH_ADDRESS +#define CPU_INST_FETCH_OFFSET WLAN_CPU_INST_FETCH_OFFSET +#define CPU_INST_FETCH_CNT_MSB WLAN_CPU_INST_FETCH_CNT_MSB +#define CPU_INST_FETCH_CNT_LSB WLAN_CPU_INST_FETCH_CNT_LSB +#define CPU_INST_FETCH_CNT_MASK WLAN_CPU_INST_FETCH_CNT_MASK +#define CPU_INST_FETCH_CNT_GET(x) WLAN_CPU_INST_FETCH_CNT_GET(x) +#define CPU_INST_FETCH_CNT_SET(x) WLAN_CPU_INST_FETCH_CNT_SET(x) +#define CPU_DATA_FETCH_ADDRESS WLAN_CPU_DATA_FETCH_ADDRESS +#define CPU_DATA_FETCH_OFFSET WLAN_CPU_DATA_FETCH_OFFSET +#define CPU_DATA_FETCH_CNT_MSB WLAN_CPU_DATA_FETCH_CNT_MSB +#define CPU_DATA_FETCH_CNT_LSB WLAN_CPU_DATA_FETCH_CNT_LSB +#define CPU_DATA_FETCH_CNT_MASK WLAN_CPU_DATA_FETCH_CNT_MASK +#define CPU_DATA_FETCH_CNT_GET(x) WLAN_CPU_DATA_FETCH_CNT_GET(x) +#define CPU_DATA_FETCH_CNT_SET(x) WLAN_CPU_DATA_FETCH_CNT_SET(x) +#define CPU_RAM1_CONFLICT_ADDRESS WLAN_CPU_RAM1_CONFLICT_ADDRESS +#define CPU_RAM1_CONFLICT_OFFSET WLAN_CPU_RAM1_CONFLICT_OFFSET +#define CPU_RAM1_CONFLICT_CNT_MSB WLAN_CPU_RAM1_CONFLICT_CNT_MSB +#define CPU_RAM1_CONFLICT_CNT_LSB WLAN_CPU_RAM1_CONFLICT_CNT_LSB +#define CPU_RAM1_CONFLICT_CNT_MASK WLAN_CPU_RAM1_CONFLICT_CNT_MASK +#define CPU_RAM1_CONFLICT_CNT_GET(x) WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) +#define CPU_RAM1_CONFLICT_CNT_SET(x) WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) +#define CPU_RAM2_CONFLICT_ADDRESS WLAN_CPU_RAM2_CONFLICT_ADDRESS +#define CPU_RAM2_CONFLICT_OFFSET WLAN_CPU_RAM2_CONFLICT_OFFSET +#define CPU_RAM2_CONFLICT_CNT_MSB WLAN_CPU_RAM2_CONFLICT_CNT_MSB +#define CPU_RAM2_CONFLICT_CNT_LSB WLAN_CPU_RAM2_CONFLICT_CNT_LSB +#define CPU_RAM2_CONFLICT_CNT_MASK WLAN_CPU_RAM2_CONFLICT_CNT_MASK +#define CPU_RAM2_CONFLICT_CNT_GET(x) WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) +#define CPU_RAM2_CONFLICT_CNT_SET(x) WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) +#define CPU_RAM3_CONFLICT_ADDRESS WLAN_CPU_RAM3_CONFLICT_ADDRESS +#define CPU_RAM3_CONFLICT_OFFSET WLAN_CPU_RAM3_CONFLICT_OFFSET +#define CPU_RAM3_CONFLICT_CNT_MSB WLAN_CPU_RAM3_CONFLICT_CNT_MSB +#define CPU_RAM3_CONFLICT_CNT_LSB WLAN_CPU_RAM3_CONFLICT_CNT_LSB +#define CPU_RAM3_CONFLICT_CNT_MASK WLAN_CPU_RAM3_CONFLICT_CNT_MASK +#define CPU_RAM3_CONFLICT_CNT_GET(x) WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) +#define CPU_RAM3_CONFLICT_CNT_SET(x) WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) +#define CPU_RAM4_CONFLICT_ADDRESS WLAN_CPU_RAM4_CONFLICT_ADDRESS +#define CPU_RAM4_CONFLICT_OFFSET WLAN_CPU_RAM4_CONFLICT_OFFSET +#define CPU_RAM4_CONFLICT_CNT_MSB WLAN_CPU_RAM4_CONFLICT_CNT_MSB +#define CPU_RAM4_CONFLICT_CNT_LSB WLAN_CPU_RAM4_CONFLICT_CNT_LSB +#define CPU_RAM4_CONFLICT_CNT_MASK WLAN_CPU_RAM4_CONFLICT_CNT_MASK +#define CPU_RAM4_CONFLICT_CNT_GET(x) WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) +#define CPU_RAM4_CONFLICT_CNT_SET(x) WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) + + +#endif +#endif + + + diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h new file mode 100644 index 000000000000..d28de3938b2e --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h @@ -0,0 +1,195 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _VMC_WLAN_REG_REG_H_ +#define _VMC_WLAN_REG_REG_H_ + +#define WLAN_MC_BCAM_VALID_ADDRESS 0x00000000 +#define WLAN_MC_BCAM_VALID_OFFSET 0x00000000 +#define WLAN_MC_BCAM_VALID_BIT_MSB 0 +#define WLAN_MC_BCAM_VALID_BIT_LSB 0 +#define WLAN_MC_BCAM_VALID_BIT_MASK 0x00000001 +#define WLAN_MC_BCAM_VALID_BIT_GET(x) (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB) +#define WLAN_MC_BCAM_VALID_BIT_SET(x) (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK) + +#define WLAN_MC_BCAM_COMPARE_ADDRESS 0x00000200 +#define WLAN_MC_BCAM_COMPARE_OFFSET 0x00000200 +#define WLAN_MC_BCAM_COMPARE_KEY_MSB 19 +#define WLAN_MC_BCAM_COMPARE_KEY_LSB 2 +#define WLAN_MC_BCAM_COMPARE_KEY_MASK 0x000ffffc +#define WLAN_MC_BCAM_COMPARE_KEY_GET(x) (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB) +#define WLAN_MC_BCAM_COMPARE_KEY_SET(x) (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK) + +#define WLAN_MC_BCAM_TARGET_ADDRESS 0x00000400 +#define WLAN_MC_BCAM_TARGET_OFFSET 0x00000400 +#define WLAN_MC_BCAM_TARGET_INST_MSB 31 +#define WLAN_MC_BCAM_TARGET_INST_LSB 0 +#define WLAN_MC_BCAM_TARGET_INST_MASK 0xffffffff +#define WLAN_MC_BCAM_TARGET_INST_GET(x) (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB) +#define WLAN_MC_BCAM_TARGET_INST_SET(x) (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK) + +#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS 0x00000600 +#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET 0x00000600 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS 0x00000604 +#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET 0x00000604 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB 25 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB 25 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) + +#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS 0x00000608 +#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET 0x00000608 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS 0x0000060c +#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET 0x0000060c +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB 31 +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB 31 +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK 0x80000000 +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB 30 +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB 30 +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK 0x40000000 +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB 23 +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x00ffffff +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) + +#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS 0x00000610 +#define WLAN_BCAM_CONFLICT_ERROR_OFFSET 0x00000610 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB 1 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB 1 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB 0 +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB 0 +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001 +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) + +#define WLAN_CPU_PERF_CNT_ADDRESS 0x00000614 +#define WLAN_CPU_PERF_CNT_OFFSET 0x00000614 +#define WLAN_CPU_PERF_CNT_EN_MSB 0 +#define WLAN_CPU_PERF_CNT_EN_LSB 0 +#define WLAN_CPU_PERF_CNT_EN_MASK 0x00000001 +#define WLAN_CPU_PERF_CNT_EN_GET(x) (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB) +#define WLAN_CPU_PERF_CNT_EN_SET(x) (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK) + +#define WLAN_CPU_INST_FETCH_ADDRESS 0x00000618 +#define WLAN_CPU_INST_FETCH_OFFSET 0x00000618 +#define WLAN_CPU_INST_FETCH_CNT_MSB 31 +#define WLAN_CPU_INST_FETCH_CNT_LSB 0 +#define WLAN_CPU_INST_FETCH_CNT_MASK 0xffffffff +#define WLAN_CPU_INST_FETCH_CNT_GET(x) (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB) +#define WLAN_CPU_INST_FETCH_CNT_SET(x) (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK) + +#define WLAN_CPU_DATA_FETCH_ADDRESS 0x0000061c +#define WLAN_CPU_DATA_FETCH_OFFSET 0x0000061c +#define WLAN_CPU_DATA_FETCH_CNT_MSB 31 +#define WLAN_CPU_DATA_FETCH_CNT_LSB 0 +#define WLAN_CPU_DATA_FETCH_CNT_MASK 0xffffffff +#define WLAN_CPU_DATA_FETCH_CNT_GET(x) (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB) +#define WLAN_CPU_DATA_FETCH_CNT_SET(x) (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK) + +#define WLAN_CPU_RAM1_CONFLICT_ADDRESS 0x00000620 +#define WLAN_CPU_RAM1_CONFLICT_OFFSET 0x00000620 +#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) + +#define WLAN_CPU_RAM2_CONFLICT_ADDRESS 0x00000624 +#define WLAN_CPU_RAM2_CONFLICT_OFFSET 0x00000624 +#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) + +#define WLAN_CPU_RAM3_CONFLICT_ADDRESS 0x00000628 +#define WLAN_CPU_RAM3_CONFLICT_OFFSET 0x00000628 +#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) + +#define WLAN_CPU_RAM4_CONFLICT_ADDRESS 0x0000062c +#define WLAN_CPU_RAM4_CONFLICT_OFFSET 0x0000062c +#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct vmc_wlan_reg_reg_s { + volatile unsigned int wlan_mc_bcam_valid[128]; + volatile unsigned int wlan_mc_bcam_compare[128]; + volatile unsigned int wlan_mc_bcam_target[128]; + volatile unsigned int wlan_apb_addr_error_control; + volatile unsigned int wlan_apb_addr_error_status; + volatile unsigned int wlan_ahb_addr_error_control; + volatile unsigned int wlan_ahb_addr_error_status; + volatile unsigned int wlan_bcam_conflict_error; + volatile unsigned int wlan_cpu_perf_cnt; + volatile unsigned int wlan_cpu_inst_fetch; + volatile unsigned int wlan_cpu_data_fetch; + volatile unsigned int wlan_cpu_ram1_conflict; + volatile unsigned int wlan_cpu_ram2_conflict; + volatile unsigned int wlan_cpu_ram3_conflict; + volatile unsigned int wlan_cpu_ram4_conflict; +} vmc_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/a_hci.h b/drivers/staging/ath6kl/include/common/a_hci.h new file mode 100644 index 000000000000..f2943466339f --- /dev/null +++ b/drivers/staging/ath6kl/include/common/a_hci.h @@ -0,0 +1,682 @@ +//- +// Copyright (c) 2009-2010 Atheros Communications Inc. +// All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// +// + + +#ifndef __A_HCI_H__ +#define __A_HCI_H__ + +#define HCI_CMD_OGF_MASK 0x3F +#define HCI_CMD_OGF_SHIFT 10 +#define HCI_CMD_GET_OGF(opcode) ((opcode >> HCI_CMD_OGF_SHIFT) & HCI_CMD_OGF_MASK) + +#define HCI_CMD_OCF_MASK 0x3FF +#define HCI_CMD_OCF_SHIFT 0 +#define HCI_CMD_GET_OCF(opcode) (((opcode) >> HCI_CMD_OCF_SHIFT) & HCI_CMD_OCF_MASK) + +#define HCI_FORM_OPCODE(ocf, ogf) ((ocf & HCI_CMD_OCF_MASK) << HCI_CMD_OCF_SHIFT | \ + (ogf & HCI_CMD_OGF_MASK) << HCI_CMD_OGF_SHIFT) + + +/*======== HCI Opcode groups ===============*/ +#define OGF_NOP 0x00 +#define OGF_LINK_CONTROL 0x01 +#define OGF_LINK_POLICY 0x03 +#define OGF_INFO_PARAMS 0x04 +#define OGF_STATUS 0x05 +#define OGF_TESTING 0x06 +#define OGF_BLUETOOTH 0x3E +#define OGF_VENDOR_DEBUG 0x3F + + + +#define OCF_NOP 0x00 + + +/*===== Link Control Commands Opcode===================*/ +#define OCF_HCI_Create_Physical_Link 0x35 +#define OCF_HCI_Accept_Physical_Link_Req 0x36 +#define OCF_HCI_Disconnect_Physical_Link 0x37 +#define OCF_HCI_Create_Logical_Link 0x38 +#define OCF_HCI_Accept_Logical_Link 0x39 +#define OCF_HCI_Disconnect_Logical_Link 0x3A +#define OCF_HCI_Logical_Link_Cancel 0x3B +#define OCF_HCI_Flow_Spec_Modify 0x3C + + + +/*===== Link Policy Commands Opcode====================*/ +#define OCF_HCI_Set_Event_Mask 0x01 +#define OCF_HCI_Reset 0x03 +#define OCF_HCI_Read_Conn_Accept_Timeout 0x15 +#define OCF_HCI_Write_Conn_Accept_Timeout 0x16 +#define OCF_HCI_Read_Link_Supervision_Timeout 0x36 +#define OCF_HCI_Write_Link_Supervision_Timeout 0x37 +#define OCF_HCI_Enhanced_Flush 0x5F +#define OCF_HCI_Read_Logical_Link_Accept_Timeout 0x61 +#define OCF_HCI_Write_Logical_Link_Accept_Timeout 0x62 +#define OCF_HCI_Set_Event_Mask_Page_2 0x63 +#define OCF_HCI_Read_Location_Data 0x64 +#define OCF_HCI_Write_Location_Data 0x65 +#define OCF_HCI_Read_Flow_Control_Mode 0x66 +#define OCF_HCI_Write_Flow_Control_Mode 0x67 +#define OCF_HCI_Read_BE_Flush_Timeout 0x69 +#define OCF_HCI_Write_BE_Flush_Timeout 0x6A +#define OCF_HCI_Short_Range_Mode 0x6B + + +/*======== Info Commands Opcode========================*/ +#define OCF_HCI_Read_Local_Ver_Info 0x01 +#define OCF_HCI_Read_Local_Supported_Cmds 0x02 +#define OCF_HCI_Read_Data_Block_Size 0x0A +/*======== Status Commands Opcode======================*/ +#define OCF_HCI_Read_Failed_Contact_Counter 0x01 +#define OCF_HCI_Reset_Failed_Contact_Counter 0x02 +#define OCF_HCI_Read_Link_Quality 0x03 +#define OCF_HCI_Read_RSSI 0x05 +#define OCF_HCI_Read_Local_AMP_Info 0x09 +#define OCF_HCI_Read_Local_AMP_ASSOC 0x0A +#define OCF_HCI_Write_Remote_AMP_ASSOC 0x0B + + +/*======= AMP_ASSOC Specific TLV tags =================*/ +#define AMP_ASSOC_MAC_ADDRESS_INFO_TYPE 0x1 +#define AMP_ASSOC_PREF_CHAN_LIST 0x2 +#define AMP_ASSOC_CONNECTED_CHAN 0x3 +#define AMP_ASSOC_PAL_CAPABILITIES 0x4 +#define AMP_ASSOC_PAL_VERSION 0x5 + + +/*========= PAL Events =================================*/ +#define PAL_COMMAND_COMPLETE_EVENT 0x0E +#define PAL_COMMAND_STATUS_EVENT 0x0F +#define PAL_HARDWARE_ERROR_EVENT 0x10 +#define PAL_FLUSH_OCCURRED_EVENT 0x11 +#define PAL_LOOPBACK_EVENT 0x19 +#define PAL_BUFFER_OVERFLOW_EVENT 0x1A +#define PAL_QOS_VIOLATION_EVENT 0x1E +#define PAL_ENHANCED_FLUSH_COMPLT_EVENT 0x39 +#define PAL_PHYSICAL_LINK_COMPL_EVENT 0x40 +#define PAL_CHANNEL_SELECT_EVENT 0x41 +#define PAL_DISCONNECT_PHYSICAL_LINK_EVENT 0x42 +#define PAL_PHY_LINK_EARLY_LOSS_WARNING_EVENT 0x43 +#define PAL_PHY_LINK_RECOVERY_EVENT 0x44 +#define PAL_LOGICAL_LINK_COMPL_EVENT 0x45 +#define PAL_DISCONNECT_LOGICAL_LINK_COMPL_EVENT 0x46 +#define PAL_FLOW_SPEC_MODIFY_COMPL_EVENT 0x47 +#define PAL_NUM_COMPL_DATA_BLOCK_EVENT 0x48 +#define PAL_SHORT_RANGE_MODE_CHANGE_COMPL_EVENT 0x4C +#define PAL_AMP_STATUS_CHANGE_EVENT 0x4D +/*======== End of PAL events definiton =================*/ + + +/*======== Timeouts (not part of HCI cmd, but input to PAL engine) =========*/ +#define Timer_Conn_Accept_TO 0x01 +#define Timer_Link_Supervision_TO 0x02 + +#define NUM_HCI_COMMAND_PKTS 0x1 + + +/*====== NOP Cmd ============================*/ +#define HCI_CMD_NOP HCI_FORM_OPCODE(OCF_NOP, OGF_NOP) + + +/*===== Link Control Commands================*/ +#define HCI_Create_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Physical_Link, OGF_LINK_CONTROL) +#define HCI_Accept_Physical_Link_Req HCI_FORM_OPCODE(OCF_HCI_Accept_Physical_Link_Req, OGF_LINK_CONTROL) +#define HCI_Disconnect_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Physical_Link, OGF_LINK_CONTROL) +#define HCI_Create_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Logical_Link, OGF_LINK_CONTROL) +#define HCI_Accept_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Accept_Logical_Link, OGF_LINK_CONTROL) +#define HCI_Disconnect_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Logical_Link, OGF_LINK_CONTROL) +#define HCI_Logical_Link_Cancel HCI_FORM_OPCODE(OCF_HCI_Logical_Link_Cancel, OGF_LINK_CONTROL) +#define HCI_Flow_Spec_Modify HCI_FORM_OPCODE(OCF_HCI_Flow_Spec_Modify, OGF_LINK_CONTROL) + + +/*===== Link Policy Commands ================*/ +#define HCI_Set_Event_Mask HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask, OGF_LINK_POLICY) +#define HCI_Reset HCI_FORM_OPCODE(OCF_HCI_Reset, OGF_LINK_POLICY) +#define HCI_Enhanced_Flush HCI_FORM_OPCODE(OCF_HCI_Enhanced_Flush, OGF_LINK_POLICY) +#define HCI_Read_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Conn_Accept_Timeout, OGF_LINK_POLICY) +#define HCI_Write_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Conn_Accept_Timeout, OGF_LINK_POLICY) +#define HCI_Read_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Logical_Link_Accept_Timeout, OGF_LINK_POLICY) +#define HCI_Write_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Logical_Link_Accept_Timeout, OGF_LINK_POLICY) +#define HCI_Read_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Link_Supervision_Timeout, OGF_LINK_POLICY) +#define HCI_Write_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Link_Supervision_Timeout, OGF_LINK_POLICY) +#define HCI_Read_Location_Data HCI_FORM_OPCODE(OCF_HCI_Read_Location_Data, OGF_LINK_POLICY) +#define HCI_Write_Location_Data HCI_FORM_OPCODE(OCF_HCI_Write_Location_Data, OGF_LINK_POLICY) +#define HCI_Set_Event_Mask_Page_2 HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask_Page_2, OGF_LINK_POLICY) +#define HCI_Read_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Read_Flow_Control_Mode, OGF_LINK_POLICY) +#define HCI_Write_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Write_Flow_Control_Mode, OGF_LINK_POLICY) +#define HCI_Write_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_BE_Flush_Timeout, OGF_LINK_POLICY) +#define HCI_Read_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_BE_Flush_Timeout, OGF_LINK_POLICY) +#define HCI_Short_Range_Mode HCI_FORM_OPCODE(OCF_HCI_Short_Range_Mode, OGF_LINK_POLICY) + + +/*===== Info Commands =====================*/ +#define HCI_Read_Local_Ver_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_Ver_Info, OGF_INFO_PARAMS) +#define HCI_Read_Local_Supported_Cmds HCI_FORM_OPCODE(OCF_HCI_Read_Local_Supported_Cmds, OGF_INFO_PARAMS) +#define HCI_Read_Data_Block_Size HCI_FORM_OPCODE(OCF_HCI_Read_Data_Block_Size, OGF_INFO_PARAMS) + +/*===== Status Commands =====================*/ +#define HCI_Read_Link_Quality HCI_FORM_OPCODE(OCF_HCI_Read_Link_Quality, OGF_STATUS) +#define HCI_Read_RSSI HCI_FORM_OPCODE(OCF_HCI_Read_RSSI, OGF_STATUS) +#define HCI_Read_Local_AMP_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_Info, OGF_STATUS) +#define HCI_Read_Local_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_ASSOC, OGF_STATUS) +#define HCI_Write_Remote_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Write_Remote_AMP_ASSOC, OGF_STATUS) + +/*====== End of cmd definitions =============*/ + + + +/*===== Timeouts(private - can't come from HCI)=================*/ +#define Conn_Accept_TO HCI_FORM_OPCODE(Timer_Conn_Accept_TO, OGF_VENDOR_DEBUG) +#define Link_Supervision_TO HCI_FORM_OPCODE(Timer_Link_Supervision_TO, OGF_VENDOR_DEBUG) + +/*----- PAL Constants (Sec 6 of Doc)------------------------*/ +#define Max80211_PAL_PDU_Size 1492 +#define Max80211_AMP_ASSOC_Len 672 +#define MinGUserPrio 4 +#define MaxGUserPrio 7 +#define BEUserPrio0 0 +#define BEUserPrio1 3 +#define Max80211BeaconPeriod 2000 /* in millisec */ +#define ShortRangeModePowerMax 4 /* dBm */ + +/*------ PAL Protocol Identifiers (Sec5.1) ------------------*/ +typedef enum { + ACL_DATA = 0x01, + ACTIVITY_REPORT, + SECURED_FRAMES, + LINK_SUPERVISION_REQ, + LINK_SUPERVISION_RESP, +}PAL_PROTOCOL_IDENTIFIERS; + +#define HCI_CMD_HDR_SZ 3 +#define HCI_EVENT_HDR_SIZE 2 +#define MAX_EVT_PKT_SZ 255 +#define AMP_ASSOC_MAX_FRAG_SZ 248 +#define AMP_MAX_GUARANTEED_BW 20000 + +#define DEFAULT_CONN_ACCPT_TO 5000 +#define DEFAULT_LL_ACCPT_TO 5000 +#define DEFAULT_LSTO 10000 + +#define PACKET_BASED_FLOW_CONTROL_MODE 0x00 +#define DATA_BLK_BASED_FLOW_CONTROL_MODE 0x01 + +#define SERVICE_TYPE_BEST_EFFORT 0x01 +#define SERVICE_TYPE_GUARANTEED 0x02 + +#define MAC_ADDR_LEN 6 +#define LINK_KEY_LEN 32 + +typedef enum { + ACL_DATA_PB_1ST_NON_AUTOMATICALLY_FLUSHABLE = 0x00, + ACL_DATA_PB_CONTINUING_FRAGMENT = 0x01, + ACL_DATA_PB_1ST_AUTOMATICALLY_FLUSHABLE = 0x02, + ACL_DATA_PB_COMPLETE_PDU = 0x03, +} ACL_DATA_PB_FLAGS; +#define ACL_DATA_PB_FLAGS_SHIFT 12 + +typedef enum { + ACL_DATA_BC_POINT_TO_POINT = 0x00, +} ACL_DATA_BC_FLAGS; +#define ACL_DATA_BC_FLAGS_SHIFT 14 + +/* Command pkt */ +typedef struct hci_cmd_pkt_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 params[255]; +} POSTPACK HCI_CMD_PKT; + +#define ACL_DATA_HDR_SIZE 4 /* hdl_and flags + data_len */ +/* Data pkt */ +typedef struct hci_acl_data_pkt_t { + A_UINT16 hdl_and_flags; + A_UINT16 data_len; + A_UINT8 data[Max80211_PAL_PDU_Size]; +} POSTPACK HCI_ACL_DATA_PKT; + +/* Event pkt */ +typedef struct hci_event_pkt_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 params[256]; +} POSTPACK HCI_EVENT_PKT; + + +/*============== HCI Command definitions ======================= */ +typedef struct hci_cmd_phy_link_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT8 link_key_len; + A_UINT8 link_key_type; + A_UINT8 link_key[LINK_KEY_LEN]; +} POSTPACK HCI_CMD_PHY_LINK; + +typedef struct hci_cmd_write_rem_amp_assoc_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT16 len_so_far; + A_UINT16 amp_assoc_remaining_len; + A_UINT8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ]; +} POSTPACK HCI_CMD_WRITE_REM_AMP_ASSOC; + + +typedef struct hci_cmd_opcode_hdl_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 hdl; +} POSTPACK HCI_CMD_READ_LINK_QUAL, + HCI_CMD_FLUSH, + HCI_CMD_READ_LINK_SUPERVISION_TIMEOUT; + +typedef struct hci_cmd_read_local_amp_assoc_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT16 len_so_far; + A_UINT16 max_rem_amp_assoc_len; +} POSTPACK HCI_CMD_READ_LOCAL_AMP_ASSOC; + + +typedef struct hci_cmd_set_event_mask_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT64 mask; +}POSTPACK HCI_CMD_SET_EVT_MASK, HCI_CMD_SET_EVT_MASK_PG_2; + + +typedef struct hci_cmd_enhanced_flush_t{ + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 hdl; + A_UINT8 type; +} POSTPACK HCI_CMD_ENHANCED_FLUSH; + + +typedef struct hci_cmd_write_timeout_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 timeout; +} POSTPACK HCI_CMD_WRITE_TIMEOUT; + +typedef struct hci_cmd_write_link_supervision_timeout_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 hdl; + A_UINT16 timeout; +} POSTPACK HCI_CMD_WRITE_LINK_SUPERVISION_TIMEOUT; + +typedef struct hci_cmd_write_flow_control_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 mode; +} POSTPACK HCI_CMD_WRITE_FLOW_CONTROL; + +typedef struct location_data_cfg_t { + A_UINT8 reg_domain_aware; + A_UINT8 reg_domain[3]; + A_UINT8 reg_options; +} POSTPACK LOCATION_DATA_CFG; + +typedef struct hci_cmd_write_location_data_t { + A_UINT16 opcode; + A_UINT8 param_length; + LOCATION_DATA_CFG cfg; +} POSTPACK HCI_CMD_WRITE_LOCATION_DATA; + + +typedef struct flow_spec_t { + A_UINT8 id; + A_UINT8 service_type; + A_UINT16 max_sdu; + A_UINT32 sdu_inter_arrival_time; + A_UINT32 access_latency; + A_UINT32 flush_timeout; +} POSTPACK FLOW_SPEC; + + +typedef struct hci_cmd_create_logical_link_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + FLOW_SPEC tx_flow_spec; + FLOW_SPEC rx_flow_spec; +} POSTPACK HCI_CMD_CREATE_LOGICAL_LINK; + +typedef struct hci_cmd_flow_spec_modify_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 hdl; + FLOW_SPEC tx_flow_spec; + FLOW_SPEC rx_flow_spec; +} POSTPACK HCI_CMD_FLOW_SPEC_MODIFY; + +typedef struct hci_cmd_logical_link_cancel_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT8 tx_flow_spec_id; +} POSTPACK HCI_CMD_LOGICAL_LINK_CANCEL; + +typedef struct hci_cmd_disconnect_logical_link_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 logical_link_hdl; +} POSTPACK HCI_CMD_DISCONNECT_LOGICAL_LINK; + +typedef struct hci_cmd_disconnect_phy_link_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; +} POSTPACK HCI_CMD_DISCONNECT_PHY_LINK; + +typedef struct hci_cmd_srm_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT8 mode; +} POSTPACK HCI_CMD_SHORT_RANGE_MODE; +/*============== HCI Command definitions end ======================= */ + + + +/*============== HCI Event definitions ============================= */ + +/* Command complete event */ +typedef struct hci_event_cmd_complete_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 num_hci_cmd_pkts; + A_UINT16 opcode; + A_UINT8 params[255]; +} POSTPACK HCI_EVENT_CMD_COMPLETE; + + +/* Command status event */ +typedef struct hci_event_cmd_status_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 num_hci_cmd_pkts; + A_UINT16 opcode; +} POSTPACK HCI_EVENT_CMD_STATUS; + +/* Hardware Error event */ +typedef struct hci_event_hw_err_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 hw_err_code; +} POSTPACK HCI_EVENT_HW_ERR; + +/* Flush occured event */ +/* Qos Violation event */ +typedef struct hci_event_handle_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT16 handle; +} POSTPACK HCI_EVENT_FLUSH_OCCRD, + HCI_EVENT_QOS_VIOLATION; + +/* Loopback command event */ +typedef struct hci_loopback_cmd_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 params[252]; +} POSTPACK HCI_EVENT_LOOPBACK_CMD; + +/* Data buffer overflow event */ +typedef struct hci_data_buf_overflow_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 link_type; +} POSTPACK HCI_EVENT_DATA_BUF_OVERFLOW; + +/* Enhanced Flush complete event */ +typedef struct hci_enhanced_flush_complt_t{ + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT16 hdl; +} POSTPACK HCI_EVENT_ENHANCED_FLUSH_COMPLT; + +/* Channel select event */ +typedef struct hci_event_chan_select_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 phy_link_hdl; +} POSTPACK HCI_EVENT_CHAN_SELECT; + +/* Physical Link Complete event */ +typedef struct hci_event_phy_link_complete_event_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 phy_link_hdl; +} POSTPACK HCI_EVENT_PHY_LINK_COMPLETE; + +/* Logical Link complete event */ +typedef struct hci_event_logical_link_complete_event_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT16 logical_link_hdl; + A_UINT8 phy_hdl; + A_UINT8 tx_flow_id; +} POSTPACK HCI_EVENT_LOGICAL_LINK_COMPLETE_EVENT; + +/* Disconnect Logical Link complete event */ +typedef struct hci_event_disconnect_logical_link_event_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT16 logical_link_hdl; + A_UINT8 reason; +} POSTPACK HCI_EVENT_DISCONNECT_LOGICAL_LINK_EVENT; + +/* Disconnect Physical Link complete event */ +typedef struct hci_event_disconnect_phy_link_complete_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 phy_link_hdl; + A_UINT8 reason; +} POSTPACK HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE; + +typedef struct hci_event_physical_link_loss_early_warning_t{ + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 phy_hdl; + A_UINT8 reason; +} POSTPACK HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING; + +typedef struct hci_event_physical_link_recovery_t{ + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 phy_hdl; +} POSTPACK HCI_EVENT_PHY_LINK_RECOVERY; + + +/* Flow spec modify complete event */ +/* Flush event */ +typedef struct hci_event_status_handle_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT16 handle; +} POSTPACK HCI_EVENT_FLOW_SPEC_MODIFY, + HCI_EVENT_FLUSH; + + +/* Num of completed data blocks event */ +typedef struct hci_event_num_of_compl_data_blks_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT16 num_data_blks; + A_UINT8 num_handles; + A_UINT8 params[255]; +} POSTPACK HCI_EVENT_NUM_COMPL_DATA_BLKS; + +/* Short range mode change complete event */ +typedef struct hci_srm_cmpl_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 phy_link; + A_UINT8 state; +} POSTPACK HCI_EVENT_SRM_COMPL; + +typedef struct hci_event_amp_status_change_t{ + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 amp_status; +} POSTPACK HCI_EVENT_AMP_STATUS_CHANGE; + +/*============== Event definitions end =========================== */ + + +typedef struct local_amp_info_resp_t { + A_UINT8 status; + A_UINT8 amp_status; + A_UINT32 total_bw; /* kbps */ + A_UINT32 max_guranteed_bw; /* kbps */ + A_UINT32 min_latency; + A_UINT32 max_pdu_size; + A_UINT8 amp_type; + A_UINT16 pal_capabilities; + A_UINT16 amp_assoc_len; + A_UINT32 max_flush_timeout; /* in ms */ + A_UINT32 be_flush_timeout; /* in ms */ +} POSTPACK LOCAL_AMP_INFO; + +typedef struct amp_assoc_cmd_resp_t{ + A_UINT8 status; + A_UINT8 phy_hdl; + A_UINT16 amp_assoc_len; + A_UINT8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ]; +}POSTPACK AMP_ASSOC_CMD_RESP; + + +enum PAL_HCI_CMD_STATUS { + PAL_HCI_CMD_PROCESSED, + PAL_HCI_CMD_IGNORED +}; + + +/*============= HCI Error Codes =======================*/ +#define HCI_SUCCESS 0x00 +#define HCI_ERR_UNKNOW_CMD 0x01 +#define HCI_ERR_UNKNOWN_CONN_ID 0x02 +#define HCI_ERR_HW_FAILURE 0x03 +#define HCI_ERR_PAGE_TIMEOUT 0x04 +#define HCI_ERR_AUTH_FAILURE 0x05 +#define HCI_ERR_KEY_MISSING 0x06 +#define HCI_ERR_MEM_CAP_EXECED 0x07 +#define HCI_ERR_CON_TIMEOUT 0x08 +#define HCI_ERR_CON_LIMIT_EXECED 0x09 +#define HCI_ERR_ACL_CONN_ALRDY_EXISTS 0x0B +#define HCI_ERR_COMMAND_DISALLOWED 0x0C +#define HCI_ERR_CONN_REJ_BY_LIMIT_RES 0x0D +#define HCI_ERR_CONN_REJ_BY_SEC 0x0E +#define HCI_ERR_CONN_REJ_BY_BAD_ADDR 0x0F +#define HCI_ERR_CONN_ACCPT_TIMEOUT 0x10 +#define HCI_ERR_UNSUPPORT_FEATURE 0x11 +#define HCI_ERR_INVALID_HCI_CMD_PARAMS 0x12 +#define HCI_ERR_REMOTE_USER_TERMINATE_CONN 0x13 +#define HCI_ERR_CON_TERM_BY_HOST 0x16 +#define HCI_ERR_UNSPECIFIED_ERROR 0x1F +#define HCI_ERR_ENCRYPTION_MODE_NOT_SUPPORT 0x25 +#define HCI_ERR_REQUESTED_QOS_NOT_SUPPORT 0x27 +#define HCI_ERR_QOS_UNACCEPTABLE_PARM 0x2C +#define HCI_ERR_QOS_REJECTED 0x2D +#define HCI_ERR_CONN_REJ_NO_SUITABLE_CHAN 0x39 + +/*============= HCI Error Codes End =======================*/ + + +/* Following are event return parameters.. part of HCI events + */ +typedef struct timeout_read_t { + A_UINT8 status; + A_UINT16 timeout; +}POSTPACK TIMEOUT_INFO; + +typedef struct link_supervision_timeout_read_t { + A_UINT8 status; + A_UINT16 hdl; + A_UINT16 timeout; +}POSTPACK LINK_SUPERVISION_TIMEOUT_INFO; + +typedef struct status_hdl_t { + A_UINT8 status; + A_UINT16 hdl; +}POSTPACK INFO_STATUS_HDL; + +typedef struct write_remote_amp_assoc_t{ + A_UINT8 status; + A_UINT8 hdl; +}POSTPACK WRITE_REMOTE_AMP_ASSOC_INFO; + +typedef struct read_loc_info_t { + A_UINT8 status; + LOCATION_DATA_CFG loc; +}POSTPACK READ_LOC_INFO; + +typedef struct read_flow_ctrl_mode_t { + A_UINT8 status; + A_UINT8 mode; +}POSTPACK READ_FLWCTRL_INFO; + +typedef struct read_data_blk_size_t { + A_UINT8 status; + A_UINT16 max_acl_data_pkt_len; + A_UINT16 data_block_len; + A_UINT16 total_num_data_blks; +}POSTPACK READ_DATA_BLK_SIZE_INFO; + +/* Read Link quality info */ +typedef struct link_qual_t { + A_UINT8 status; + A_UINT16 hdl; + A_UINT8 link_qual; +} POSTPACK READ_LINK_QUAL_INFO, + READ_RSSI_INFO; + +typedef struct ll_cancel_resp_t { + A_UINT8 status; + A_UINT8 phy_link_hdl; + A_UINT8 tx_flow_spec_id; +} POSTPACK LL_CANCEL_RESP; + +typedef struct read_local_ver_info_t { + A_UINT8 status; + A_UINT8 hci_version; + A_UINT16 hci_revision; + A_UINT8 pal_version; + A_UINT16 manf_name; + A_UINT16 pal_sub_ver; +} POSTPACK READ_LOCAL_VER_INFO; + + +#endif /* __A_HCI_H__ */ diff --git a/drivers/staging/ath6kl/include/common/athdefs.h b/drivers/staging/ath6kl/include/common/athdefs.h new file mode 100644 index 000000000000..b59bfd3af0a5 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/athdefs.h @@ -0,0 +1,84 @@ +//------------------------------------------------------------------------------ +// <copyright file="athdefs.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHDEFS_H__ +#define __ATHDEFS_H__ + +/* + * This file contains definitions that may be used across both + * Host and Target software. Nothing here is module-dependent + * or platform-dependent. + */ + +/* + * Generic error codes that can be used by hw, sta, ap, sim, dk + * and any other environments. Since these are enums, feel free to + * add any more codes that you need. + */ + +typedef enum { + A_ERROR = -1, /* Generic error return */ + A_OK = 0, /* success */ + /* Following values start at 1 */ + A_DEVICE_NOT_FOUND, /* not able to find PCI device */ + A_NO_MEMORY, /* not able to allocate memory, not available */ + A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ + A_NO_FREE_DESC, /* no free descriptors available */ + A_BAD_ADDRESS, /* address does not match descriptor */ + A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ + A_REGS_NOT_MAPPED, /* registers not correctly mapped */ + A_EPERM, /* Not superuser */ + A_EACCES, /* Access denied */ + A_ENOENT, /* No such entry, search failed, etc. */ + A_EEXIST, /* The object already exists (can't create) */ + A_EFAULT, /* Bad address fault */ + A_EBUSY, /* Object is busy */ + A_EINVAL, /* Invalid parameter */ + A_EMSGSIZE, /* Inappropriate message buffer length */ + A_ECANCELED, /* Operation canceled */ + A_ENOTSUP, /* Operation not supported */ + A_ECOMM, /* Communication error on send */ + A_EPROTO, /* Protocol error */ + A_ENODEV, /* No such device */ + A_EDEVNOTUP, /* device is not UP */ + A_NO_RESOURCE, /* No resources for requested operation */ + A_HARDWARE, /* Hardware failure */ + A_PENDING, /* Asynchronous routine; will send up results la +ter (typically in callback) */ + A_EBADCHANNEL, /* The channel cannot be used */ + A_DECRYPT_ERROR, /* Decryption error */ + A_PHY_ERROR, /* RX PHY error */ + A_CONSUMED /* Object was consumed */ +} A_STATUS; + +#define A_SUCCESS(x) (x == A_OK) +#define A_FAILED(x) (!A_SUCCESS(x)) + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#endif /* __ATHDEFS_H__ */ diff --git a/drivers/staging/ath6kl/include/common/bmi_msg.h b/drivers/staging/ath6kl/include/common/bmi_msg.h new file mode 100644 index 000000000000..f9687d325b2f --- /dev/null +++ b/drivers/staging/ath6kl/include/common/bmi_msg.h @@ -0,0 +1,241 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// +// Author(s): ="Atheros" +//------------------------------------------------------------------------------ + +#ifndef __BMI_MSG_H__ +#define __BMI_MSG_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +/* + * Bootloader Messaging Interface (BMI) + * + * BMI is a very simple messaging interface used during initialization + * to read memory, write memory, execute code, and to define an + * application entry PC. + * + * It is used to download an application to AR6K, to provide + * patches to code that is already resident on AR6K, and generally + * to examine and modify state. The Host has an opportunity to use + * BMI only once during bootup. Once the Host issues a BMI_DONE + * command, this opportunity ends. + * + * The Host writes BMI requests to mailbox0, and reads BMI responses + * from mailbox0. BMI requests all begin with a command + * (see below for specific commands), and are followed by + * command-specific data. + * + * Flow control: + * The Host can only issue a command once the Target gives it a + * "BMI Command Credit", using AR6K Counter #4. As soon as the + * Target has completed a command, it issues another BMI Command + * Credit (so the Host can issue the next command). + * + * BMI handles all required Target-side cache flushing. + */ + + +/* Maximum data size used for BMI transfers */ +#define BMI_DATASZ_MAX 256 + +/* BMI Commands */ + +#define BMI_NO_COMMAND 0 + +#define BMI_DONE 1 + /* + * Semantics: Host is done using BMI + * Request format: + * A_UINT32 command (BMI_DONE) + * Response format: none + */ + +#define BMI_READ_MEMORY 2 + /* + * Semantics: Host reads AR6K memory + * Request format: + * A_UINT32 command (BMI_READ_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * Response format: + * A_UINT8 data[length] + */ + +#define BMI_WRITE_MEMORY 3 + /* + * Semantics: Host writes AR6K memory + * Request format: + * A_UINT32 command (BMI_WRITE_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * A_UINT8 data[length] + * Response format: none + */ + +#define BMI_EXECUTE 4 + /* + * Semantics: Causes AR6K to execute code + * Request format: + * A_UINT32 command (BMI_EXECUTE) + * A_UINT32 address + * A_UINT32 parameter + * Response format: + * A_UINT32 return value + */ + +#define BMI_SET_APP_START 5 + /* + * Semantics: Set Target application starting address + * Request format: + * A_UINT32 command (BMI_SET_APP_START) + * A_UINT32 address + * Response format: none + */ + +#define BMI_READ_SOC_REGISTER 6 + /* + * Semantics: Read a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_READ_REGISTER) + * A_UINT32 address + * Response format: + * A_UINT32 value + */ + +#define BMI_WRITE_SOC_REGISTER 7 + /* + * Semantics: Write a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_WRITE_REGISTER) + * A_UINT32 address + * A_UINT32 value + * + * Response format: none + */ + +#define BMI_GET_TARGET_ID 8 +#define BMI_GET_TARGET_INFO 8 + /* + * Semantics: Fetch the 4-byte Target information + * Request format: + * A_UINT32 command (BMI_GET_TARGET_ID/INFO) + * Response format1 (old firmware): + * A_UINT32 TargetVersionID + * Response format2 (newer firmware): + * A_UINT32 TARGET_VERSION_SENTINAL + * struct bmi_target_info; + */ + +PREPACK struct bmi_target_info { + A_UINT32 target_info_byte_count; /* size of this structure */ + A_UINT32 target_ver; /* Target Version ID */ + A_UINT32 target_type; /* Target type */ +} POSTPACK; +#define TARGET_VERSION_SENTINAL 0xffffffff +#define TARGET_TYPE_AR6001 1 +#define TARGET_TYPE_AR6002 2 +#define TARGET_TYPE_AR6003 3 + + +#define BMI_ROMPATCH_INSTALL 9 + /* + * Semantics: Install a ROM Patch. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_INSTALL) + * A_UINT32 Target ROM Address + * A_UINT32 Target RAM Address or Value (depending on Target Type) + * A_UINT32 Size, in bytes + * A_UINT32 Activate? 1-->activate; + * 0-->install but do not activate + * Response format: + * A_UINT32 PatchID + */ + +#define BMI_ROMPATCH_UNINSTALL 10 + /* + * Semantics: Uninstall a previously-installed ROM Patch, + * automatically deactivating, if necessary. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_UNINSTALL) + * A_UINT32 PatchID + * + * Response format: none + */ + +#define BMI_ROMPATCH_ACTIVATE 11 + /* + * Semantics: Activate a list of previously-installed ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_ACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_ROMPATCH_DEACTIVATE 12 + /* + * Semantics: Deactivate a list of active ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_DEACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + + +#define BMI_LZ_STREAM_START 13 + /* + * Semantics: Begin an LZ-compressed stream of input + * which is to be uncompressed by the Target to an + * output buffer at address. The output buffer must + * be sufficiently large to hold the uncompressed + * output from the compressed input stream. This BMI + * command should be followed by a series of 1 or more + * BMI_LZ_DATA commands. + * A_UINT32 command (BMI_LZ_STREAM_START) + * A_UINT32 address + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_LZ_DATA 14 + /* + * Semantics: Host writes AR6K memory with LZ-compressed + * data which is uncompressed by the Target. This command + * must be preceded by a BMI_LZ_STREAM_START command. A series + * of BMI_LZ_DATA commands are considered part of a single + * input stream until another BMI_LZ_STREAM_START is issued. + * Request format: + * A_UINT32 command (BMI_LZ_DATA) + * A_UINT32 length (of compressed data), + * at most BMI_DATASZ_MAX + * A_UINT8 CompressedData[length] + * Response format: none + * Note: Not supported on all versions of ROM firmware. + */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* __BMI_MSG_H__ */ diff --git a/drivers/staging/ath6kl/include/common/btcoexGpio.h b/drivers/staging/ath6kl/include/common/btcoexGpio.h new file mode 100644 index 000000000000..bc067f557eaa --- /dev/null +++ b/drivers/staging/ath6kl/include/common/btcoexGpio.h @@ -0,0 +1,86 @@ +// Copyright (c) 2010 Atheros Communications Inc. +// All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// + +#ifndef BTCOEX_GPIO_H_ +#define BTCOEX_GPIO_H_ + + + +#ifdef FPGA +#define GPIO_A (15) +#define GPIO_B (16) +#define GPIO_C (17) +#define GPIO_D (18) +#define GPIO_E (19) +#define GPIO_F (21) +#define GPIO_G (21) +#else +#define GPIO_A (0) +#define GPIO_B (5) +#define GPIO_C (6) +#define GPIO_D (7) +#define GPIO_E (7) +#define GPIO_F (7) +#define GPIO_G (7) +#endif + + + + + +#define GPIO_DEBUG_WORD_1 (1<<GPIO_A) +#define GPIO_DEBUG_WORD_2 (1<<GPIO_B) +#define GPIO_DEBUG_WORD_3 ((1<<GPIO_B) | (1<<GPIO_A)) +#define GPIO_DEBUG_WORD_4 (1<<GPIO_C) +#define GPIO_DEBUG_WORD_5 ((1<<GPIO_C) | (1<<GPIO_A)) +#define GPIO_DEBUG_WORD_6 ((1<<GPIO_C) | (1<<GPIO_B)) +#define GPIO_DEBUG_WORD_7 ((1<<GPIO_C) | (1<<GPIO_B) | (1<<GPIO_A)) + +#define GPIO_DEBUG_WORD_8 (1<<GPIO_D) +#define GPIO_DEBUG_WORD_9 ((1<<GPIO_D) | GPIO_DEBUG_WORD_1) +#define GPIO_DEBUG_WORD_10 ((1<<GPIO_D) | GPIO_DEBUG_WORD_2) +#define GPIO_DEBUG_WORD_11 ((1<<GPIO_D) | GPIO_DEBUG_WORD_3) +#define GPIO_DEBUG_WORD_12 ((1<<GPIO_D) | GPIO_DEBUG_WORD_4) +#define GPIO_DEBUG_WORD_13 ((1<<GPIO_D) | GPIO_DEBUG_WORD_5) +#define GPIO_DEBUG_WORD_14 ((1<<GPIO_D) | GPIO_DEBUG_WORD_6) +#define GPIO_DEBUG_WORD_15 ((1<<GPIO_D) | GPIO_DEBUG_WORD_7) + +#define GPIO_DEBUG_WORD_16 (1<<GPIO_E) +#define GPIO_DEBUG_WORD_17 ((1<<GPIO_E) | GPIO_DEBUG_WORD_1) +#define GPIO_DEBUG_WORD_18 ((1<<GPIO_E) | GPIO_DEBUG_WORD_2) +#define GPIO_DEBUG_WORD_19 ((1<<GPIO_E) | GPIO_DEBUG_WORD_3) +#define GPIO_DEBUG_WORD_20 ((1<<GPIO_E) | GPIO_DEBUG_WORD_4) +#define GPIO_DEBUG_WORD_21 ((1<<GPIO_E) | GPIO_DEBUG_WORD_5) +#define GPIO_DEBUG_WORD_22 ((1<<GPIO_E) | GPIO_DEBUG_WORD_6) +#define GPIO_DEBUG_WORD_23 ((1<<GPIO_E) | GPIO_DEBUG_WORD_7) + + + +extern void btcoexDbgPulseWord(A_UINT32 gpioPinMask); +extern void btcoexDbgPulse(A_UINT32 pin); + +#ifdef CONFIG_BTCOEX_ENABLE_GPIO_DEBUG +#define BTCOEX_DBG_PULSE_WORD(gpioPinMask) (btcoexDbgPulseWord(gpioPinMask)) +#define BTCOEX_DBG_PULSE(pin) (btcoexDbgPulse(pin)) +#else +#define BTCOEX_DBG_PULSE_WORD(gpioPinMask) +#define BTCOEX_DBG_PULSE(pin) + +#endif +#endif + diff --git a/drivers/staging/ath6kl/include/common/cnxmgmt.h b/drivers/staging/ath6kl/include/common/cnxmgmt.h new file mode 100644 index 000000000000..7a902cb54831 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/cnxmgmt.h @@ -0,0 +1,36 @@ +//------------------------------------------------------------------------------ +// <copyright file="cnxmgmt.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _CNXMGMT_H_ +#define _CNXMGMT_H_ + +typedef enum { + CM_CONNECT_WITHOUT_SCAN = 0x0001, + CM_CONNECT_ASSOC_POLICY_USER = 0x0002, + CM_CONNECT_SEND_REASSOC = 0x0004, + CM_CONNECT_WITHOUT_ROAMTABLE_UPDATE = 0x0008, + CM_CONNECT_DO_WPA_OFFLOAD = 0x0010, + CM_CONNECT_DO_NOT_DEAUTH = 0x0020, +} CM_CONNECT_TYPE; + +#endif /* _CNXMGMT_H_ */ diff --git a/drivers/staging/ath6kl/include/common/dbglog.h b/drivers/staging/ath6kl/include/common/dbglog.h new file mode 100644 index 000000000000..382d9a2dd4eb --- /dev/null +++ b/drivers/staging/ath6kl/include/common/dbglog.h @@ -0,0 +1,134 @@ +//------------------------------------------------------------------------------ +// <copyright file="dbglog.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_H_ +#define _DBGLOG_H_ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define DBGLOG_TIMESTAMP_OFFSET 0 +#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit + 8-23 of the LF0 timer */ +#define DBGLOG_DBGID_OFFSET 16 +#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */ +#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */ + +#define DBGLOG_MODULEID_OFFSET 26 +#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */ +#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */ + +/* + * Please ensure that the definition of any new module intrduced is captured + * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The + * structure is required for the parser to correctly pick up the values for + * different modules. + */ +#define DBGLOG_MODULEID_START +#define DBGLOG_MODULEID_INF 0 +#define DBGLOG_MODULEID_WMI 1 +#define DBGLOG_MODULEID_MISC 2 +#define DBGLOG_MODULEID_PM 3 +#define DBGLOG_MODULEID_TXRX_MGMTBUF 4 +#define DBGLOG_MODULEID_TXRX_TXBUF 5 +#define DBGLOG_MODULEID_TXRX_RXBUF 6 +#define DBGLOG_MODULEID_WOW 7 +#define DBGLOG_MODULEID_WHAL 8 +#define DBGLOG_MODULEID_DC 9 +#define DBGLOG_MODULEID_CO 10 +#define DBGLOG_MODULEID_RO 11 +#define DBGLOG_MODULEID_CM 12 +#define DBGLOG_MODULEID_MGMT 13 +#define DBGLOG_MODULEID_TMR 14 +#define DBGLOG_MODULEID_BTCOEX 15 +#define DBGLOG_MODULEID_END + +#define DBGLOG_NUM_ARGS_OFFSET 30 +#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */ +#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */ + +#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0 +#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF + +#define DBGLOG_REPORTING_ENABLED_OFFSET 16 +#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000 + +#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17 +#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000 + +#define DBGLOG_REPORT_SIZE_OFFSET 20 +#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000 + +#define DBGLOG_LOG_BUFFER_SIZE 1500 +#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 + +PREPACK struct dbglog_buf_s { + struct dbglog_buf_s *next; + A_UINT8 *buffer; + A_UINT32 bufsize; + A_UINT32 length; + A_UINT32 count; + A_UINT32 free; +} POSTPACK; + +PREPACK struct dbglog_hdr_s { + struct dbglog_buf_s *dbuf; + A_UINT32 dropped; +} POSTPACK; + +PREPACK struct dbglog_config_s { + A_UINT32 cfgvalid; /* Mask with valid config bits */ + union { + /* TODO: Take care of endianness */ + struct { + A_UINT32 mmask:16; /* Mask of modules with logging on */ + A_UINT32 rep:1; /* Reporting enabled or not */ + A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */ + A_UINT32 size:10; /* Report size in number of messages */ + A_UINT32 reserved:2; + } dbglog_config; + + A_UINT32 value; + } u; +} POSTPACK; + +#define cfgmmask u.dbglog_config.mmask +#define cfgrep u.dbglog_config.rep +#define cfgtsr u.dbglog_config.tsr +#define cfgsize u.dbglog_config.size +#define cfgvalue u.value + +#ifdef __cplusplus +} +#endif + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* _DBGLOG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/dbglog_id.h b/drivers/staging/ath6kl/include/common/dbglog_id.h new file mode 100644 index 000000000000..15ef829cab20 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/dbglog_id.h @@ -0,0 +1,558 @@ +//------------------------------------------------------------------------------ +// <copyright file="dbglog_id.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_ID_H_ +#define _DBGLOG_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The nomenclature for the debug identifiers is MODULE_DESCRIPTION. + * Please ensure that the definition of any new debugid introduced is captured + * between the <MODULE>_DBGID_DEFINITION_START and + * <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the + * parser to correctly pick up the values for different debug identifiers. + */ + +/* INF debug identifier definitions */ +#define INF_DBGID_DEFINITION_START +#define INF_ASSERTION_FAILED 1 +#define INF_TARGET_ID 2 +#define INF_DBGID_DEFINITION_END + +/* WMI debug identifier definitions */ +#define WMI_DBGID_DEFINITION_START +#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1 +#define WMI_EXTENDED_CMD_NOT_HANDLED 2 +#define WMI_CMD_RX_PKT_TOO_SHORT 3 +#define WMI_CALLING_WMI_EXTENSION_FN 4 +#define WMI_CMD_NOT_HANDLED 5 +#define WMI_IN_SYNC 6 +#define WMI_TARGET_WMI_SYNC_CMD 7 +#define WMI_SET_SNR_THRESHOLD_PARAMS 8 +#define WMI_SET_RSSI_THRESHOLD_PARAMS 9 +#define WMI_SET_LQ_TRESHOLD_PARAMS 10 +#define WMI_TARGET_CREATE_PSTREAM_CMD 11 +#define WMI_WI_DTM_INUSE 12 +#define WMI_TARGET_DELETE_PSTREAM_CMD 13 +#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14 +#define WMI_TARGET_GET_BIT_RATE_CMD 15 +#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16 +#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17 +#define WMI_TARGET_GET_TX_PWR_CMD 18 +#define WMI_FREE_EVBUF_WMIBUF 19 +#define WMI_FREE_EVBUF_DATABUF 20 +#define WMI_FREE_EVBUF_BADFLAG 21 +#define WMI_HTC_RX_ERROR_DATA_PACKET 22 +#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23 +#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24 +#define WMI_SENDING_READY_EVENT 25 +#define WMI_SETPOWER_MDOE_TO_MAXPERF 26 +#define WMI_SETPOWER_MDOE_TO_REC 27 +#define WMI_BSSINFO_EVENT_FROM 28 +#define WMI_TARGET_GET_STATS_CMD 29 +#define WMI_SENDING_SCAN_COMPLETE_EVENT 30 +#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31 +#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32 +#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33 +#define WMI_SENDING_ERROR_REPORT_EVENT 34 +#define WMI_SENDING_CAC_EVENT 35 +#define WMI_TARGET_GET_ROAM_TABLE_CMD 36 +#define WMI_TARGET_GET_ROAM_DATA_CMD 37 +#define WMI_SENDING_GPIO_INTR_EVENT 38 +#define WMI_SENDING_GPIO_ACK_EVENT 39 +#define WMI_SENDING_GPIO_DATA_EVENT 40 +#define WMI_CMD_RX 41 +#define WMI_CMD_RX_XTND 42 +#define WMI_EVENT_SEND 43 +#define WMI_EVENT_SEND_XTND 44 +#define WMI_CMD_PARAMS_DUMP_START 45 +#define WMI_CMD_PARAMS_DUMP_END 46 +#define WMI_CMD_PARAMS 47 +#define WMI_DBGID_DEFINITION_END + +/* MISC debug identifier definitions */ +#define MISC_DBGID_DEFINITION_START +#define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR 1 +#define TLPM_INIT 2 +#define TLPM_FILTER_POWER_STATE 3 +#define TLPM_NOTIFY_NOT_IDLE 4 +#define TLPM_TIMEOUT_IDLE_HANDLER 5 +#define TLPM_TIMEOUT_WAKEUP_HANDLER 6 +#define TLPM_WAKEUP_SIGNAL_HANDLER 7 +#define TLPM_UNEXPECTED_GPIO_INTR_ERROR 8 +#define TLPM_BREAK_ON_NOT_RECEIVED_ERROR 9 +#define TLPM_BREAK_OFF_NOT_RECIVED_ERROR 10 +#define TLPM_ACK_GPIO_INTR 11 +#define TLPM_ON 12 +#define TLPM_OFF 13 +#define TLPM_WAKEUP_FROM_HOST 14 +#define TLPM_WAKEUP_FROM_BT 15 +#define TLPM_TX_BREAK_RECIVED 16 +#define TLPM_IDLE_TIMER_NOT_RUNNING 17 +#define MISC_DBGID_DEFINITION_END + +/* TXRX debug identifier definitions */ +#define TXRX_TXBUF_DBGID_DEFINITION_START +#define TXRX_TXBUF_ALLOCATE_BUF 1 +#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2 +#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3 +#define TXRX_TXBUF_TXQ_DEPTH 4 +#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5 +#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6 +#define TXRX_TXBUF_INITIALIZE_TIMER 7 +#define TXRX_TXBUF_ARM_TIMER 8 +#define TXRX_TXBUF_DISARM_TIMER 9 +#define TXRX_TXBUF_UNINITIALIZE_TIMER 10 +#define TXRX_TXBUF_DBGID_DEFINITION_END + +#define TXRX_RXBUF_DBGID_DEFINITION_START +#define TXRX_RXBUF_ALLOCATE_BUF 1 +#define TXRX_RXBUF_QUEUE_TO_HOST 2 +#define TXRX_RXBUF_QUEUE_TO_WLAN 3 +#define TXRX_RXBUF_ZERO_LEN_BUF 4 +#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5 +#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6 +#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7 +#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8 +#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9 +#define TXRX_RXBUF_REQUEUE_ERROR 10 +#define TXRX_RXBUF_DBGID_DEFINITION_END + +#define TXRX_MGMTBUF_DBGID_DEFINITION_START +#define TXRX_MGMTBUF_ALLOCATE_BUF 1 +#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2 +#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3 +#define TXRX_MGMTBUF_GET_BUF 4 +#define TXRX_MGMTBUF_GET_SM_BUF 5 +#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6 +#define TXRX_MGMTBUF_REAPED_BUF 7 +#define TXRX_MGMTBUF_REAPED_SM_BUF 8 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10 +#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11 +#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12 +#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13 +#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14 +#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15 +#define TXRX_MGMTBUF_DRAINQ 16 +#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17 +#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18 +#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19 +#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20 +#define TXRX_MGMTBUF_RESUME_HW_TXQ 21 +#define TXRX_MGMTBUF_TEAR_DOWN_BA 22 +#define TXRX_MGMTBUF_PROCESS_ADDBA_REQ 23 +#define TXRX_MGMTBUF_PROCESS_DELBA 24 +#define TXRX_MGMTBUF_PERFORM_BA 25 +#define TXRX_MGMTBUF_WLAN_RESET_ON_ERROR 26 +#define TXRX_MGMTBUF_DBGID_DEFINITION_END + +/* PM (Power Module) debug identifier definitions */ +#define PM_DBGID_DEFINITION_START +#define PM_INIT 1 +#define PM_ENABLE 2 +#define PM_SET_STATE 3 +#define PM_SET_POWERMODE 4 +#define PM_CONN_NOTIFY 5 +#define PM_REF_COUNT_NEGATIVE 6 +#define PM_INFRA_STA_APSD_ENABLE 7 +#define PM_INFRA_STA_UPDATE_APSD_STATE 8 +#define PM_CHAN_OP_REQ 9 +#define PM_SET_MY_BEACON_POLICY 10 +#define PM_SET_ALL_BEACON_POLICY 11 +#define PM_INFRA_STA_SET_PM_PARAMS1 12 +#define PM_INFRA_STA_SET_PM_PARAMS2 13 +#define PM_ADHOC_SET_PM_CAPS_FAIL 14 +#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15 +#define PM_ADHOC_SET_PM_PARAMS 16 +#define PM_ADHOC_STATE1 18 +#define PM_ADHOC_STATE2 19 +#define PM_ADHOC_CONN_MAP 20 +#define PM_FAKE_SLEEP 21 +#define PM_AP_STATE1 22 +#define PM_AP_SET_PM_PARAMS 23 +#define PM_DBGID_DEFINITION_END + +/* Wake on Wireless debug identifier definitions */ +#define WOW_DBGID_DEFINITION_START +#define WOW_INIT 1 +#define WOW_GET_CONFIG_DSET 2 +#define WOW_NO_CONFIG_DSET 3 +#define WOW_INVALID_CONFIG_DSET 4 +#define WOW_USE_DEFAULT_CONFIG 5 +#define WOW_SETUP_GPIO 6 +#define WOW_INIT_DONE 7 +#define WOW_SET_GPIO_PIN 8 +#define WOW_CLEAR_GPIO_PIN 9 +#define WOW_SET_WOW_MODE_CMD 10 +#define WOW_SET_HOST_MODE_CMD 11 +#define WOW_ADD_WOW_PATTERN_CMD 12 +#define WOW_NEW_WOW_PATTERN_AT_INDEX 13 +#define WOW_DEL_WOW_PATTERN_CMD 14 +#define WOW_LIST_CONTAINS_PATTERNS 15 +#define WOW_GET_WOW_LIST_CMD 16 +#define WOW_INVALID_FILTER_ID 17 +#define WOW_INVALID_FILTER_LISTID 18 +#define WOW_NO_VALID_FILTER_AT_ID 19 +#define WOW_NO_VALID_LIST_AT_ID 20 +#define WOW_NUM_PATTERNS_EXCEEDED 21 +#define WOW_NUM_LISTS_EXCEEDED 22 +#define WOW_GET_WOW_STATS 23 +#define WOW_CLEAR_WOW_STATS 24 +#define WOW_WAKEUP_HOST 25 +#define WOW_EVENT_WAKEUP_HOST 26 +#define WOW_EVENT_DISCARD 27 +#define WOW_PATTERN_MATCH 28 +#define WOW_PATTERN_NOT_MATCH 29 +#define WOW_PATTERN_NOT_MATCH_OFFSET 30 +#define WOW_DISABLED_HOST_ASLEEP 31 +#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32 +#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33 +#define WOW_DBGID_DEFINITION_END + +/* WHAL debug identifier definitions */ +#define WHAL_DBGID_DEFINITION_START +#define WHAL_ERROR_ANI_CONTROL 1 +#define WHAL_ERROR_CHIP_TEST1 2 +#define WHAL_ERROR_CHIP_TEST2 3 +#define WHAL_ERROR_EEPROM_CHECKSUM 4 +#define WHAL_ERROR_EEPROM_MACADDR 5 +#define WHAL_ERROR_INTERRUPT_HIU 6 +#define WHAL_ERROR_KEYCACHE_RESET 7 +#define WHAL_ERROR_KEYCACHE_SET 8 +#define WHAL_ERROR_KEYCACHE_TYPE 9 +#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10 +#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11 +#define WHAL_ERROR_PHY_INVALID_CHANNEL 12 +#define WHAL_ERROR_POWER_AWAKE 13 +#define WHAL_ERROR_POWER_SET 14 +#define WHAL_ERROR_RECV_STOPDMA 15 +#define WHAL_ERROR_RECV_STOPPCU 16 +#define WHAL_ERROR_RESET_CHANNF1 17 +#define WHAL_ERROR_RESET_CHANNF2 18 +#define WHAL_ERROR_RESET_PM 19 +#define WHAL_ERROR_RESET_OFFSETCAL 20 +#define WHAL_ERROR_RESET_RFGRANT 21 +#define WHAL_ERROR_RESET_RXFRAME 22 +#define WHAL_ERROR_RESET_STOPDMA 23 +#define WHAL_ERROR_RESET_RECOVER 24 +#define WHAL_ERROR_XMIT_COMPUTE 25 +#define WHAL_ERROR_XMIT_NOQUEUE 26 +#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27 +#define WHAL_ERROR_XMIT_BADTYPE 28 +#define WHAL_ERROR_XMIT_STOPDMA 29 +#define WHAL_ERROR_INTERRUPT_BB_PANIC 30 +#define WHAL_ERROR_RESET_TXIQCAL 31 +#define WHAL_ERROR_PAPRD_MAXGAIN_ABOVE_WINDOW 32 +#define WHAL_DBGID_DEFINITION_END + +/* DC debug identifier definitions */ +#define DC_DBGID_DEFINITION_START +#define DC_SCAN_CHAN_START 1 +#define DC_SCAN_CHAN_FINISH 2 +#define DC_BEACON_RECEIVE7 3 +#define DC_SSID_PROBE_CB 4 +#define DC_SEND_NEXT_SSID_PROBE 5 +#define DC_START_SEARCH 6 +#define DC_CANCEL_SEARCH_CB 7 +#define DC_STOP_SEARCH 8 +#define DC_END_SEARCH 9 +#define DC_MIN_CHDWELL_TIMEOUT 10 +#define DC_START_SEARCH_CANCELED 11 +#define DC_SET_POWER_MODE 12 +#define DC_INIT 13 +#define DC_SEARCH_OPPORTUNITY 14 +#define DC_RECEIVED_ANY_BEACON 15 +#define DC_RECEIVED_MY_BEACON 16 +#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17 +#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18 +#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19 +#define DC_SET_BEACON_UPDATE 20 +#define DC_BEACON_UPDATE_COMPLETE 21 +#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22 +#define DC_BSSINFO_EVENT_DROPPED 23 +#define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT 24 +#define DC_DBGID_DEFINITION_END + +/* CO debug identifier definitions */ +#define CO_DBGID_DEFINITION_START +#define CO_INIT 1 +#define CO_ACQUIRE_LOCK 2 +#define CO_START_OP1 3 +#define CO_START_OP2 4 +#define CO_DRAIN_TX_COMPLETE_CB 5 +#define CO_CHANGE_CHANNEL_CB 6 +#define CO_RETURN_TO_HOME_CHANNEL 7 +#define CO_FINISH_OP_TIMEOUT 8 +#define CO_OP_END 9 +#define CO_CANCEL_OP 10 +#define CO_CHANGE_CHANNEL 11 +#define CO_RELEASE_LOCK 12 +#define CO_CHANGE_STATE 13 +#define CO_DBGID_DEFINITION_END + +/* RO debug identifier definitions */ +#define RO_DBGID_DEFINITION_START +#define RO_REFRESH_ROAM_TABLE 1 +#define RO_UPDATE_ROAM_CANDIDATE 2 +#define RO_UPDATE_ROAM_CANDIDATE_CB 3 +#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4 +#define RO_REFRESH_ROAM_TABLE_DONE 5 +#define RO_PERIODIC_SEARCH_CB 6 +#define RO_PERIODIC_SEARCH_TIMEOUT 7 +#define RO_INIT 8 +#define RO_BMISS_STATE1 9 +#define RO_BMISS_STATE2 10 +#define RO_SET_PERIODIC_SEARCH_ENABLE 11 +#define RO_SET_PERIODIC_SEARCH_DISABLE 12 +#define RO_ENABLE_SQ_THRESHOLD 13 +#define RO_DISABLE_SQ_THRESHOLD 14 +#define RO_ADD_BSS_TO_ROAM_TABLE 15 +#define RO_SET_PERIODIC_SEARCH_MODE 16 +#define RO_CONFIGURE_SQ_THRESHOLD1 17 +#define RO_CONFIGURE_SQ_THRESHOLD2 18 +#define RO_CONFIGURE_SQ_PARAMS 19 +#define RO_LOW_SIGNAL_QUALITY_EVENT 20 +#define RO_HIGH_SIGNAL_QUALITY_EVENT 21 +#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22 +#define RO_UPDATE_CONNECTION_STATE_METRIC 23 +#define RO_DBGID_DEFINITION_END + +/* CM debug identifier definitions */ +#define CM_DBGID_DEFINITION_START +#define CM_INITIATE_HANDOFF 1 +#define CM_INITIATE_HANDOFF_CB 2 +#define CM_CONNECT_EVENT 3 +#define CM_DISCONNECT_EVENT 4 +#define CM_INIT 5 +#define CM_HANDOFF_SOURCE 6 +#define CM_SET_HANDOFF_TRIGGERS 7 +#define CM_CONNECT_REQUEST 8 +#define CM_CONNECT_REQUEST_CB 9 +#define CM_CONTINUE_SCAN_CB 10 +#define CM_DBGID_DEFINITION_END + + +/* mgmt debug identifier definitions */ +#define MGMT_DBGID_DEFINITION_START +#define KEYMGMT_CONNECTION_INIT 1 +#define KEYMGMT_CONNECTION_COMPLETE 2 +#define KEYMGMT_CONNECTION_CLOSE 3 +#define KEYMGMT_ADD_KEY 4 +#define MLME_NEW_STATE 5 +#define MLME_CONN_INIT 6 +#define MLME_CONN_COMPLETE 7 +#define MLME_CONN_CLOSE 8 +#define MGMT_DBGID_DEFINITION_END + +/* TMR debug identifier definitions */ +#define TMR_DBGID_DEFINITION_START +#define TMR_HANG_DETECTED 1 +#define TMR_WDT_TRIGGERED 2 +#define TMR_WDT_RESET 3 +#define TMR_HANDLER_ENTRY 4 +#define TMR_HANDLER_EXIT 5 +#define TMR_SAVED_START 6 +#define TMR_SAVED_END 7 +#define TMR_DBGID_DEFINITION_END + +/* BTCOEX debug identifier definitions */ +#define BTCOEX_DBGID_DEFINITION_START +#define BTCOEX_STATUS_CMD 1 +#define BTCOEX_PARAMS_CMD 2 +#define BTCOEX_ANT_CONFIG 3 +#define BTCOEX_COLOCATED_BT_DEVICE 4 +#define BTCOEX_CLOSE_RANGE_SCO_ON 5 +#define BTCOEX_CLOSE_RANGE_SCO_OFF 6 +#define BTCOEX_CLOSE_RANGE_A2DP_ON 7 +#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8 +#define BTCOEX_A2DP_PROTECT_ON 9 +#define BTCOEX_A2DP_PROTECT_OFF 10 +#define BTCOEX_SCO_PROTECT_ON 11 +#define BTCOEX_SCO_PROTECT_OFF 12 +#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13 +#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14 +#define BTCOEX_CLOSE_RANGE_TOGGLE 15 +#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16 +#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17 +#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18 +#define BTCOEX_PTA_PRI_INTR_HANDLER 19 +#define BTCOEX_PSPOLL_QUEUED 20 +#define BTCOEX_PSPOLL_COMPLETE 21 +#define BTCOEX_DBG_PM_AWAKE 22 +#define BTCOEX_DBG_PM_SLEEP 23 +#define BTCOEX_DBG_SCO_COEX_ON 24 +#define BTCOEX_SCO_DATARECEIVE 25 +#define BTCOEX_INTR_INIT 26 +#define BTCOEX_PTA_PRI_DIFF 27 +#define BTCOEX_TIM_NOTIFICATION 28 +#define BTCOEX_SCO_WAKEUP_ON_DATA 29 +#define BTCOEX_SCO_SLEEP 30 +#define BTCOEX_SET_WEIGHTS 31 +#define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL 32 +#define BTCOEX_SCO_MEASURE_TIME_DIFF 33 +#define BTCOEX_SET_EOL_VAL 34 +#define BTCOEX_OPT_DETECT_HANDLER 35 +#define BTCOEX_SCO_TOGGLE_STATE 36 +#define BTCOEX_SCO_STOMP 37 +#define BTCOEX_NULL_COMP_CALLBACK 38 +#define BTCOEX_RX_INCOMING 39 +#define BTCOEX_RX_INCOMING_CTL 40 +#define BTCOEX_RX_INCOMING_MGMT 41 +#define BTCOEX_RX_INCOMING_DATA 42 +#define BTCOEX_RTS_RECEPTION 43 +#define BTCOEX_FRAME_PRI_LOW_RATE_THRES 44 +#define BTCOEX_PM_FAKE_SLEEP 45 +#define BTCOEX_ACL_COEX_STATUS 46 +#define BTCOEX_ACL_COEX_DETECTION 47 +#define BTCOEX_A2DP_COEX_STATUS 48 +#define BTCOEX_SCO_STATUS 49 +#define BTCOEX_WAKEUP_ON_DATA 50 +#define BTCOEX_DATARECEIVE 51 +#define BTCOEX_GET_MAX_AGGR_SIZE 53 +#define BTCOEX_MAX_AGGR_AVAIL_TIME 54 +#define BTCOEX_DBG_WBTIMER_INTR 55 +#define BTCOEX_DBG_SCO_SYNC 57 +#define BTCOEX_UPLINK_QUEUED_RATE 59 +#define BTCOEX_DBG_UPLINK_ENABLE_EOL 60 +#define BTCOEX_UPLINK_FRAME_DURATION 61 +#define BTCOEX_UPLINK_SET_EOL 62 +#define BTCOEX_DBG_EOL_EXPIRED 63 +#define BTCOEX_DBG_DATA_COMPLETE 64 +#define BTCOEX_UPLINK_QUEUED_TIMESTAMP 65 +#define BTCOEX_DBG_DATA_COMPLETE_TIME 66 +#define BTCOEX_DBG_A2DP_ROLE_IS_SLAVE 67 +#define BTCOEX_DBG_A2DP_ROLE_IS_MASTER 68 +#define BTCOEX_DBG_UPLINK_SEQ_NUM 69 +#define BTCOEX_UPLINK_AGGR_SEQ 70 +#define BTCOEX_DBG_TX_COMP_SEQ_NO 71 +#define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE 72 +#define BTCOEX_DBG_ACL_TRAFFIC 73 +#define BTCOEX_CURR_AGGR_PROP 74 +#define BTCOEX_DBG_SCO_GET_PER_TIME_DIFF 75 +#define BTCOEX_PSPOLL_PROCESS 76 +#define BTCOEX_RETURN_FROM_MAC 77 +#define BTCOEX_FREED_REQUEUED_CNT 78 +#define BTCOEX_DBG_TOGGLE_LOW_RATES 79 +#define BTCOEX_MAC_GOES_TO_SLEEP 80 +#define BTCOEX_DBG_A2DP_NO_SYNC 81 +#define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO 82 +#define BTCOEX_RETURN_FROM_MAC_AC 83 +#define BTCOEX_DBG_DTIM_RECV 84 +#define BTCOEX_IS_PRE_UPDATE 86 +#define BTCOEX_ENQUEUED_BIT_MAP 87 +#define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS 88 +#define BTCOEX_UPLINK_DESC 89 +#define BTCOEX_SCO_GET_PER_FIRST_FRM_TIMESTAMP 90 +#define BTCOEX_DBG_RECV_ACK 94 +#define BTCOEX_DBG_ADDBA_INDICATION 95 +#define BTCOEX_TX_COMPLETE_EOL_FAILED 96 +#define BTCOEX_DBG_A2DP_USAGE_COMPLETE 97 +#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER 98 +#define BTCOEX_DBG_A2DP_SYNC_INTR 99 +#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION 100 +#define BTCOEX_FORM_AGGR_CURR_AGGR 101 +#define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT 102 +#define BTCOEX_DBG_BT_TRAFFIC 103 +#define BTCOEX_DBG_STOMP_BT_TRAFFIC 104 +#define BTCOEX_RECV_NULL 105 +#define BTCOEX_DBG_A2DP_MASTER_BT_END 106 +#define BTCOEX_DBG_A2DP_BT_START 107 +#define BTCOEX_DBG_A2DP_SLAVE_BT_END 108 +#define BTCOEX_DBG_A2DP_STOMP_BT 109 +#define BTCOEX_DBG_GO_TO_SLEEP 110 +#define BTCOEX_DBG_A2DP_PKT 111 +#define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV 112 +#define BTCOEX_DBG_A2DP_NULL 113 +#define BTCOEX_DBG_UPLINK_DATA 114 +#define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL 115 +#define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT 116 +#define BTCOEX_DBG_TXQ_STATE 117 +#define BTCOEX_DBG_ALLOW_SCAN 118 +#define BTCOEX_DBG_SCAN_REQUEST 119 +#define BTCOEX_A2DP_SLEEP 127 +#define BTCOEX_DBG_DATA_ACTIV_TIMEOUT 128 +#define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE 129 +#define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 130 +#define BTCOEX_DATARECEIVE_AGGR 131 +#define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING 132 +#define BTCOEX_DBG_DATARESP_TIMEOUT 133 +#define BTCOEX_BDG_BMISS 134 +#define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM 135 +#define BTCOEX_DBG_SECOND_BMISS 136 +#define BTCOEX_DBG_SET_WLAN_STATE 138 +#define BTCOEX_BDG_FIRST_BMISS 139 +#define BTCOEX_DBG_A2DP_CHAN_OP 140 +#define BTCOEX_DBG_A2DP_INTR 141 +#define BTCOEX_DBG_BT_INQUIRY 142 +#define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH 143 +#define BTCOEX_DBG_POST_INQUIRY_FINISH 144 +#define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER 145 +#define BTCOEX_DBG_NULL_FRAME_SLEEP 146 +#define BTCOEX_DBG_NULL_FRAME_AWAKE 147 +#define BTCOEX_DBG_SET_AGGR_SIZE 152 +#define BTCOEX_DBG_TEAR_BA_TIMEOUT 153 +#define BTCOEX_DBG_MGMT_FRAME_SEQ_NO 154 +#define BTCOEX_DBG_SCO_STOMP_HIGH_PRI 155 +#define BTCOEX_DBG_COLOCATED_BT_DEV 156 +#define BTCOEX_DBG_FE_ANT_TYPE 157 +#define BTCOEX_DBG_BT_INQUIRY_CMD 158 +#define BTCOEX_DBG_SCO_CONFIG 159 +#define BTCOEX_DBG_SCO_PSPOLL_CONFIG 160 +#define BTCOEX_DBG_SCO_OPTMODE_CONFIG 161 +#define BTCOEX_DBG_A2DP_CONFIG 162 +#define BTCOEX_DBG_A2DP_PSPOLL_CONFIG 163 +#define BTCOEX_DBG_A2DP_OPTMODE_CONFIG 164 +#define BTCOEX_DBG_ACLCOEX_CONFIG 165 +#define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG 166 +#define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG 167 +#define BTCOEX_DBG_DEBUG_CMD 168 +#define BTCOEX_DBG_SET_BT_OPERATING_STATUS 169 +#define BTCOEX_DBG_GET_CONFIG 170 +#define BTCOEX_DBG_GET_STATS 171 +#define BTCOEX_DBG_BT_OPERATING_STATUS 172 +#define BTCOEX_DBG_PERFORM_RECONNECT 173 +#define BTCOEX_DBG_ACL_WLAN_MED 175 +#define BTCOEX_DBG_ACL_BT_MED 176 +#define BTCOEX_DBG_WLAN_CONNECT 177 +#define BTCOEX_DBG_A2DP_DUAL_START 178 +#define BTCOEX_DBG_PMAWAKE_NOTIFY 179 +#define BTCOEX_DBG_BEACON_SCAN_ENABLE 180 +#define BTCOEX_DBG_BEACON_SCAN_DISABLE 181 +#define BTCOEX_DBG_RX_NOTIFY 182 +#define BTCOEX_SCO_GET_PER_SECOND_FRM_TIMESTAMP 183 +#define BTCOEX_DBG_TXQ_DETAILS 184 +#define BTCOEX_DBG_SCO_STOMP_LOW_PRI 185 +#define BTCOEX_DBG_A2DP_FORCE_SCAN 186 +#define BTCOEX_DBG_DTIM_STOMP_COMP 187 +#define BTCOEX_ACL_PRESENCE_TIMER 188 +#define BTCOEX_DBGID_DEFINITION_END + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_ID_H_ */ diff --git a/drivers/staging/ath6kl/include/common/discovery.h b/drivers/staging/ath6kl/include/common/discovery.h new file mode 100644 index 000000000000..da1b33245069 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/discovery.h @@ -0,0 +1,75 @@ +//------------------------------------------------------------------------------ +// <copyright file="discovery.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DISCOVERY_H_ +#define _DISCOVERY_H_ + +/* + * DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel + */ +typedef enum { + DEFAULT_SCPRI = 0x01, + POPULAR_SCPRI = 0x02, + SSIDS_SCPRI = 0x04, + PROF_SCPRI = 0x08, +} DC_SCAN_PRIORITY; + +/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */ +typedef enum { + SCAN_RESET = 0, + SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \ + SSIDS_SCPRI | PROF_SCPRI), + + SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI), + SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI), + SCAN_PROF_MASK = (PROF_SCPRI), + SCAN_MULTI_CHANNEL = 0x000100, + SCAN_DETERMINISTIC = 0x000200, + SCAN_PROFILE_MATCH_TERMINATED = 0x000400, + SCAN_HOME_CHANNEL_SKIP = 0x000800, + SCAN_CHANNEL_LIST_CONTINUE = 0x001000, + SCAN_CURRENT_SSID_SKIP = 0x002000, + SCAN_ACTIVE_PROBE_DISABLE = 0x004000, + SCAN_CHANNEL_HINT_ONLY = 0x008000, + SCAN_ACTIVE_CHANNELS_ONLY = 0x010000, + SCAN_UNUSED1 = 0x020000, /* unused */ + SCAN_PERIODIC = 0x040000, + SCAN_FIXED_DURATION = 0x080000, + SCAN_AP_ASSISTED = 0x100000, +} DC_SCAN_TYPE; + +typedef enum { + BSS_REPORTING_DEFAULT = 0x0, + EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */ +} DC_BSS_REPORTING_POLICY; + +typedef enum { + DC_IGNORE_WPAx_GROUP_CIPHER = 0x01, + DC_PROFILE_MATCH_DONE = 0x02, + DC_IGNORE_AAC_BEACON = 0x04, + DC_CSA_FOLLOW_BSS = 0x08, +} DC_PROFILE_FILTER; + +#define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS) + +#endif /* _DISCOVERY_H_ */ diff --git a/drivers/staging/ath6kl/include/common/dset_internal.h b/drivers/staging/ath6kl/include/common/dset_internal.h new file mode 100644 index 000000000000..2460f0ecf12b --- /dev/null +++ b/drivers/staging/ath6kl/include/common/dset_internal.h @@ -0,0 +1,63 @@ +//------------------------------------------------------------------------------ +// <copyright file="dset_internal.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSET_INTERNAL_H__ +#define __DSET_INTERNAL_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +/* + * Internal dset definitions, common for DataSet layer. + */ + +#define DSET_TYPE_STANDARD 0 +#define DSET_TYPE_BPATCHED 1 +#define DSET_TYPE_COMPRESSED 2 + +/* Dataset descriptor */ + +typedef PREPACK struct dset_descriptor_s { + struct dset_descriptor_s *next; /* List link. NULL only at the last + descriptor */ + A_UINT16 id; /* Dset ID */ + A_UINT16 size; /* Dset size. */ + void *DataPtr; /* Pointer to raw data for standard + DataSet or pointer to original + dset_descriptor for patched + DataSet */ + A_UINT32 data_type; /* DSET_TYPE_*, above */ + + void *AuxPtr; /* Additional data that might + needed for data_type. For + example, pointer to patch + Dataset descriptor for BPatch. */ +} POSTPACK dset_descriptor_t; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* __DSET_INTERNAL_H__ */ diff --git a/drivers/staging/ath6kl/include/common/dsetid.h b/drivers/staging/ath6kl/include/common/dsetid.h new file mode 100644 index 000000000000..d08fdeb39ec3 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/dsetid.h @@ -0,0 +1,134 @@ +//------------------------------------------------------------------------------ +// <copyright file="dsetid.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSETID_H__ +#define __DSETID_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +/* Well-known DataSet IDs */ +#define DSETID_UNUSED 0x00000000 +#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */ +#define DSETID_REGDB 0x00000002 /* Regulatory Database */ +#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */ +#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */ + +#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005 +#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025 +/* + * Get DSETID for various reference clock speeds. + * For each speed there are three DataSets that correspond + * to the three columns of bank6 data (addr, 11a, 11b/g). + * This macro returns the dsetid of the first of those + * three DataSets. + */ +#define ANALOG_CONTROL_DATA_DSETID(refclk) \ + (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk) + +/* + * There are TWO STARTUP_PATCH DataSets. + * DSETID_STARTUP_PATCH is historical, and was applied before BMI on + * earlier systems. On AR6002, it is applied after BMI, just like + * DSETID_STARTUP_PATCH2. + */ +#define DSETID_STARTUP_PATCH 0x00000026 +#define DSETID_GPIO_CONFIG_PATCH 0x00000027 +#define DSETID_WLANREGS 0x00000028 /* override wlan regs */ +#define DSETID_STARTUP_PATCH2 0x00000029 + +#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */ + +/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */ +#define DSETID_INI_DATA 0x00000100 +/* Reserved for WHAL INI Tables: 0x100..0x11f */ +#define DSETID_INI_DATA_END 0x0000011f + +#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */ + +#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the + end of a memory-based + DataSet Index */ +#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */ + +/* + * PATCH DataSet format: + * A list of patches, terminated by a patch with + * address=PATCH_END. + * + * This allows for patches to be stored in flash. + */ +PREPACK struct patch_s { + A_UINT32 *address; + A_UINT32 data; +} POSTPACK ; + +/* + * Skip some patches. Can be used to erase a single patch in a + * patch DataSet without having to re-write the DataSet. May + * also be used to embed information for use by subsequent + * patch code. The "data" in a PATCH_SKIP tells how many + * bytes of length "patch_s" to skip. + */ +#define PATCH_SKIP ((A_UINT32 *)0x00000000) + +/* + * Execute code at the address specified by "data". + * The address of the patch structure is passed as + * the one parameter. + */ +#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001) + +/* + * Same as PATCH_CODE_ABS, but treat "data" as an + * offset from the start of the patch word. + */ +#define PATCH_CODE_REL ((A_UINT32 *)0x00000002) + +/* Mark the end of this patch DataSet. */ +#define PATCH_END ((A_UINT32 *)0xffffffff) + +/* + * A DataSet which contains a Binary Patch to some other DataSet + * uses the original dsetid with the DSETID_BPATCH_FLAG bit set. + * Such a BPatch DataSet consists of BPatch metadata followed by + * the bdiff bytes. BPatch metadata consists of a single 32-bit + * word that contains the size of the BPatched final image. + * + * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff + * to create "diffs": + * bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs + * Then add BPatch metadata to the start of "diffs". + * + * NB: There are some implementation-induced restrictions + * on which DataSets can be BPatched. + */ +#define DSETID_BPATCH_FLAG 0x80000000 + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* __DSETID_H__ */ diff --git a/drivers/staging/ath6kl/include/common/epping_test.h b/drivers/staging/ath6kl/include/common/epping_test.h new file mode 100644 index 000000000000..f8aeb3f657ea --- /dev/null +++ b/drivers/staging/ath6kl/include/common/epping_test.h @@ -0,0 +1,120 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +// + +/* This file contains shared definitions for the host/target endpoint ping test */ + +#ifndef EPPING_TEST_H_ +#define EPPING_TEST_H_ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + + /* alignment to 4-bytes */ +#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR)) + +#ifndef A_OFFSETOF +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field)) +#endif + +#define EPPING_RSVD_FILL 0xCC + +#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7 + +typedef PREPACK struct { + A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */ + A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */ + A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target) + When echoed: StreamEchoSent_t == StreamEcho_h */ + A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */ + A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */ + A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host*/ + A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value + since this packet maps to a 14-byte ethernet frame we want + to make sure ethertype field is set to something unknown */ + + A_UINT8 _pad[2]; /* padding for alignment */ + A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */ + A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */ + A_UINT32 SeqNo; /* sequence number (set by host or target) */ + A_UINT16 Cmd_h; /* ping command (filled by host) */ + A_UINT16 CmdFlags_h; /* optional flags */ + A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */ + A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */ + A_UINT16 DataLength; /* length of data */ + A_UINT16 DataCRC; /* 16 bit CRC of data */ + A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */ +} POSTPACK EPPING_HEADER; + +#define EPPING_PING_MAGIC_0 0xAA +#define EPPING_PING_MAGIC_1 0x55 +#define EPPING_PING_MAGIC_2 0xCE +#define EPPING_PING_MAGIC_3 0xEC + + + +#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \ + ((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \ + ((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \ + ((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3)) + +#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \ + (pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \ + (pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \ + (pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;} + +#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */ +#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */ +#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */ + +#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP) + +#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */ +#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */ +#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */ +#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */ +#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */ +#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */ + + /* test command parameters may be no more than 8 bytes */ +typedef PREPACK struct { + A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */ + A_UINT16 PacketLength; /* length of packet to generate including header */ + A_UINT16 Flags; /* flags */ + +#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */ +#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */ +#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */ +} POSTPACK EPPING_CONT_RX_PARAMS; + +#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h) +#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16))) + +#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we + can use this to distinguish packets */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + + +#endif /*EPPING_TEST_H_*/ diff --git a/drivers/staging/ath6kl/include/common/gmboxif.h b/drivers/staging/ath6kl/include/common/gmboxif.h new file mode 100644 index 000000000000..4d8d85fd2e7c --- /dev/null +++ b/drivers/staging/ath6kl/include/common/gmboxif.h @@ -0,0 +1,78 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __GMBOXIF_H__ +#define __GMBOXIF_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +/* GMBOX interface definitions */ + +#define AR6K_GMBOX_CREDIT_COUNTER 1 /* we use credit counter 1 to track credits */ +#define AR6K_GMBOX_CREDIT_SIZE_COUNTER 2 /* credit counter 2 is used to pass the size of each credit */ + + + /* HCI UART transport definitions when used over GMBOX interface */ +#define HCI_UART_COMMAND_PKT 0x01 +#define HCI_UART_ACL_PKT 0x02 +#define HCI_UART_SCO_PKT 0x03 +#define HCI_UART_EVENT_PKT 0x04 + + /* definitions for BT HCI packets */ +typedef PREPACK struct { + A_UINT16 Flags_ConnHandle; + A_UINT16 Length; +} POSTPACK BT_HCI_ACL_HEADER; + +typedef PREPACK struct { + A_UINT16 Flags_ConnHandle; + A_UINT8 Length; +} POSTPACK BT_HCI_SCO_HEADER; + +typedef PREPACK struct { + A_UINT16 OpCode; + A_UINT8 ParamLength; +} POSTPACK BT_HCI_COMMAND_HEADER; + +typedef PREPACK struct { + A_UINT8 EventCode; + A_UINT8 ParamLength; +} POSTPACK BT_HCI_EVENT_HEADER; + +/* MBOX host interrupt signal assignments */ + +#define MBOX_SIG_HCI_BRIDGE_MAX 8 +#define MBOX_SIG_HCI_BRIDGE_BT_ON 0 +#define MBOX_SIG_HCI_BRIDGE_BT_OFF 1 +#define MBOX_SIG_HCI_BRIDGE_BAUD_SET 2 +#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_ON 3 +#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_OFF 4 + + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* __GMBOXIF_H__ */ + diff --git a/drivers/staging/ath6kl/include/common/gpio.h b/drivers/staging/ath6kl/include/common/gpio.h new file mode 100644 index 000000000000..f7230667dd66 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/gpio.h @@ -0,0 +1,45 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// +// Author(s): ="Atheros" +//------------------------------------------------------------------------------ + +#define AR6001_GPIO_PIN_COUNT 18 +#define AR6002_GPIO_PIN_COUNT 18 +#define AR6003_GPIO_PIN_COUNT 28 + +/* + * Possible values for WMIX_GPIO_SET_REGISTER_CMDID. + * NB: These match hardware order, so that addresses can + * easily be computed. + */ +#define GPIO_ID_OUT 0x00000000 +#define GPIO_ID_OUT_W1TS 0x00000001 +#define GPIO_ID_OUT_W1TC 0x00000002 +#define GPIO_ID_ENABLE 0x00000003 +#define GPIO_ID_ENABLE_W1TS 0x00000004 +#define GPIO_ID_ENABLE_W1TC 0x00000005 +#define GPIO_ID_IN 0x00000006 +#define GPIO_ID_STATUS 0x00000007 +#define GPIO_ID_STATUS_W1TS 0x00000008 +#define GPIO_ID_STATUS_W1TC 0x00000009 +#define GPIO_ID_PIN0 0x0000000a +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) + +#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17) +#define GPIO_ID_NONE 0xffffffff diff --git a/drivers/staging/ath6kl/include/common/htc.h b/drivers/staging/ath6kl/include/common/htc.h new file mode 100644 index 000000000000..f96cf7db7e06 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/htc.h @@ -0,0 +1,236 @@ +//------------------------------------------------------------------------------ +// <copyright file="htc.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_H__ +#define __HTC_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field)) + +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ + (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)])) + +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a + * structure using only the type and field name. + * Use these macros if there is the potential for unaligned buffer accesses. */ +#define A_GET_UINT16_FIELD(p,type,field) \ + ASSEMBLE_UNALIGNED_UINT16(p,\ + A_OFFSETOF(type,field) + 1, \ + A_OFFSETOF(type,field)) + +#define A_SET_UINT16_FIELD(p,type,field,value) \ +{ \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \ +} + +#define A_GET_UINT8_FIELD(p,type,field) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] + +#define A_SET_UINT8_FIELD(p,type,field,value) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value) + +/****** DANGER DANGER *************** + * + * The frame header length and message formats defined herein were + * selected to accommodate optimal alignment for target processing. This reduces code + * size and improves performance. + * + * Any changes to the header length may alter the alignment and cause exceptions + * on the target. When adding to the message structures insure that fields are + * properly aligned. + * + */ + +/* HTC frame header */ +typedef PREPACK struct _HTC_FRAME_HDR{ + /* do not remove or re-arrange these fields, these are minimally required + * to take advantage of 4-byte lookaheads in some hardware implementations */ + A_UINT8 EndpointID; + A_UINT8 Flags; + A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */ + + /***** end of 4-byte lookahead ****/ + + A_UINT8 ControlBytes[2]; + + /* message payload starts after the header */ + +} POSTPACK HTC_FRAME_HDR; + +/* frame header flags */ + + /* send direction */ +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) +#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */ + /* receive direction */ +#define HTC_FLAGS_RECV_UNUSED_0 (1 << 0) /* bit 0 unused */ +#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */ +#define HTC_FLAGS_RECV_UNUSED_2 (1 << 0) /* bit 2 unused */ +#define HTC_FLAGS_RECV_UNUSED_3 (1 << 0) /* bit 3 unused */ +#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0) /* bits 7..4 */ +#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4 + +#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) +#define HTC_MAX_TRAILER_LENGTH 255 +#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR)) + +/* HTC control message IDs */ + +#define HTC_MSG_READY_ID 1 +#define HTC_MSG_CONNECT_SERVICE_ID 2 +#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3 +#define HTC_MSG_SETUP_COMPLETE_ID 4 +#define HTC_MSG_SETUP_COMPLETE_EX_ID 5 + +#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 + +/* base message ID header */ +typedef PREPACK struct { + A_UINT16 MessageID; +} POSTPACK HTC_UNKNOWN_MSG; + +/* HTC ready message + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; /* ID */ + A_UINT16 CreditCount; /* number of credits the target can offer */ + A_UINT16 CreditSize; /* size of each credit */ + A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */ + A_UINT8 _Pad1; +} POSTPACK HTC_READY_MSG; + + /* extended HTC ready message */ +typedef PREPACK struct { + HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */ + /* extended information */ + A_UINT8 HTCVersion; + A_UINT8 MaxMsgsPerHTCBundle; +} POSTPACK HTC_READY_EX_MSG; + +#define HTC_VERSION_2P0 0x00 +#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */ + +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128 + +/* connect service + * direction : host-to-target */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID of the service to connect to */ + A_UINT16 ConnectionFlags; /* connection flags */ + +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when + the host needs credits */ +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 + + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_MSG; + +/* connect response + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID that the connection request was made */ + A_UINT8 Status; /* service connection status */ + A_UINT8 EndpointID; /* assigned endpoint ID */ + A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */ + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; + +typedef PREPACK struct { + A_UINT16 MessageID; + /* currently, no other fields */ +} POSTPACK HTC_SETUP_COMPLETE_MSG; + + /* extended setup completion message */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT32 SetupFlags; + A_UINT8 MaxMsgsPerBundledRecv; + A_UINT8 Rsvd[3]; +} POSTPACK HTC_SETUP_COMPLETE_EX_MSG; + +#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) + +/* connect response status codes */ +#define HTC_SERVICE_SUCCESS 0 /* success */ +#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ +#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ +#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ +#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more + endpoints */ + +/* report record IDs */ + +#define HTC_RECORD_NULL 0 +#define HTC_RECORD_CREDITS 1 +#define HTC_RECORD_LOOKAHEAD 2 +#define HTC_RECORD_LOOKAHEAD_BUNDLE 3 + +typedef PREPACK struct { + A_UINT8 RecordID; /* Record ID */ + A_UINT8 Length; /* Length of record */ +} POSTPACK HTC_RECORD_HDR; + +typedef PREPACK struct { + A_UINT8 EndpointID; /* Endpoint that owns these credits */ + A_UINT8 Credits; /* credits to report since last report */ +} POSTPACK HTC_CREDIT_REPORT; + +typedef PREPACK struct { + A_UINT8 PreValid; /* pre valid guard */ + A_UINT8 LookAhead[4]; /* 4 byte lookahead */ + A_UINT8 PostValid; /* post valid guard */ + + /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. + * The PreValid bytes must equal the inverse of the PostValid byte */ + +} POSTPACK HTC_LOOKAHEAD_REPORT; + +typedef PREPACK struct { + A_UINT8 LookAhead[4]; /* 4 byte lookahead */ +} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + + +#endif /* __HTC_H__ */ + diff --git a/drivers/staging/ath6kl/include/common/htc_services.h b/drivers/staging/ath6kl/include/common/htc_services.h new file mode 100644 index 000000000000..fb22268a8d84 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/htc_services.h @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// <copyright file="htc_services.h" company="Atheros"> +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_SERVICES_H__ +#define __HTC_SERVICES_H__ + +/* Current service IDs */ + +typedef enum { + RSVD_SERVICE_GROUP = 0, + WMI_SERVICE_GROUP = 1, + + HTC_TEST_GROUP = 254, + HTC_SERVICE_GROUP_LAST = 255 +}HTC_SERVICE_GROUP_IDS; + +#define MAKE_SERVICE_ID(group,index) \ + (int)(((int)group << 8) | (int)(index)) + +/* NOTE: service ID of 0x0000 is reserved and should never be used */ +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) +#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) +#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) +#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) +#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) +#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) +#define WMI_MAX_SERVICES 5 + +/* raw stream service (i.e. flash, tcmd, calibration apps) */ +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) + +#endif /*HTC_SERVICES_H_*/ diff --git a/drivers/staging/ath6kl/include/common/ini_dset.h b/drivers/staging/ath6kl/include/common/ini_dset.h new file mode 100644 index 000000000000..8cf1af834bd0 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/ini_dset.h @@ -0,0 +1,82 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// +// Author(s): ="Atheros" +//------------------------------------------------------------------------------ + +#ifndef _INI_DSET_H_ +#define _INI_DSET_H_ + +/* + * Each of these represents a WHAL INI table, which consists + * of an "address column" followed by 1 or more "value columns". + * + * Software uses the base WHAL_INI_DATA_ID+column to access a + * DataSet that holds a particular column of data. + */ +typedef enum { +#if defined(AR6002_REV4) || defined(AR6003) +/* Add these definitions for compatability */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */ + WHAL_INI_DATA_ID_COMMON =6, /* 7 */ + WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */ +#ifdef FPGA + WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */ + WHAL_INI_DATA_ID_ADDAC =25, /* 26 */ +#else + WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21,22,23 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */ +#endif /* FPGA */ +#else + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */ + WHAL_INI_DATA_ID_COMMON =4, /* 5 */ + WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */ + WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */ +#endif + WHAL_INI_DATA_ID_MAX =31 +} WHAL_INI_DATA_ID; + +typedef PREPACK struct { + A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common + A_UINT16 offset; + A_UINT32 newValue; +} POSTPACK INI_DSET_REG_OVERRIDE; + +#endif diff --git a/drivers/staging/ath6kl/include/common/pkt_log.h b/drivers/staging/ath6kl/include/common/pkt_log.h new file mode 100644 index 000000000000..331cc04edada --- /dev/null +++ b/drivers/staging/ath6kl/include/common/pkt_log.h @@ -0,0 +1,45 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __PKT_LOG_H__ +#define __PKT_LOG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Pkt log info */ +typedef PREPACK struct pkt_log_t { + struct info_t { + A_UINT16 st; + A_UINT16 end; + A_UINT16 cur; + }info[4096]; + A_UINT16 last_idx; +}POSTPACK PACKET_LOG; + + +#ifdef __cplusplus +} +#endif +#endif /* __PKT_LOG_H__ */ diff --git a/drivers/staging/ath6kl/include/common/regDb.h b/drivers/staging/ath6kl/include/common/regDb.h new file mode 100644 index 000000000000..f8245f104528 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/regDb.h @@ -0,0 +1,29 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REG_DB_H__ +#define __REG_DB_H__ + +#include "./regulatory/reg_dbschema.h" +#include "./regulatory/reg_dbvalues.h" + +#endif /* __REG_DB_H__ */ diff --git a/drivers/staging/ath6kl/include/common/regdump.h b/drivers/staging/ath6kl/include/common/regdump.h new file mode 100644 index 000000000000..ff79b4846e69 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/regdump.h @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// <copyright file="regdump.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REGDUMP_H__ +#define __REGDUMP_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#if defined(AR6001) +#include "AR6001/AR6001_regdump.h" +#endif +#if defined(AR6002) +#include "AR6002/AR6002_regdump.h" +#endif + +#if !defined(__ASSEMBLER__) +/* + * Target CPU state at the time of failure is reflected + * in a register dump, which the Host can fetch through + * the diagnostic window. + */ +PREPACK struct register_dump_s { + A_UINT32 target_id; /* Target ID */ + A_UINT32 assline; /* Line number (if assertion failure) */ + A_UINT32 pc; /* Program Counter at time of exception */ + A_UINT32 badvaddr; /* Virtual address causing exception */ + CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ + + /* Could copy top of stack here, too.... */ +} POSTPACK; +#endif /* __ASSEMBLER__ */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* __REGDUMP_H__ */ diff --git a/drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h b/drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h new file mode 100644 index 000000000000..c6844d69fe47 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h @@ -0,0 +1,237 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REG_DBSCHEMA_H__ +#define __REG_DBSCHEMA_H__ + +/* + * This file describes the regulatory DB schema, which is common between the + * 'generator' and 'parser'. The 'generator' runs on a host(typically a x86 + * Linux) and spits outs two binary files, which follow the DB file + * format(described below). The resultant output "regulatoryData_AG.bin" + * is binary file which has information regarding A and G regulatory + * information, while the "regulatoryData_G.bin" consists of G-ONLY regulatory + * information. This binary file is parsed in the target for extracting + * regulatory information. + * + * The DB values used to populate the regulatory DB are defined in + * reg_dbvalues.h + * + */ + +/* Binary data file - Representation of Regulatory DB*/ +#define REG_DATA_FILE_AG "./regulatoryData_AG.bin" +#define REG_DATA_FILE_G "./regulatoryData_G.bin" + + +/* Table tags used to encode different tables in the database */ +enum data_tags_t{ + REG_DMN_PAIR_MAPPING_TAG = 0, + REG_COUNTRY_CODE_TO_ENUM_RD_TAG, + REG_DMN_FREQ_BAND_regDmn5GhzFreq_TAG, + REG_DMN_FREQ_BAND_regDmn2Ghz11_BG_Freq_TAG, + REG_DOMAIN_TAG, + MAX_DB_TABLE_TAGS + }; + + + +/* + **************************************************************************** + * Regulatory DB file format : + * 4-bytes : "RGDB" (Magic Key) + * 4-bytes : version (Default is 5379(my extn)) + * 4-bytes : length of file + * dbType(4) + * TAG(4) + * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... + * TAG(4) + * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... + * TAG(4) + * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... + * ... + * ... + **************************************************************************** + * + */ + +/* + * Length of the file would be filled in when the file is created and + * it would include the header size. + */ + +#define REG_DB_KEY "RGDB" /* Should be EXACTLY 4-bytes */ +#define REG_DB_VER 7802 /* Between 0-9999 */ +/* REG_DB_VER history in reverse chronological order: + * 7802: 78 (ASCII code of N) + 02 (minor version number) - updated 10/21/09 + * 7801: 78 (ASCII code of N) + 01 (minor version number, increment on further changes) + * 1178: '11N' = 11 + ASCII code of N(78) + * 5379: initial version, no 11N support + */ +#define MAGIC_KEY_OFFSET 0 +#define VERSION_OFFSET 4 +#define FILE_SZ_OFFSET 8 +#define DB_TYPE_OFFSET 12 + +#define MAGIC_KEY_SZ 4 +#define VERSION_SZ 4 +#define FILE_SZ_SZ 4 +#define DB_TYPE_SZ 4 +#define DB_TAG_SZ 4 + +#define REGDB_GET_MAGICKEY(x) ((char *)x + MAGIC_KEY_OFFSET) +#define REGDB_GET_VERSION(x) ((char *)x + VERSION_OFFSET) +#define REGDB_GET_FILESIZE(x) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) +#define REGDB_GET_DBTYPE(x) *((char *)x + DB_TYPE_OFFSET) + +#define REGDB_SET_FILESIZE(x, sz_) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) = (sz_) +#define REGDB_IS_EOF(cur, begin) ( REGDB_GET_FILESIZE(begin) > ((cur) - (begin)) ) + + +/* A Table can be search based on key as a parameter or accessed directly + * by giving its index in to the table. + */ +enum searchType { + KEY_BASED_TABLE_SEARCH = 1, + INDEX_BASED_TABLE_ACCESS + }; + + +/* Data is organised as different tables. There is a Master table, which + * holds information regarding all the tables. It does not have any + * knowledge about the attributes of the table it is holding + * but has external view of the same(for ex, how many entries, record size, + * how to search the table, total table size and reference to the data + * instance of table). + */ +typedef PREPACK struct dbMasterTable_t { /* Hold ptrs to Table data structures */ + A_UCHAR numOfEntries; + A_CHAR entrySize; /* Entry size per table row */ + A_CHAR searchType; /* Index based access or key based */ + A_CHAR reserved[3]; /* for alignment */ + A_UINT16 tableSize; /* Size of this table */ + A_CHAR *dataPtr; /* Ptr to the actual Table */ +} POSTPACK dbMasterTable; /* Master table - table of tables */ + + +/* used to get the number of rows in a table */ +#define REGDB_NUM_OF_ROWS(a) (sizeof (a) / sizeof (a[0])) + +/* + * Used to set the RegDomain bitmask which chooses which frequency + * band specs are used. + */ + +#define BMLEN 2 /* Use 2 32-bit uint for channel bitmask */ +#define BMZERO {0,0} /* BMLEN zeros */ + +#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ + {((((_fa >= 0) && (_fa < 32)) ? (((A_UINT32) 1) << _fa) : 0) | \ + (((_fb >= 0) && (_fb < 32)) ? (((A_UINT32) 1) << _fb) : 0) | \ + (((_fc >= 0) && (_fc < 32)) ? (((A_UINT32) 1) << _fc) : 0) | \ + (((_fd >= 0) && (_fd < 32)) ? (((A_UINT32) 1) << _fd) : 0) | \ + (((_fe >= 0) && (_fe < 32)) ? (((A_UINT32) 1) << _fe) : 0) | \ + (((_ff >= 0) && (_ff < 32)) ? (((A_UINT32) 1) << _ff) : 0) | \ + (((_fg >= 0) && (_fg < 32)) ? (((A_UINT32) 1) << _fg) : 0) | \ + (((_fh >= 0) && (_fh < 32)) ? (((A_UINT32) 1) << _fh) : 0)), \ + ((((_fa > 31) && (_fa < 64)) ? (((A_UINT32) 1) << (_fa - 32)) : 0) | \ + (((_fb > 31) && (_fb < 64)) ? (((A_UINT32) 1) << (_fb - 32)) : 0) | \ + (((_fc > 31) && (_fc < 64)) ? (((A_UINT32) 1) << (_fc - 32)) : 0) | \ + (((_fd > 31) && (_fd < 64)) ? (((A_UINT32) 1) << (_fd - 32)) : 0) | \ + (((_fe > 31) && (_fe < 64)) ? (((A_UINT32) 1) << (_fe - 32)) : 0) | \ + (((_ff > 31) && (_ff < 64)) ? (((A_UINT32) 1) << (_ff - 32)) : 0) | \ + (((_fg > 31) && (_fg < 64)) ? (((A_UINT32) 1) << (_fg - 32)) : 0) | \ + (((_fh > 31) && (_fh < 64)) ? (((A_UINT32) 1) << (_fh - 32)) : 0))} + + +/* + * THE following table is the mapping of regdomain pairs specified by + * a regdomain value to the individual unitary reg domains + */ + +typedef PREPACK struct reg_dmn_pair_mapping { + A_UINT16 regDmnEnum; /* 16 bit reg domain pair */ + A_UINT16 regDmn5GHz; /* 5GHz reg domain */ + A_UINT16 regDmn2GHz; /* 2GHz reg domain */ + A_UINT8 flags5GHz; /* Requirements flags (AdHoc disallow etc) */ + A_UINT8 flags2GHz; /* Requirements flags (AdHoc disallow etc) */ + A_UINT32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan + flags. This value is used as a mask on the unitary flags*/ +} POSTPACK REG_DMN_PAIR_MAPPING; + +#define OFDM_YES (1 << 0) +#define OFDM_NO (0 << 0) +#define MCS_HT20_YES (1 << 1) +#define MCS_HT20_NO (0 << 1) +#define MCS_HT40_A_YES (1 << 2) +#define MCS_HT40_A_NO (0 << 2) +#define MCS_HT40_G_YES (1 << 3) +#define MCS_HT40_G_NO (0 << 3) + +typedef PREPACK struct { + A_UINT16 countryCode; + A_UINT16 regDmnEnum; + A_CHAR isoName[3]; + A_CHAR allowMode; /* what mode is allowed - bit 0: OFDM; bit 1: MCS_HT20; bit 2: MCS_HT40_A; bit 3: MCS_HT40_G */ +} POSTPACK COUNTRY_CODE_TO_ENUM_RD; + +/* lower 16 bits of ht40ChanMask */ +#define NO_FREQ_HT40 0x0 /* no freq is HT40 capable */ +#define F1_TO_F4_HT40 0xF /* freq 1 to 4 in the block is ht40 capable */ +#define F2_TO_F3_HT40 0x6 /* freq 2 to 3 in the block is ht40 capable */ +#define F1_TO_F10_HT40 0x3FF /* freq 1 to 10 in the block is ht40 capable */ +#define F3_TO_F11_HT40 0x7FC /* freq 3 to 11 in the block is ht40 capable */ +#define F3_TO_F9_HT40 0x1FC /* freq 3 to 9 in the block is ht40 capable */ +#define F1_TO_F8_HT40 0xFF /* freq 1 to 8 in the block is ht40 capable */ +#define F1_TO_F4_F9_TO_F10_HT40 0x30F /* freq 1 to 4, 9 to 10 in the block is ht40 capable */ + +/* upper 16 bits of ht40ChanMask */ +#define FREQ_HALF_RATE 0x10000 +#define FREQ_QUARTER_RATE 0x20000 + +typedef PREPACK struct RegDmnFreqBand { + A_UINT16 lowChannel; /* Low channel center in MHz */ + A_UINT16 highChannel; /* High Channel center in MHz */ + A_UINT8 power; /* Max power (dBm) for channel range */ + A_UINT8 channelSep; /* Channel separation within the band */ + A_UINT8 useDfs; /* Use DFS in the RegDomain if corresponding bit is set */ + A_UINT8 mode; /* Mode of operation */ + A_UINT32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */ + A_UINT32 ht40ChanMask; /* lower 16 bits: indicate which frequencies in the block is HT40 capable + upper 16 bits: what rate (half/quarter) the channel is */ +} POSTPACK REG_DMN_FREQ_BAND; + + + +typedef PREPACK struct regDomain { + A_UINT16 regDmnEnum; /* value from EnumRd table */ + A_UINT8 rdCTL; + A_UINT8 maxAntGain; + A_UINT8 dfsMask; /* DFS bitmask for 5Ghz tables */ + A_UINT8 flags; /* Requirement flags (AdHoc disallow etc) */ + A_UINT16 reserved; /* for alignment */ + A_UINT32 pscan; /* Bitmask for passive scan */ + A_UINT32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */ + A_UINT32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */ +} POSTPACK REG_DOMAIN; + +#endif /* __REG_DBSCHEMA_H__ */ diff --git a/drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h b/drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h new file mode 100644 index 000000000000..278f90346b5a --- /dev/null +++ b/drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h @@ -0,0 +1,504 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __REG_DBVALUE_H__ +#define __REG_DBVALUE_H__ + +/* + * Numbering from ISO 3166 + */ +enum CountryCode { + CTRY_ALBANIA = 8, /* Albania */ + CTRY_ALGERIA = 12, /* Algeria */ + CTRY_ARGENTINA = 32, /* Argentina */ + CTRY_ARMENIA = 51, /* Armenia */ + CTRY_ARUBA = 533, /* Aruba */ + CTRY_AUSTRALIA = 36, /* Australia (for STA) */ + CTRY_AUSTRALIA_AP = 5000, /* Australia (for AP) */ + CTRY_AUSTRIA = 40, /* Austria */ + CTRY_AZERBAIJAN = 31, /* Azerbaijan */ + CTRY_BAHRAIN = 48, /* Bahrain */ + CTRY_BANGLADESH = 50, /* Bangladesh */ + CTRY_BARBADOS = 52, /* Barbados */ + CTRY_BELARUS = 112, /* Belarus */ + CTRY_BELGIUM = 56, /* Belgium */ + CTRY_BELIZE = 84, /* Belize */ + CTRY_BOLIVIA = 68, /* Bolivia */ + CTRY_BOSNIA_HERZEGOWANIA = 70, /* Bosnia & Herzegowania */ + CTRY_BRAZIL = 76, /* Brazil */ + CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ + CTRY_BULGARIA = 100, /* Bulgaria */ + CTRY_CAMBODIA = 116, /* Cambodia */ + CTRY_CANADA = 124, /* Canada (for STA) */ + CTRY_CANADA_AP = 5001, /* Canada (for AP) */ + CTRY_CHILE = 152, /* Chile */ + CTRY_CHINA = 156, /* People's Republic of China */ + CTRY_COLOMBIA = 170, /* Colombia */ + CTRY_COSTA_RICA = 188, /* Costa Rica */ + CTRY_CROATIA = 191, /* Croatia */ + CTRY_CYPRUS = 196, + CTRY_CZECH = 203, /* Czech Republic */ + CTRY_DENMARK = 208, /* Denmark */ + CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ + CTRY_ECUADOR = 218, /* Ecuador */ + CTRY_EGYPT = 818, /* Egypt */ + CTRY_EL_SALVADOR = 222, /* El Salvador */ + CTRY_ESTONIA = 233, /* Estonia */ + CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ + CTRY_FINLAND = 246, /* Finland */ + CTRY_FRANCE = 250, /* France */ + CTRY_FRANCE2 = 255, /* France2 */ + CTRY_GEORGIA = 268, /* Georgia */ + CTRY_GERMANY = 276, /* Germany */ + CTRY_GREECE = 300, /* Greece */ + CTRY_GREENLAND = 304, /* Greenland */ + CTRY_GRENADA = 308, /* Grenada */ + CTRY_GUAM = 316, /* Guam */ + CTRY_GUATEMALA = 320, /* Guatemala */ + CTRY_HAITI = 332, /* Haiti */ + CTRY_HONDURAS = 340, /* Honduras */ + CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ + CTRY_HUNGARY = 348, /* Hungary */ + CTRY_ICELAND = 352, /* Iceland */ + CTRY_INDIA = 356, /* India */ + CTRY_INDONESIA = 360, /* Indonesia */ + CTRY_IRAN = 364, /* Iran */ + CTRY_IRAQ = 368, /* Iraq */ + CTRY_IRELAND = 372, /* Ireland */ + CTRY_ISRAEL = 376, /* Israel */ + CTRY_ITALY = 380, /* Italy */ + CTRY_JAMAICA = 388, /* Jamaica */ + CTRY_JAPAN = 392, /* Japan */ + CTRY_JAPAN1 = 393, /* Japan (JP1) */ + CTRY_JAPAN2 = 394, /* Japan (JP0) */ + CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ + CTRY_JAPAN4 = 396, /* Japan (JE1) */ + CTRY_JAPAN5 = 397, /* Japan (JE2) */ + CTRY_JAPAN6 = 399, /* Japan (JP6) */ + CTRY_JORDAN = 400, /* Jordan */ + CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ + CTRY_KENYA = 404, /* Kenya */ + CTRY_KOREA_NORTH = 408, /* North Korea */ + CTRY_KOREA_ROC = 410, /* South Korea (for STA) */ + CTRY_KOREA_ROC2 = 411, /* South Korea */ + CTRY_KOREA_ROC3 = 412, /* South Korea (for AP) */ + CTRY_KUWAIT = 414, /* Kuwait */ + CTRY_LATVIA = 428, /* Latvia */ + CTRY_LEBANON = 422, /* Lebanon */ + CTRY_LIBYA = 434, /* Libya */ + CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ + CTRY_LITHUANIA = 440, /* Lithuania */ + CTRY_LUXEMBOURG = 442, /* Luxembourg */ + CTRY_MACAU = 446, /* Macau */ + CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */ + CTRY_MALAYSIA = 458, /* Malaysia */ + CTRY_MALTA = 470, /* Malta */ + CTRY_MEXICO = 484, /* Mexico */ + CTRY_MONACO = 492, /* Principality of Monaco */ + CTRY_MOROCCO = 504, /* Morocco */ + CTRY_NEPAL = 524, /* Nepal */ + CTRY_NETHERLANDS = 528, /* Netherlands */ + CTRY_NETHERLAND_ANTILLES = 530, /* Netherlands-Antilles */ + CTRY_NEW_ZEALAND = 554, /* New Zealand */ + CTRY_NICARAGUA = 558, /* Nicaragua */ + CTRY_NORWAY = 578, /* Norway */ + CTRY_OMAN = 512, /* Oman */ + CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ + CTRY_PANAMA = 591, /* Panama */ + CTRY_PARAGUAY = 600, /* Paraguay */ + CTRY_PERU = 604, /* Peru */ + CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ + CTRY_POLAND = 616, /* Poland */ + CTRY_PORTUGAL = 620, /* Portugal */ + CTRY_PUERTO_RICO = 630, /* Puerto Rico */ + CTRY_QATAR = 634, /* Qatar */ + CTRY_ROMANIA = 642, /* Romania */ + CTRY_RUSSIA = 643, /* Russia */ + CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ + CTRY_MONTENEGRO = 891, /* Montenegro */ + CTRY_SINGAPORE = 702, /* Singapore */ + CTRY_SLOVAKIA = 703, /* Slovak Republic */ + CTRY_SLOVENIA = 705, /* Slovenia */ + CTRY_SOUTH_AFRICA = 710, /* South Africa */ + CTRY_SPAIN = 724, /* Spain */ + CTRY_SRILANKA = 144, /* Sri Lanka */ + CTRY_SWEDEN = 752, /* Sweden */ + CTRY_SWITZERLAND = 756, /* Switzerland */ + CTRY_SYRIA = 760, /* Syria */ + CTRY_TAIWAN = 158, /* Taiwan */ + CTRY_THAILAND = 764, /* Thailand */ + CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ + CTRY_TUNISIA = 788, /* Tunisia */ + CTRY_TURKEY = 792, /* Turkey */ + CTRY_UAE = 784, /* U.A.E. */ + CTRY_UKRAINE = 804, /* Ukraine */ + CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ + CTRY_UNITED_STATES = 840, /* United States (for STA) */ + CTRY_UNITED_STATES_AP = 841, /* United States (for AP) */ + CTRY_UNITED_STATES_PS = 842, /* United States - public safety */ + CTRY_URUGUAY = 858, /* Uruguay */ + CTRY_UZBEKISTAN = 860, /* Uzbekistan */ + CTRY_VENEZUELA = 862, /* Venezuela */ + CTRY_VIET_NAM = 704, /* Viet Nam */ + CTRY_YEMEN = 887, /* Yemen */ + CTRY_ZIMBABWE = 716 /* Zimbabwe */ +}; + +#define CTRY_DEBUG 0 +#define CTRY_DEFAULT 0x1ff + +/* + * The following regulatory domain definitions are + * found in the EEPROM. Each regulatory domain + * can operate in either a 5GHz or 2.4GHz wireless mode or + * both 5GHz and 2.4GHz wireless modes. + * In general, the value holds no special + * meaning and is used to decode into either specific + * 2.4GHz or 5GHz wireless mode for that particular + * regulatory domain. + * + * Enumerated Regulatory Domain Information 8 bit values indicate that + * the regdomain is really a pair of unitary regdomains. 12 bit values + * are the real unitary regdomains and are the only ones which have the + * frequency bitmasks and flags set. + */ + +enum EnumRd { + NO_ENUMRD = 0x00, + NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */ + NULL1_ETSIB = 0x07, /* Israel */ + NULL1_ETSIC = 0x08, + + FCC1_FCCA = 0x10, /* USA */ + FCC1_WORLD = 0x11, /* Hong Kong */ + FCC2_FCCA = 0x20, /* Canada */ + FCC2_WORLD = 0x21, /* Australia & HK */ + FCC2_ETSIC = 0x22, + FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */ + FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */ + FCC4_FCCA = 0x12, /* FCC public safety plus UNII bands */ + FCC5_FCCA = 0x13, /* US with no DFS */ + FCC5_WORLD = 0x16, /* US with no DFS */ + FCC6_FCCA = 0x14, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for US & Canada APs */ + FCC6_WORLD = 0x23, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for Australia APs */ + + ETSI1_WORLD = 0x37, + + ETSI2_WORLD = 0x35, /* Hungary & others */ + ETSI3_WORLD = 0x36, /* France & others */ + ETSI4_WORLD = 0x30, + ETSI4_ETSIC = 0x38, + ETSI5_WORLD = 0x39, + ETSI6_WORLD = 0x34, /* Bulgaria */ + ETSI_RESERVED = 0x33, /* Reserved (Do not used) */ + FRANCE_RES = 0x31, /* Legacy France for OEM */ + + APL6_WORLD = 0x5B, /* Singapore */ + APL4_WORLD = 0x42, /* Singapore */ + APL3_FCCA = 0x50, + APL_RESERVED = 0x44, /* Reserved (Do not used) */ + APL2_WORLD = 0x45, /* Korea */ + APL2_APLC = 0x46, + APL3_WORLD = 0x47, + APL2_APLD = 0x49, /* Korea with 2.3G channels */ + APL2_FCCA = 0x4D, /* Specific Mobile Customer */ + APL1_WORLD = 0x52, /* Latin America */ + APL1_FCCA = 0x53, + APL1_ETSIC = 0x55, + APL2_ETSIC = 0x56, /* Venezuela */ + APL5_WORLD = 0x58, /* Chile */ + APL7_FCCA = 0x5C, + APL8_WORLD = 0x5D, + APL9_WORLD = 0x5E, + APL10_WORLD = 0x5F, /* Korea 5GHz for STA */ + + + MKK5_MKKA = 0x99, /* This is a temporary value. MG and DQ have to give official one */ + MKK5_FCCA = 0x9A, /* This is a temporary value. MG and DQ have to give official one */ + MKK5_MKKC = 0x88, + MKK11_MKKA = 0xD4, + MKK11_FCCA = 0xD5, + MKK11_MKKC = 0xD7, + + /* + * World mode SKUs + */ + WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */ + WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */ + WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */ + WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */ + WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */ + WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */ + + WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */ + WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */ + EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */ + + WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */ + WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */ + WORB_WORLD = 0x6B, /* WorldB (WOA SKU) */ + WORC_WORLD = 0x6C, /* WorldC (WOA SKU) */ + + /* + * Regulator domains ending in a number (e.g. APL1, + * MK1, ETSI4, etc) apply to 5GHz channel and power + * information. Regulator domains ending in a letter + * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and + * power information. + */ + APL1 = 0x0150, /* LAT & Asia */ + APL2 = 0x0250, /* LAT & Asia */ + APL3 = 0x0350, /* Taiwan */ + APL4 = 0x0450, /* Jordan */ + APL5 = 0x0550, /* Chile */ + APL6 = 0x0650, /* Singapore */ + APL7 = 0x0750, /* Taiwan */ + APL8 = 0x0850, /* Malaysia */ + APL9 = 0x0950, /* Korea */ + APL10 = 0x1050, /* Korea 5GHz */ + + ETSI1 = 0x0130, /* Europe & others */ + ETSI2 = 0x0230, /* Europe & others */ + ETSI3 = 0x0330, /* Europe & others */ + ETSI4 = 0x0430, /* Europe & others */ + ETSI5 = 0x0530, /* Europe & others */ + ETSI6 = 0x0630, /* Europe & others */ + ETSIB = 0x0B30, /* Israel */ + ETSIC = 0x0C30, /* Latin America */ + + FCC1 = 0x0110, /* US & others */ + FCC2 = 0x0120, /* Canada, Australia & New Zealand */ + FCC3 = 0x0160, /* US w/new middle band & DFS */ + FCC4 = 0x0165, + FCC5 = 0x0180, + FCC6 = 0x0610, + FCCA = 0x0A10, + + APLD = 0x0D50, /* South Korea */ + + MKK1 = 0x0140, /* Japan */ + MKK2 = 0x0240, /* Japan Extended */ + MKK3 = 0x0340, /* Japan new 5GHz */ + MKK4 = 0x0440, /* Japan new 5GHz */ + MKK5 = 0x0540, /* Japan new 5GHz */ + MKK6 = 0x0640, /* Japan new 5GHz */ + MKK7 = 0x0740, /* Japan new 5GHz */ + MKK8 = 0x0840, /* Japan new 5GHz */ + MKK9 = 0x0940, /* Japan new 5GHz */ + MKK10 = 0x1040, /* Japan new 5GHz */ + MKK11 = 0x1140, /* Japan new 5GHz */ + MKK12 = 0x1240, /* Japan new 5GHz */ + + MKKA = 0x0A40, /* Japan */ + MKKC = 0x0A50, + + NULL1 = 0x0198, + WORLD = 0x0199, + DEBUG_REG_DMN = 0x01ff, + UNINIT_REG_DMN = 0x0fff, +}; + +enum { /* conformance test limits */ + FCC = 0x10, + MKK = 0x40, + ETSI = 0x30, + NO_CTL = 0xff, + CTL_11B = 1, + CTL_11G = 2 +}; + + +/* + * The following are flags for different requirements per reg domain. + * These requirements are either inhereted from the reg domain pair or + * from the unitary reg domain if the reg domain pair flags value is + * 0 + */ + +enum { + NO_REQ = 0x00, + DISALLOW_ADHOC_11A = 0x01, + ADHOC_PER_11D = 0x02, + ADHOC_NO_11A = 0x04, + DISALLOW_ADHOC_11G = 0x08 +}; + + + + +/* + * The following describe the bit masks for different passive scan + * capability/requirements per regdomain. + */ +#define NO_PSCAN 0x00000000 +#define PSCAN_FCC 0x00000001 +#define PSCAN_ETSI 0x00000002 +#define PSCAN_MKK 0x00000004 +#define PSCAN_ETSIB 0x00000008 +#define PSCAN_ETSIC 0x00000010 +#define PSCAN_WWR 0x00000020 +#define PSCAN_DEFER 0xFFFFFFFF + +/* Bit masks for DFS per regdomain */ + +enum { + NO_DFS = 0x00, + DFS_FCC3 = 0x01, + DFS_ETSI = 0x02, + DFS_MKK = 0x04 +}; + + +#define DEF_REGDMN FCC1_FCCA + +/* + * The following table is the master list for all different freqeuncy + * bands with the complete matrix of all possible flags and settings + * for each band if it is used in ANY reg domain. + * + * The table of frequency bands is indexed by a bitmask. The ordering + * must be consistent with the enum below. When adding a new + * frequency band, be sure to match the location in the enum with the + * comments + */ + +/* + * These frequency values are as per channel tags and regulatory domain + * info. Please update them as database is updated. + */ +#define A_FREQ_MIN 4920 +#define A_FREQ_MAX 5825 + +#define A_CHAN0_FREQ 5000 +#define A_CHAN_MAX ((A_FREQ_MAX - A_CHAN0_FREQ)/5) + +#define BG_FREQ_MIN 2412 +#define BG_FREQ_MAX 2484 + +#define BG_CHAN0_FREQ 2407 +#define BG_CHAN_MIN ((BG_FREQ_MIN - BG_CHAN0_FREQ)/5) +#define BG_CHAN_MAX 14 /* corresponding to 2484 MHz */ + +#define A_20MHZ_BAND_FREQ_MAX 5000 + + +/* + * 5GHz 11A channel tags + */ + +enum { + F1_4920_4980, + F1_5040_5080, + + F1_5120_5240, + + F1_5180_5240, + F2_5180_5240, + F3_5180_5240, + F4_5180_5240, + F5_5180_5240, + F6_5180_5240, + F7_5180_5240, + + F1_5260_5280, + + F1_5260_5320, + F2_5260_5320, + F3_5260_5320, + F4_5260_5320, + F5_5260_5320, + F6_5260_5320, + + F1_5260_5700, + + F1_5280_5320, + + F1_5500_5620, + + F1_5500_5700, + F2_5500_5700, + F3_5500_5700, + F4_5500_5700, + F5_5500_5700, + F6_5500_5700, + F7_5500_5700, + + F1_5745_5805, + F2_5745_5805, + + F1_5745_5825, + F2_5745_5825, + F3_5745_5825, + F4_5745_5825, + F5_5745_5825, + F6_5745_5825, + + W1_4920_4980, + W1_5040_5080, + W1_5170_5230, + W1_5180_5240, + W1_5260_5320, + W1_5745_5825, + W1_5500_5700, +}; + + +/* 2.4 GHz table - for 11b and 11g info */ +enum { + BG1_2312_2372, + BG2_2312_2372, + + BG1_2412_2472, + BG2_2412_2472, + BG3_2412_2472, + BG4_2412_2472, + + BG1_2412_2462, + BG2_2412_2462, + + BG1_2432_2442, + + BG1_2457_2472, + + BG1_2467_2472, + + BG1_2484_2484, /* No G */ + BG2_2484_2484, /* No G */ + + BG1_2512_2732, + + WBG1_2312_2372, + WBG1_2412_2412, + WBG1_2417_2432, + WBG1_2437_2442, + WBG1_2447_2457, + WBG1_2462_2462, + WBG1_2467_2467, + WBG2_2467_2467, + WBG1_2472_2472, + WBG2_2472_2472, + WBG1_2484_2484, /* No G */ + WBG2_2484_2484, /* No G */ +}; + +#endif /* __REG_DBVALUE_H__ */ diff --git a/drivers/staging/ath6kl/include/common/roaming.h b/drivers/staging/ath6kl/include/common/roaming.h new file mode 100644 index 000000000000..8019850a0571 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/roaming.h @@ -0,0 +1,41 @@ +//------------------------------------------------------------------------------ +// <copyright file="roaming.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _ROAMING_H_ +#define _ROAMING_H_ + +/* + * The signal quality could be in terms of either snr or rssi. We should + * have an enum for both of them. For the time being, we are going to move + * it to wmi.h that is shared by both host and the target, since we are + * repartitioning the code to the host + */ +#define SIGNAL_QUALITY_NOISE_FLOOR -96 +#define SIGNAL_QUALITY_METRICS_NUM_MAX 2 +typedef enum { + SIGNAL_QUALITY_METRICS_SNR = 0, + SIGNAL_QUALITY_METRICS_RSSI, + SIGNAL_QUALITY_METRICS_ALL, +} SIGNAL_QUALITY_METRICS_TYPE; + +#endif /* _ROAMING_H_ */ diff --git a/drivers/staging/ath6kl/include/common/targaddrs.h b/drivers/staging/ath6kl/include/common/targaddrs.h new file mode 100644 index 000000000000..e8cf70354d21 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/targaddrs.h @@ -0,0 +1,245 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// +// Author(s): ="Atheros" +//------------------------------------------------------------------------------ + +#ifndef __TARGADDRS_H__ +#define __TARGADDRS_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#if defined(AR6002) +#include "AR6002/addrs.h" +#endif + +/* + * AR6K option bits, to enable/disable various features. + * By default, all option bits are 0. + * These bits can be set in LOCAL_SCRATCH register 0. + */ +#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ +#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ +#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ +#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ +#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ +#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ +#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ +#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ + +/* + * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the + * host_interest structure. It must match the address of the _host_interest + * symbol (see linker script). + * + * Host Interest is shared between Host and Target in order to coordinate + * between the two, and is intended to remain constant (with additions only + * at the end) across software releases. + * + * All addresses are available here so that it's possible to + * write a single binary that works with all Target Types. + * May be used in assembler code as well as C. + */ +#define AR6002_HOST_INTEREST_ADDRESS 0x00500400 +#define AR6003_HOST_INTEREST_ADDRESS 0x00540600 + + +#define HOST_INTEREST_MAX_SIZE 0x100 + +#if !defined(__ASSEMBLER__) +struct register_dump_s; +struct dbglog_hdr_s; + +/* + * These are items that the Host may need to access + * via BMI or via the Diagnostic Window. The position + * of items in this structure must remain constant + * across firmware revisions! + * + * Types for each item must be fixed size across + * target and host platforms. + * + * More items may be added at the end. + */ +PREPACK struct host_interest_s { + /* + * Pointer to application-defined area, if any. + * Set by Target application during startup. + */ + A_UINT32 hi_app_host_interest; /* 0x00 */ + + /* Pointer to register dump area, valid after Target crash. */ + A_UINT32 hi_failure_state; /* 0x04 */ + + /* Pointer to debug logging header */ + A_UINT32 hi_dbglog_hdr; /* 0x08 */ + + /* Indicates whether or not flash is present on Target. + * NB: flash_is_present indicator is here not just + * because it might be of interest to the Host; but + * also because it's set early on by Target's startup + * asm code and we need it to have a special RAM address + * so that it doesn't get reinitialized with the rest + * of data. + */ + A_UINT32 hi_flash_is_present; /* 0x0c */ + + /* + * General-purpose flag bits, similar to AR6000_OPTION_* flags. + * Can be used by application rather than by OS. + */ + A_UINT32 hi_option_flag; /* 0x10 */ + + /* + * Boolean that determines whether or not to + * display messages on the serial port. + */ + A_UINT32 hi_serial_enable; /* 0x14 */ + + /* Start address of Flash DataSet index, if any */ + A_UINT32 hi_dset_list_head; /* 0x18 */ + + /* Override Target application start address */ + A_UINT32 hi_app_start; /* 0x1c */ + + /* Clock and voltage tuning */ + A_UINT32 hi_skip_clock_init; /* 0x20 */ + A_UINT32 hi_core_clock_setting; /* 0x24 */ + A_UINT32 hi_cpu_clock_setting; /* 0x28 */ + A_UINT32 hi_system_sleep_setting; /* 0x2c */ + A_UINT32 hi_xtal_control_setting; /* 0x30 */ + A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ + A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ + A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ + A_UINT32 hi_clock_info; /* 0x40 */ + + /* + * Flash configuration overrides, used only + * when firmware is not executing from flash. + * (When using flash, modify the global variables + * with equivalent names.) + */ + A_UINT32 hi_bank0_addr_value; /* 0x44 */ + A_UINT32 hi_bank0_read_value; /* 0x48 */ + A_UINT32 hi_bank0_write_value; /* 0x4c */ + A_UINT32 hi_bank0_config_value; /* 0x50 */ + + /* Pointer to Board Data */ + A_UINT32 hi_board_data; /* 0x54 */ + A_UINT32 hi_board_data_initialized; /* 0x58 */ + + A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ + + A_UINT32 hi_desired_baud_rate; /* 0x60 */ + A_UINT32 hi_dbglog_config; /* 0x64 */ + A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ + A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ + + A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ + A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ + + A_UINT32 hi_refclk_hz; /* 0x78 */ + A_UINT32 hi_ext_clk_detected; /* 0x7c */ + A_UINT32 hi_dbg_uart_txpin; /* 0x80 */ + A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */ + A_UINT32 hi_hci_uart_baud; /* 0x88 */ + A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */ + /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */ + A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */ + A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */ + + A_UINT32 hi_allocram_start; /* 0x98 */ + A_UINT32 hi_allocram_sz; /* 0x9c */ + A_UINT32 hi_hci_bridge_flags; /* 0xa0 */ + A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */ + /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */ + A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ + /* 0xa8 - [0]: 1 = enable, 0 = disable + * [1]: 0 = UART FC active low, 1 = UART FC active high + * 0xa9 - [7:0]: wakeup timeout in ms + * 0xaa, 0xab - [15:0]: idle timeout in ms + */ + /* Pointer to extended board Data */ + A_UINT32 hi_board_ext_data; /* 0xac */ + A_UINT32 hi_board_ext_data_initialized; /* 0xb0 */ +} POSTPACK; + +/* Bits defined in hi_option_flag */ +#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ +#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ +#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ +#define HI_OPTION_FW_MODE_LSB 0x08 /* low bit of MODE (see below) */ +#define HI_OPTION_FW_MODE_MSB 0x10 /* high bit of MODE (see below) */ +#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ +#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ +#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ +#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */ + +/* 2 bits of hi_option_flag are used to represent 3 modes */ +#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ +#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ +#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ + +/* Fw Mode Mask */ +#define HI_OPTION_FW_MODE_MASK 0x3 +#define HI_OPTION_FW_MODE_SHIFT 0x3 + +/* + * Intended for use by Host software, this macro returns the Target RAM + * address of any item in the host_interest structure. + * Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); + */ +#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ + (A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) + +#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ + (A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) + +#define HOST_INTEREST_DBGLOG_IS_ENABLED() \ + (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) + +#define HOST_INTEREST_PROFILE_IS_ENABLED() \ + (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) + +/* Convert a Target virtual address into a Target physical address */ +#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define TARG_VTOP(TargetType, vaddr) \ + (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr)) + +/* override REV2 ROM's app start address */ +#define AR6002_REV2_APP_START_OVERRIDE 0x911A00 +#define AR6003_REV1_APP_START_OVERRIDE 0x944c00 +#define AR6003_REV1_OTP_DATA_ADDRESS 0x542800 +#define AR6003_REV2_APP_START_OVERRIDE 0x945000 +#define AR6003_REV2_OTP_DATA_ADDRESS 0x543800 +#define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600 + + +/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */ +#define AR6003_FETCH_TARG_REGS_COUNT 64 + +#endif /* !__ASSEMBLER__ */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* __TARGADDRS_H__ */ diff --git a/drivers/staging/ath6kl/include/common/testcmd.h b/drivers/staging/ath6kl/include/common/testcmd.h new file mode 100644 index 000000000000..d6616f0fab7d --- /dev/null +++ b/drivers/staging/ath6kl/include/common/testcmd.h @@ -0,0 +1,185 @@ +//------------------------------------------------------------------------------ +// <copyright file="testcmd.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef TESTCMD_H_ +#define TESTCMD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef AR6002_REV2 +#define TCMD_MAX_RATES 12 +#else +#define TCMD_MAX_RATES 28 +#endif + +typedef enum { + ZEROES_PATTERN = 0, + ONES_PATTERN, + REPEATING_10, + PN7_PATTERN, + PN9_PATTERN, + PN15_PATTERN +}TX_DATA_PATTERN; + +/* Continous tx + mode : TCMD_CONT_TX_OFF - Disabling continous tx + TCMD_CONT_TX_SINE - Enable continuous unmodulated tx + TCMD_CONT_TX_FRAME- Enable continuous modulated tx + freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g) +dataRate: 0 - 1 Mbps + 1 - 2 Mbps + 2 - 5.5 Mbps + 3 - 11 Mbps + 4 - 6 Mbps + 5 - 9 Mbps + 6 - 12 Mbps + 7 - 18 Mbps + 8 - 24 Mbps + 9 - 36 Mbps + 10 - 28 Mbps + 11 - 54 Mbps + txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx +antenna: 1 - one antenna + 2 - two antenna +Note : Enable/disable continuous tx test cmd works only when target is awake. +*/ + +typedef enum { + TCMD_CONT_TX_OFF = 0, + TCMD_CONT_TX_SINE, + TCMD_CONT_TX_FRAME, + TCMD_CONT_TX_TX99, + TCMD_CONT_TX_TX100 +} TCMD_CONT_TX_MODE; + +typedef enum { + TCMD_WLAN_MODE_NOHT = 0, + TCMD_WLAN_MODE_HT20 = 1, + TCMD_WLAN_MODE_HT40PLUS = 2, + TCMD_WLAN_MODE_HT40MINUS = 3, +} TCMD_WLAN_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; + A_UINT32 freq; + A_UINT32 dataRate; + A_INT32 txPwr; + A_UINT32 antenna; + A_UINT32 enANI; + A_UINT32 scramblerOff; + A_UINT32 aifsn; + A_UINT16 pktSz; + A_UINT16 txPattern; + A_UINT32 shortGuard; + A_UINT32 numPackets; + A_UINT32 wlanMode; +} POSTPACK TCMD_CONT_TX; + +#define TCMD_TXPATTERN_ZERONE 0x1 +#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2 + +/* Continuous Rx + act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames) + TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest + address equal specified + mac address (set via act =3) + TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the + report from the last cont + Rx test) + + TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the + target. This Overrides + the default MAC address.) + +*/ +typedef enum { + TCMD_CONT_RX_PROMIS =0, + TCMD_CONT_RX_FILTER, + TCMD_CONT_RX_REPORT, + TCMD_CONT_RX_SETMAC, + TCMD_CONT_RX_SET_ANT_SWITCH_TABLE +} TCMD_CONT_RX_ACT; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 act; + A_UINT32 enANI; + PREPACK union { + struct PREPACK TCMD_CONT_RX_PARA { + A_UINT32 freq; + A_UINT32 antenna; + A_UINT32 wlanMode; + } POSTPACK para; + struct PREPACK TCMD_CONT_RX_REPORT { + A_UINT32 totalPkt; + A_INT32 rssiInDBm; + A_UINT32 crcErrPkt; + A_UINT32 secErrPkt; + A_UINT16 rateCnt[TCMD_MAX_RATES]; + A_UINT16 rateCntShortGuard[TCMD_MAX_RATES]; + } POSTPACK report; + struct PREPACK TCMD_CONT_RX_MAC { + A_UCHAR addr[ATH_MAC_LEN]; + } POSTPACK mac; + struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE { + A_UINT32 antswitch1; + A_UINT32 antswitch2; + }POSTPACK antswitchtable; + } POSTPACK u; +} POSTPACK TCMD_CONT_RX; + +/* Force sleep/wake test cmd + mode: TCMD_PM_WAKEUP - Wakeup the target + TCMD_PM_SLEEP - Force the target to sleep. + */ +typedef enum { + TCMD_PM_WAKEUP = 1, /* be consistent with target */ + TCMD_PM_SLEEP, + TCMD_PM_DEEPSLEEP +} TCMD_PM_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; +} POSTPACK TCMD_PM; + +typedef enum { + TCMD_CONT_TX_ID, + TCMD_CONT_RX_ID, + TCMD_PM_ID +} TCMD_ID; + +typedef PREPACK union { + TCMD_CONT_TX contTx; + TCMD_CONT_RX contRx; + TCMD_PM pm; +} POSTPACK TEST_CMD; + +#ifdef __cplusplus +} +#endif + +#endif /* TESTCMD_H_ */ diff --git a/drivers/staging/ath6kl/include/common/tlpm.h b/drivers/staging/ath6kl/include/common/tlpm.h new file mode 100644 index 000000000000..659b1c07ba90 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/tlpm.h @@ -0,0 +1,38 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __TLPM_H__ +#define __TLPM_H__ + +/* idle timeout in 16-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */ +#define TLPM_DEFAULT_IDLE_TIMEOUT_MS 1000 +/* hex in LSB and MSB for HCI command */ +#define TLPM_DEFAULT_IDLE_TIMEOUT_LSB 0xE8 +#define TLPM_DEFAULT_IDLE_TIMEOUT_MSB 0x3 + +/* wakeup timeout in 8-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */ +#define TLPM_DEFAULT_WAKEUP_TIMEOUT_MS 10 + +/* default UART FC polarity is low */ +#define TLPM_DEFAULT_UART_FC_POLARITY 0 + +#endif diff --git a/drivers/staging/ath6kl/include/common/wlan_defs.h b/drivers/staging/ath6kl/include/common/wlan_defs.h new file mode 100644 index 000000000000..03e4d23788ce --- /dev/null +++ b/drivers/staging/ath6kl/include/common/wlan_defs.h @@ -0,0 +1,79 @@ +//------------------------------------------------------------------------------ +// <copyright file="wlan_defs.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __WLAN_DEFS_H__ +#define __WLAN_DEFS_H__ + +/* + * This file contains WLAN definitions that may be used across both + * Host and Target software. + */ + +typedef enum { + MODE_11A = 0, /* 11a Mode */ + MODE_11G = 1, /* 11b/g Mode */ + MODE_11B = 2, /* 11b Mode */ + MODE_11GONLY = 3, /* 11g only Mode */ +#ifdef SUPPORT_11N + MODE_11NA_HT20 = 4, /* 11a HT20 mode */ + MODE_11NG_HT20 = 5, /* 11g HT20 mode */ + MODE_11NA_HT40 = 6, /* 11a HT40 mode */ + MODE_11NG_HT40 = 7, /* 11g HT40 mode */ + MODE_UNKNOWN = 8, + MODE_MAX = 8 +#else + MODE_UNKNOWN = 4, + MODE_MAX = 4 +#endif +} WLAN_PHY_MODE; + +typedef enum { + WLAN_11A_CAPABILITY = 1, + WLAN_11G_CAPABILITY = 2, + WLAN_11AG_CAPABILITY = 3, +}WLAN_CAPABILITY; + +#ifdef SUPPORT_11N +typedef unsigned long A_RATEMASK; +#else +typedef unsigned short A_RATEMASK; +#endif + +#ifdef SUPPORT_11N +#define IS_MODE_11A(mode) (((mode) == MODE_11A) || \ + ((mode) == MODE_11NA_HT20) || \ + ((mode) == MODE_11NA_HT40)) +#define IS_MODE_11B(mode) ((mode) == MODE_11B) +#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ + ((mode) == MODE_11GONLY) || \ + ((mode) == MODE_11NG_HT20) || \ + ((mode) == MODE_11NG_HT40)) +#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) +#else +#define IS_MODE_11A(mode) ((mode) == MODE_11A) +#define IS_MODE_11B(mode) ((mode) == MODE_11B) +#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ + ((mode) == MODE_11GONLY)) +#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) +#endif /* SUPPORT_11N */ + +#endif /* __WLANDEFS_H__ */ diff --git a/drivers/staging/ath6kl/include/common/wlan_dset.h b/drivers/staging/ath6kl/include/common/wlan_dset.h new file mode 100644 index 000000000000..864a60cedf10 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/wlan_dset.h @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __WLAN_DSET_H__ +#define __WLAN_DSET_H__ + +typedef PREPACK struct wow_config_dset { + + A_UINT8 valid_dset; + A_UINT8 gpio_enable; + A_UINT16 gpio_pin; +} POSTPACK WOW_CONFIG_DSET; + +#endif diff --git a/drivers/staging/ath6kl/include/common/wmi.h b/drivers/staging/ath6kl/include/common/wmi.h new file mode 100644 index 000000000000..c75d310c37a7 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/wmi.h @@ -0,0 +1,3119 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +// +// Author(s): ="Atheros" +//------------------------------------------------------------------------------ + +/* + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to commands + * belongs to the host driver and the WMI is not required to validate + * parameters for value, proper range, or any other checking. + * + */ + +#ifndef _WMI_H_ +#define _WMI_H_ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "wmix.h" +#include "wlan_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HTC_PROTOCOL_VERSION 0x0002 +#define HTC_PROTOCOL_REVISION 0x0000 + +#define WMI_PROTOCOL_VERSION 0x0002 +#define WMI_PROTOCOL_REVISION 0x0000 + +#define ATH_MAC_LEN 6 /* length of mac in bytes */ +#define WMI_CMD_MAX_LEN 100 +#define WMI_CONTROL_MSG_MAX_LEN 256 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 +#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) +#define RFC1042OUI {0x00, 0x00, 0x00} + +#define IP_ETHERTYPE 0x0800 + +#define WMI_IMPLICIT_PSTREAM 0xFF +#define WMI_MAX_THINSTREAM 15 + +#ifdef AR6002_REV2 +#define IBSS_MAX_NUM_STA 4 +#else +#define IBSS_MAX_NUM_STA 8 +#endif + +PREPACK struct host_app_area_s { + A_UINT32 wmi_protocol_ver; +} POSTPACK; + +/* + * Data Path + */ +typedef PREPACK struct { + A_UINT8 dstMac[ATH_MAC_LEN]; + A_UINT8 srcMac[ATH_MAC_LEN]; + A_UINT16 typeOrLen; +} POSTPACK ATH_MAC_HDR; + +typedef PREPACK struct { + A_UINT8 dsap; + A_UINT8 ssap; + A_UINT8 cntl; + A_UINT8 orgCode[3]; + A_UINT16 etherType; +} POSTPACK ATH_LLC_SNAP_HDR; + +typedef enum { + DATA_MSGTYPE = 0x0, + CNTL_MSGTYPE, + SYNC_MSGTYPE, + OPT_MSGTYPE, +} WMI_MSG_TYPE; + + +/* + * Macros for operating on WMI_DATA_HDR (info) field + */ + +#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 +#define WMI_DATA_HDR_UP_MASK 0x07 +#define WMI_DATA_HDR_UP_SHIFT 2 +/* In AP mode, the same bit (b5) is used to indicate Power save state in + * the Rx dir and More data bit state in the tx direction. + */ +#define WMI_DATA_HDR_PS_MASK 0x1 +#define WMI_DATA_HDR_PS_SHIFT 5 + +#define WMI_DATA_HDR_MORE_MASK 0x1 +#define WMI_DATA_HDR_MORE_SHIFT 5 + +typedef enum { + WMI_DATA_HDR_DATA_TYPE_802_3 = 0, + WMI_DATA_HDR_DATA_TYPE_802_11, + WMI_DATA_HDR_DATA_TYPE_ACL, +} WMI_DATA_HDR_DATA_TYPE; + +#define WMI_DATA_HDR_DATA_TYPE_MASK 0x3 +#define WMI_DATA_HDR_DATA_TYPE_SHIFT 6 + +#define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT)) + +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) +#define WMI_DATA_HDR_GET_UP(h) (((h)->info >> WMI_DATA_HDR_UP_SHIFT) & WMI_DATA_HDR_UP_MASK) +#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) + +#define WMI_DATA_HDR_GET_DATA_TYPE(h) (((h)->info >> WMI_DATA_HDR_DATA_TYPE_SHIFT) & WMI_DATA_HDR_DATA_TYPE_MASK) +#define WMI_DATA_HDR_SET_DATA_TYPE(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_DATA_TYPE_MASK << WMI_DATA_HDR_DATA_TYPE_SHIFT)) | ((p) << WMI_DATA_HDR_DATA_TYPE_SHIFT)) + +#define WMI_DATA_HDR_GET_DOT11(h) (WMI_DATA_HDR_GET_DATA_TYPE((h)) == WMI_DATA_HDR_DATA_TYPE_802_11) +#define WMI_DATA_HDR_SET_DOT11(h, p) WMI_DATA_HDR_SET_DATA_TYPE((h), (p)) + +/* Macros for operating on WMI_DATA_HDR (info2) field */ +#define WMI_DATA_HDR_SEQNO_MASK 0xFFF +#define WMI_DATA_HDR_SEQNO_SHIFT 0 + +#define WMI_DATA_HDR_AMSDU_MASK 0x1 +#define WMI_DATA_HDR_AMSDU_SHIFT 12 + +#define WMI_DATA_HDR_META_MASK 0x7 +#define WMI_DATA_HDR_META_SHIFT 13 + +#define GET_SEQ_NO(_v) ((_v) & WMI_DATA_HDR_SEQNO_MASK) +#define GET_ISMSDU(_v) ((_v) & WMI_DATA_HDR_AMSDU_MASK) + +#define WMI_DATA_HDR_GET_SEQNO(h) GET_SEQ_NO((h)->info2 >> WMI_DATA_HDR_SEQNO_SHIFT) +#define WMI_DATA_HDR_SET_SEQNO(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_SEQNO_MASK << WMI_DATA_HDR_SEQNO_SHIFT)) | (GET_SEQ_NO(_v) << WMI_DATA_HDR_SEQNO_SHIFT)) + +#define WMI_DATA_HDR_IS_AMSDU(h) GET_ISMSDU((h)->info2 >> WMI_DATA_HDR_AMSDU_SHIFT) +#define WMI_DATA_HDR_SET_AMSDU(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_AMSDU_MASK << WMI_DATA_HDR_AMSDU_SHIFT)) | (GET_ISMSDU(_v) << WMI_DATA_HDR_AMSDU_SHIFT)) + +#define WMI_DATA_HDR_GET_META(h) (((h)->info2 >> WMI_DATA_HDR_META_SHIFT) & WMI_DATA_HDR_META_MASK) +#define WMI_DATA_HDR_SET_META(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_META_MASK << WMI_DATA_HDR_META_SHIFT)) | ((_v) << WMI_DATA_HDR_META_SHIFT)) + +typedef PREPACK struct { + A_INT8 rssi; + A_UINT8 info; /* usage of 'info' field(8-bit): + * b1:b0 - WMI_MSG_TYPE + * b4:b3:b2 - UP(tid) + * b5 - Used in AP mode. More-data in tx dir, PS in rx. + * b7:b6 - Dot3 header(0), + * Dot11 Header(1), + * ACL data(2) + */ + + A_UINT16 info2; /* usage of 'info2' field(16-bit): + * b11:b0 - seq_no + * b12 - A-MSDU? + * b15:b13 - META_DATA_VERSION 0 - 7 + */ + A_UINT16 reserved; +} POSTPACK WMI_DATA_HDR; + +/* + * TX META VERSION DEFINITIONS + */ +#define WMI_MAX_TX_META_SZ (12) +#define WMI_MAX_TX_META_VERSION (7) +#define WMI_META_VERSION_1 (0x01) +#define WMI_META_VERSION_2 (0X02) + +#define WMI_ACL_TO_DOT11_HEADROOM 36 + +#if 0 /* removed to prevent compile errors for WM.. */ +typedef PREPACK struct { +/* intentionally empty. Default version is no meta data. */ +} POSTPACK WMI_TX_META_V0; +#endif + +typedef PREPACK struct { + A_UINT8 pktID; /* The packet ID to identify the tx request */ + A_UINT8 ratePolicyID; /* The rate policy to be used for the tx of this frame */ +} POSTPACK WMI_TX_META_V1; + + +#define WMI_CSUM_DIR_TX (0x1) +#define TX_CSUM_CALC_FILL (0x1) +typedef PREPACK struct { + A_UINT8 csumStart; /*Offset from start of the WMI header for csum calculation to begin */ + A_UINT8 csumDest; /*Offset from start of WMI header where final csum goes*/ + A_UINT8 csumFlags; /*number of bytes over which csum is calculated*/ +} POSTPACK WMI_TX_META_V2; + + +/* + * RX META VERSION DEFINITIONS + */ +/* if RX meta data is present at all then the meta data field + * will consume WMI_MAX_RX_META_SZ bytes of space between the + * WMI_DATA_HDR and the payload. How much of the available + * Meta data is actually used depends on which meta data + * version is active. */ +#define WMI_MAX_RX_META_SZ (12) +#define WMI_MAX_RX_META_VERSION (7) + +#define WMI_RX_STATUS_OK 0 /* success */ +#define WMI_RX_STATUS_DECRYPT_ERR 1 /* decrypt error */ +#define WMI_RX_STATUS_MIC_ERR 2 /* tkip MIC error */ +#define WMI_RX_STATUS_ERR 3 /* undefined error */ + +#define WMI_RX_FLAGS_AGGR 0x0001 /* part of AGGR */ +#define WMI_RX_FlAGS_STBC 0x0002 /* used STBC */ +#define WMI_RX_FLAGS_SGI 0x0004 /* used SGI */ +#define WMI_RX_FLAGS_HT 0x0008 /* is HT packet */ +/* the flags field is also used to store the CRYPTO_TYPE of the frame + * that value is shifted by WMI_RX_FLAGS_CRYPTO_SHIFT */ +#define WMI_RX_FLAGS_CRYPTO_SHIFT 4 +#define WMI_RX_FLAGS_CRYPTO_MASK 0x1f +#define WMI_RX_META_GET_CRYPTO(flags) (((flags) >> WMI_RX_FLAGS_CRYPTO_SHIFT) & WMI_RX_FLAGS_CRYPTO_MASK) + +#if 0 /* removed to prevent compile errors for WM.. */ +typedef PREPACK struct { +/* intentionally empty. Default version is no meta data. */ +} POSTPACK WMI_RX_META_VERSION_0; +#endif + +typedef PREPACK struct { + A_UINT8 status; /* one of WMI_RX_STATUS_... */ + A_UINT8 rix; /* rate index mapped to rate at which this packet was received. */ + A_UINT8 rssi; /* rssi of packet */ + A_UINT8 channel;/* rf channel during packet reception */ + A_UINT16 flags; /* a combination of WMI_RX_FLAGS_... */ +} POSTPACK WMI_RX_META_V1; + +#define RX_CSUM_VALID_FLAG (0x1) +typedef PREPACK struct { + A_UINT16 csum; + A_UINT8 csumFlags;/* bit 0 set -partial csum valid + bit 1 set -test mode */ +} POSTPACK WMI_RX_META_V2; + + + +#define WMI_GET_DEVICE_ID(info1) ((info1) & 0xF) + +/* + * Control Path + */ +typedef PREPACK struct { + A_UINT16 commandId; +/* + * info1 - 16 bits + * b03:b00 - id + * b15:b04 - unused + */ + A_UINT16 info1; + + A_UINT16 reserved; /* For alignment */ +} POSTPACK WMI_CMD_HDR; /* used for commands and events */ + +/* + * List of Commnands + */ +typedef enum { + WMI_CONNECT_CMDID = 0x0001, + WMI_RECONNECT_CMDID, + WMI_DISCONNECT_CMDID, + WMI_SYNCHRONIZE_CMDID, + WMI_CREATE_PSTREAM_CMDID, + WMI_DELETE_PSTREAM_CMDID, + WMI_START_SCAN_CMDID, + WMI_SET_SCAN_PARAMS_CMDID, + WMI_SET_BSS_FILTER_CMDID, + WMI_SET_PROBED_SSID_CMDID, /* 10 */ + WMI_SET_LISTEN_INT_CMDID, + WMI_SET_BMISS_TIME_CMDID, + WMI_SET_DISC_TIMEOUT_CMDID, + WMI_GET_CHANNEL_LIST_CMDID, + WMI_SET_BEACON_INT_CMDID, + WMI_GET_STATISTICS_CMDID, + WMI_SET_CHANNEL_PARAMS_CMDID, + WMI_SET_POWER_MODE_CMDID, + WMI_SET_IBSS_PM_CAPS_CMDID, + WMI_SET_POWER_PARAMS_CMDID, /* 20 */ + WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + WMI_ADD_CIPHER_KEY_CMDID, + WMI_DELETE_CIPHER_KEY_CMDID, + WMI_ADD_KRK_CMDID, + WMI_DELETE_KRK_CMDID, + WMI_SET_PMKID_CMDID, + WMI_SET_TX_PWR_CMDID, + WMI_GET_TX_PWR_CMDID, + WMI_SET_ASSOC_INFO_CMDID, + WMI_ADD_BAD_AP_CMDID, /* 30 */ + WMI_DELETE_BAD_AP_CMDID, + WMI_SET_TKIP_COUNTERMEASURES_CMDID, + WMI_RSSI_THRESHOLD_PARAMS_CMDID, + WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + WMI_SET_ACCESS_PARAMS_CMDID, + WMI_SET_RETRY_LIMITS_CMDID, + WMI_SET_OPT_MODE_CMDID, + WMI_OPT_TX_FRAME_CMDID, + WMI_SET_VOICE_PKT_SIZE_CMDID, + WMI_SET_MAX_SP_LEN_CMDID, /* 40 */ + WMI_SET_ROAM_CTRL_CMDID, + WMI_GET_ROAM_TBL_CMDID, + WMI_GET_ROAM_DATA_CMDID, + WMI_ENABLE_RM_CMDID, + WMI_SET_MAX_OFFHOME_DURATION_CMDID, + WMI_EXTENSION_CMDID, /* Non-wireless extensions */ + WMI_SNR_THRESHOLD_PARAMS_CMDID, + WMI_LQ_THRESHOLD_PARAMS_CMDID, + WMI_SET_LPREAMBLE_CMDID, + WMI_SET_RTS_CMDID, /* 50 */ + WMI_CLR_RSSI_SNR_CMDID, + WMI_SET_FIXRATES_CMDID, + WMI_GET_FIXRATES_CMDID, + WMI_SET_AUTH_MODE_CMDID, + WMI_SET_REASSOC_MODE_CMDID, + WMI_SET_WMM_CMDID, + WMI_SET_WMM_TXOP_CMDID, + WMI_TEST_CMDID, + /* COEX AR6002 only*/ + WMI_SET_BT_STATUS_CMDID, + WMI_SET_BT_PARAMS_CMDID, /* 60 */ + + WMI_SET_KEEPALIVE_CMDID, + WMI_GET_KEEPALIVE_CMDID, + WMI_SET_APPIE_CMDID, + WMI_GET_APPIE_CMDID, + WMI_SET_WSC_STATUS_CMDID, + + /* Wake on Wireless */ + WMI_SET_HOST_SLEEP_MODE_CMDID, + WMI_SET_WOW_MODE_CMDID, + WMI_GET_WOW_LIST_CMDID, + WMI_ADD_WOW_PATTERN_CMDID, + WMI_DEL_WOW_PATTERN_CMDID, /* 70 */ + + WMI_SET_FRAMERATES_CMDID, + WMI_SET_AP_PS_CMDID, + WMI_SET_QOS_SUPP_CMDID, + /* WMI_THIN_RESERVED_... mark the start and end + * values for WMI_THIN_RESERVED command IDs. These + * command IDs can be found in wmi_thin.h */ + WMI_THIN_RESERVED_START = 0x8000, + WMI_THIN_RESERVED_END = 0x8fff, + /* + * Developer commands starts at 0xF000 + */ + WMI_SET_BITRATE_CMDID = 0xF000, + WMI_GET_BITRATE_CMDID, + WMI_SET_WHALPARAM_CMDID, + + + /*Should add the new command to the tail for compatible with + * etna. + */ + WMI_SET_MAC_ADDRESS_CMDID, + WMI_SET_AKMP_PARAMS_CMDID, + WMI_SET_PMKID_LIST_CMDID, + WMI_GET_PMKID_LIST_CMDID, + WMI_ABORT_SCAN_CMDID, + WMI_SET_TARGET_EVENT_REPORT_CMDID, + + // Unused + WMI_UNUSED1, + WMI_UNUSED2, + + /* + * AP mode commands + */ + WMI_AP_HIDDEN_SSID_CMDID, + WMI_AP_SET_NUM_STA_CMDID, + WMI_AP_ACL_POLICY_CMDID, + WMI_AP_ACL_MAC_LIST_CMDID, + WMI_AP_CONFIG_COMMIT_CMDID, + WMI_AP_SET_MLME_CMDID, + WMI_AP_SET_PVB_CMDID, + WMI_AP_CONN_INACT_CMDID, + WMI_AP_PROT_SCAN_TIME_CMDID, + WMI_AP_SET_COUNTRY_CMDID, + WMI_AP_SET_DTIM_CMDID, + WMI_AP_MODE_STAT_CMDID, + + WMI_SET_IP_CMDID, + WMI_SET_PARAMS_CMDID, + WMI_SET_MCAST_FILTER_CMDID, + WMI_DEL_MCAST_FILTER_CMDID, + + WMI_ALLOW_AGGR_CMDID, + WMI_ADDBA_REQ_CMDID, + WMI_DELBA_REQ_CMDID, + WMI_SET_HT_CAP_CMDID, + WMI_SET_HT_OP_CMDID, + WMI_SET_TX_SELECT_RATES_CMDID, + WMI_SET_TX_SGI_PARAM_CMDID, + WMI_SET_RATE_POLICY_CMDID, + + WMI_HCI_CMD_CMDID, + WMI_RX_FRAME_FORMAT_CMDID, + WMI_SET_THIN_MODE_CMDID, + WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID, + + WMI_AP_SET_11BG_RATESET_CMDID, + WMI_SET_PMK_CMDID, + WMI_MCAST_FILTER_CMDID, + /* COEX CMDID AR6003*/ + WMI_SET_BTCOEX_FE_ANT_CMDID, + WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID, + WMI_SET_BTCOEX_SCO_CONFIG_CMDID, + WMI_SET_BTCOEX_A2DP_CONFIG_CMDID, + WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID, + WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID, + WMI_SET_BTCOEX_DEBUG_CMDID, + WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID, + WMI_GET_BTCOEX_STATS_CMDID, + WMI_GET_BTCOEX_CONFIG_CMDID, +} WMI_COMMAND_ID; + +/* + * Frame Types + */ +typedef enum { + WMI_FRAME_BEACON = 0, + WMI_FRAME_PROBE_REQ, + WMI_FRAME_PROBE_RESP, + WMI_FRAME_ASSOC_REQ, + WMI_FRAME_ASSOC_RESP, + WMI_NUM_MGMT_FRAME +} WMI_MGMT_FRAME_TYPE; + +/* + * Connect Command + */ +typedef enum { + INFRA_NETWORK = 0x01, + ADHOC_NETWORK = 0x02, + ADHOC_CREATOR = 0x04, + AP_NETWORK = 0x10, +} NETWORK_TYPE; + +typedef enum { + OPEN_AUTH = 0x01, + SHARED_AUTH = 0x02, + LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */ +} DOT11_AUTH_MODE; + +typedef enum { + NONE_AUTH = 0x01, + WPA_AUTH = 0x02, + WPA2_AUTH = 0x04, + WPA_PSK_AUTH = 0x08, + WPA2_PSK_AUTH = 0x10, + WPA_AUTH_CCKM = 0x20, + WPA2_AUTH_CCKM = 0x40, +} AUTH_MODE; + +typedef enum { + NONE_CRYPT = 0x01, + WEP_CRYPT = 0x02, + TKIP_CRYPT = 0x04, + AES_CRYPT = 0x08, +#ifdef WAPI_ENABLE + WAPI_CRYPT = 0x10, +#endif /*WAPI_ENABLE*/ +} CRYPTO_TYPE; + +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) + +#ifdef WAPI_ENABLE +#undef WMI_MAX_CRYPTO_TYPE +#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1) +#endif /* WAPI_ENABLE */ + +#ifdef WAPI_ENABLE +#define IW_ENCODE_ALG_SM4 0x20 +#define IW_AUTH_WAPI_ENABLED 0x20 +#endif + +#define WMI_MIN_KEY_INDEX 0 +#define WMI_MAX_KEY_INDEX 3 + +#ifdef WAPI_ENABLE +#undef WMI_MAX_KEY_INDEX +#define WMI_MAX_KEY_INDEX 7 /* wapi grpKey 0-3, prwKey 4-7 */ +#endif /* WAPI_ENABLE */ + +#define WMI_MAX_KEY_LEN 32 + +#define WMI_MAX_SSID_LEN 32 + +typedef enum { + CONNECT_ASSOC_POLICY_USER = 0x0001, + CONNECT_SEND_REASSOC = 0x0002, + CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, + CONNECT_PROFILE_MATCH_DONE = 0x0008, + CONNECT_IGNORE_AAC_BEACON = 0x0010, + CONNECT_CSA_FOLLOW_BSS = 0x0020, + CONNECT_DO_WPA_OFFLOAD = 0x0040, + CONNECT_DO_NOT_DEAUTH = 0x0080, +} WMI_CONNECT_CTRL_FLAGS_BITS; + +#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) + +typedef PREPACK struct { + A_UINT8 networkType; + A_UINT8 dot11AuthMode; + A_UINT8 authMode; + A_UINT8 pairwiseCryptoType; + A_UINT8 pairwiseCryptoLen; + A_UINT8 groupCryptoType; + A_UINT8 groupCryptoLen; + A_UINT8 ssidLength; + A_UCHAR ssid[WMI_MAX_SSID_LEN]; + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ctrl_flags; +} POSTPACK WMI_CONNECT_CMD; + +/* + * WMI_RECONNECT_CMDID + */ +typedef PREPACK struct { + A_UINT16 channel; /* hint */ + A_UINT8 bssid[ATH_MAC_LEN]; /* mandatory if set */ +} POSTPACK WMI_RECONNECT_CMD; + +#define WMI_PMK_LEN 32 +typedef PREPACK struct { + A_UINT8 pmk[WMI_PMK_LEN]; +} POSTPACK WMI_SET_PMK_CMD; + +/* + * WMI_ADD_CIPHER_KEY_CMDID + */ +typedef enum { + PAIRWISE_USAGE = 0x00, + GROUP_USAGE = 0x01, + TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ +} KEY_USAGE; + +/* + * Bit Flag + * Bit 0 - Initialise TSC - default is Initialize + */ +#define KEY_OP_INIT_TSC 0x01 +#define KEY_OP_INIT_RSC 0x02 +#ifdef WAPI_ENABLE +#define KEY_OP_INIT_WAPIPN 0x10 +#endif /* WAPI_ENABLE */ + +#define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */ +#define KEY_OP_VALID_MASK 0x03 + +typedef PREPACK struct { + A_UINT8 keyIndex; + A_UINT8 keyType; + A_UINT8 keyUsage; /* KEY_USAGE */ + A_UINT8 keyLength; + A_UINT8 keyRSC[8]; /* key replay sequence counter */ + A_UINT8 key[WMI_MAX_KEY_LEN]; + A_UINT8 key_op_ctrl; /* Additional Key Control information */ + A_UINT8 key_macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_CIPHER_KEY_CMD; + +/* + * WMI_DELETE_CIPHER_KEY_CMDID + */ +typedef PREPACK struct { + A_UINT8 keyIndex; +} POSTPACK WMI_DELETE_CIPHER_KEY_CMD; + +#define WMI_KRK_LEN 16 +/* + * WMI_ADD_KRK_CMDID + */ +typedef PREPACK struct { + A_UINT8 krk[WMI_KRK_LEN]; +} POSTPACK WMI_ADD_KRK_CMD; + +/* + * WMI_SET_TKIP_COUNTERMEASURES_CMDID + */ +typedef enum { + WMI_TKIP_CM_DISABLE = 0x0, + WMI_TKIP_CM_ENABLE = 0x1, +} WMI_TKIP_CM_CONTROL; + +typedef PREPACK struct { + A_UINT8 cm_en; /* WMI_TKIP_CM_CONTROL */ +} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD; + +/* + * WMI_SET_PMKID_CMDID + */ + +#define WMI_PMKID_LEN 16 + +typedef enum { + PMKID_DISABLE = 0, + PMKID_ENABLE = 1, +} PMKID_ENABLE_FLG; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 enable; /* PMKID_ENABLE_FLG */ + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_SET_PMKID_CMD; + +/* + * WMI_START_SCAN_CMD + */ +typedef enum { + WMI_LONG_SCAN = 0, + WMI_SHORT_SCAN = 1, +} WMI_SCAN_TYPE; + +typedef PREPACK struct { + A_BOOL forceFgScan; + A_BOOL isLegacy; /* For Legacy Cisco AP compatibility */ + A_UINT32 homeDwellTime; /* Maximum duration in the home channel(milliseconds) */ + A_UINT32 forceScanInterval; /* Time interval between scans (milliseconds)*/ + A_UINT8 scanType; /* WMI_SCAN_TYPE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_START_SCAN_CMD; + +/* + * WMI_SET_SCAN_PARAMS_CMDID + */ +#define WMI_SHORTSCANRATIO_DEFAULT 3 +/* + * Warning: ScanCtrlFlag value of 0xFF is used to disable all flags in WMI_SCAN_PARAMS_CMD + * Do not add any more flags to WMI_SCAN_CTRL_FLAG_BITS + */ +typedef enum { + CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */ + SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */ + /* already connected to */ + ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */ + ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */ + REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */ + ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't + scan after a disconnect event */ + ENABLE_SCAN_ABORT_EVENT = 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */ +} WMI_SCAN_CTRL_FLAGS_BITS; + +#define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS) +#define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS) +#define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS) +#define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS) +#define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS) +#define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS) +#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT) + +#define DEFAULT_SCAN_CTRL_FLAGS (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS) + + +typedef PREPACK struct { + A_UINT16 fg_start_period; /* seconds */ + A_UINT16 fg_end_period; /* seconds */ + A_UINT16 bg_period; /* seconds */ + A_UINT16 maxact_chdwell_time; /* msec */ + A_UINT16 pas_chdwell_time; /* msec */ + A_UINT8 shortScanRatio; /* how many shorts scan for one long */ + A_UINT8 scanCtrlFlags; + A_UINT16 minact_chdwell_time; /* msec */ + A_UINT16 maxact_scan_per_ssid; /* max active scans per ssid */ + A_UINT32 max_dfsch_act_time; /* msecs */ +} POSTPACK WMI_SCAN_PARAMS_CMD; + +/* + * WMI_SET_BSS_FILTER_CMDID + */ +typedef enum { + NONE_BSS_FILTER = 0x0, /* no beacons forwarded */ + ALL_BSS_FILTER, /* all beacons forwarded */ + PROFILE_FILTER, /* only beacons matching profile */ + ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */ + CURRENT_BSS_FILTER, /* only beacons matching current BSS */ + ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */ + PROBED_SSID_FILTER, /* beacons matching probed ssid */ + LAST_BSS_FILTER, /* marker only */ +} WMI_BSS_FILTER; + +typedef PREPACK struct { + A_UINT8 bssFilter; /* see WMI_BSS_FILTER */ + A_UINT8 reserved1; /* For alignment */ + A_UINT16 reserved2; /* For alignment */ + A_UINT32 ieMask; +} POSTPACK WMI_BSS_FILTER_CMD; + +/* + * WMI_SET_PROBED_SSID_CMDID + */ +#define MAX_PROBED_SSID_INDEX 9 + +typedef enum { + DISABLE_SSID_FLAG = 0, /* disables entry */ + SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */ + ANY_SSID_FLAG = 0x02, /* probes for any ssid */ +} WMI_SSID_FLAG; + +typedef PREPACK struct { + A_UINT8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */ + A_UINT8 flag; /* WMI_SSID_FLG */ + A_UINT8 ssidLength; + A_UINT8 ssid[32]; +} POSTPACK WMI_PROBED_SSID_CMD; + +/* + * WMI_SET_LISTEN_INT_CMDID + * The Listen interval is between 15 and 3000 TUs + */ +#define MIN_LISTEN_INTERVAL 15 +#define MAX_LISTEN_INTERVAL 5000 +#define MIN_LISTEN_BEACONS 1 +#define MAX_LISTEN_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 listenInterval; + A_UINT16 numBeacons; +} POSTPACK WMI_LISTEN_INT_CMD; + +/* + * WMI_SET_BEACON_INT_CMDID + */ +typedef PREPACK struct { + A_UINT16 beaconInterval; +} POSTPACK WMI_BEACON_INT_CMD; + +/* + * WMI_SET_BMISS_TIME_CMDID + * valid values are between 1000 and 5000 TUs + */ + +#define MIN_BMISS_TIME 1000 +#define MAX_BMISS_TIME 5000 +#define MIN_BMISS_BEACONS 1 +#define MAX_BMISS_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 bmissTime; + A_UINT16 numBeacons; +} POSTPACK WMI_BMISS_TIME_CMD; + +/* + * WMI_SET_POWER_MODE_CMDID + */ +typedef enum { + REC_POWER = 0x01, + MAX_PERF_POWER, +} WMI_POWER_MODE; + +typedef PREPACK struct { + A_UINT8 powerMode; /* WMI_POWER_MODE */ +} POSTPACK WMI_POWER_MODE_CMD; + +typedef PREPACK struct { + A_INT8 status; /* WMI_SET_PARAMS_REPLY */ +} POSTPACK WMI_SET_PARAMS_REPLY; + +typedef PREPACK struct { + A_UINT32 opcode; + A_UINT32 length; + A_CHAR buffer[1]; /* WMI_SET_PARAMS */ +} POSTPACK WMI_SET_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 multicast_mac[ATH_MAC_LEN]; /* WMI_SET_MCAST_FILTER */ +} POSTPACK WMI_SET_MCAST_FILTER_CMD; + +typedef PREPACK struct { + A_UINT8 enable; /* WMI_MCAST_FILTER */ +} POSTPACK WMI_MCAST_FILTER_CMD; + +/* + * WMI_SET_POWER_PARAMS_CMDID + */ +typedef enum { + IGNORE_DTIM = 0x01, + NORMAL_DTIM = 0x02, + STICK_DTIM = 0x03, + AUTO_DTIM = 0x04, +} WMI_DTIM_POLICY; + +/* Policy to determnine whether TX should wakeup WLAN if sleeping */ +typedef enum { + TX_WAKEUP_UPON_SLEEP = 1, + TX_DONT_WAKEUP_UPON_SLEEP = 2 +} WMI_TX_WAKEUP_POLICY_UPON_SLEEP; + +/* + * Policy to determnine whether power save failure event should be sent to + * host during scanning + */ +typedef enum { + SEND_POWER_SAVE_FAIL_EVENT_ALWAYS = 1, + IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN = 2, +} POWER_SAVE_FAIL_EVENT_POLICY; + +typedef PREPACK struct { + A_UINT16 idle_period; /* msec */ + A_UINT16 pspoll_number; + A_UINT16 dtim_policy; + A_UINT16 tx_wakeup_policy; + A_UINT16 num_tx_to_wakeup; + A_UINT16 ps_fail_event_policy; +} POSTPACK WMI_POWER_PARAMS_CMD; + +/* Adhoc power save types */ +typedef enum { + ADHOC_PS_DISABLE=1, + ADHOC_PS_ATH=2, + ADHOC_PS_IEEE=3, + ADHOC_PS_OTHER=4, +} WMI_ADHOC_PS_TYPE; + +typedef PREPACK struct { + A_UINT8 power_saving; + A_UINT8 ttl; /* number of beacon periods */ + A_UINT16 atim_windows; /* msec */ + A_UINT16 timeout_value; /* msec */ +} POSTPACK WMI_IBSS_PM_CAPS_CMD; + +/* AP power save types */ +typedef enum { + AP_PS_DISABLE=1, + AP_PS_ATH=2, +} WMI_AP_PS_TYPE; + +typedef PREPACK struct { + A_UINT32 idle_time; /* in msec */ + A_UINT32 ps_period; /* in usec */ + A_UINT8 sleep_period; /* in ps periods */ + A_UINT8 psType; +} POSTPACK WMI_AP_PS_CMD; + +/* + * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID + */ +typedef enum { + IGNORE_TIM_ALL_QUEUES_APSD = 0, + PROCESS_TIM_ALL_QUEUES_APSD = 1, + IGNORE_TIM_SIMULATED_APSD = 2, + PROCESS_TIM_SIMULATED_APSD = 3, +} APSD_TIM_POLICY; + +typedef PREPACK struct { + A_UINT16 psPollTimeout; /* msec */ + A_UINT16 triggerTimeout; /* msec */ + A_UINT32 apsdTimPolicy; /* TIM behavior with ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */ + A_UINT32 simulatedAPSDTimPolicy; /* TIM behavior with simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */ +} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD; + +/* + * WMI_SET_VOICE_PKT_SIZE_CMDID + */ +typedef PREPACK struct { + A_UINT16 voicePktSize; +} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD; + +/* + * WMI_SET_MAX_SP_LEN_CMDID + */ +typedef enum { + DELIVER_ALL_PKT = 0x0, + DELIVER_2_PKT = 0x1, + DELIVER_4_PKT = 0x2, + DELIVER_6_PKT = 0x3, +} APSD_SP_LEN_TYPE; + +typedef PREPACK struct { + A_UINT8 maxSPLen; +} POSTPACK WMI_SET_MAX_SP_LEN_CMD; + +/* + * WMI_SET_DISC_TIMEOUT_CMDID + */ +typedef PREPACK struct { + A_UINT8 disconnectTimeout; /* seconds */ +} POSTPACK WMI_DISC_TIMEOUT_CMD; + +typedef enum { + UPLINK_TRAFFIC = 0, + DNLINK_TRAFFIC = 1, + BIDIR_TRAFFIC = 2, +} DIR_TYPE; + +typedef enum { + DISABLE_FOR_THIS_AC = 0, + ENABLE_FOR_THIS_AC = 1, + ENABLE_FOR_ALL_AC = 2, +} VOICEPS_CAP_TYPE; + +typedef enum { + TRAFFIC_TYPE_APERIODIC = 0, + TRAFFIC_TYPE_PERIODIC = 1, +}TRAFFIC_TYPE; + +/* + * WMI_SYNCHRONIZE_CMDID + */ +typedef PREPACK struct { + A_UINT8 dataSyncMap; +} POSTPACK WMI_SYNC_CMD; + +/* + * WMI_CREATE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT32 minServiceInt; /* in milli-sec */ + A_UINT32 maxServiceInt; /* in milli-sec */ + A_UINT32 inactivityInt; /* in milli-sec */ + A_UINT32 suspensionInt; /* in milli-sec */ + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; /* in bps */ + A_UINT32 meanDataRate; /* in bps */ + A_UINT32 peakDataRate; /* in bps */ + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; /* in bps */ + A_UINT32 sba; + A_UINT32 mediumTime; + A_UINT16 nominalMSDU; /* in octects */ + A_UINT16 maxMSDU; /* in octects */ + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 rxQueueNum; + A_UINT8 trafficType; /* TRAFFIC_TYPE */ + A_UINT8 voicePSCapability; /* VOICEPS_CAP_TYPE */ + A_UINT8 tsid; + A_UINT8 userPriority; /* 802.1D user priority */ + A_UINT8 nominalPHY; /* nominal phy rate */ +} POSTPACK WMI_CREATE_PSTREAM_CMD; + +/* + * WMI_DELETE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; + A_UINT8 tsid; +} POSTPACK WMI_DELETE_PSTREAM_CMD; + +/* + * WMI_SET_CHANNEL_PARAMS_CMDID + */ +typedef enum { + WMI_11A_MODE = 0x1, + WMI_11G_MODE = 0x2, + WMI_11AG_MODE = 0x3, + WMI_11B_MODE = 0x4, + WMI_11GONLY_MODE = 0x5, +} WMI_PHY_MODE; + +#define WMI_MAX_CHANNELS 32 + +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 scanParam; /* set if enable scan */ + A_UINT8 phyMode; /* see WMI_PHY_MODE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_CHANNEL_PARAMS_CMD; + + +/* + * WMI_RSSI_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + * Threshold values are in the ascending order, and should agree to: + * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal + * < highThreshold_upperVal) + */ + +typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_INT16 thresholdAbove1_Val; /* lowest of upper */ + A_INT16 thresholdAbove2_Val; + A_INT16 thresholdAbove3_Val; + A_INT16 thresholdAbove4_Val; + A_INT16 thresholdAbove5_Val; + A_INT16 thresholdAbove6_Val; /* highest of upper */ + A_INT16 thresholdBelow1_Val; /* lowest of bellow */ + A_INT16 thresholdBelow2_Val; + A_INT16 thresholdBelow3_Val; + A_INT16 thresholdBelow4_Val; + A_INT16 thresholdBelow5_Val; + A_INT16 thresholdBelow6_Val; /* highest of bellow */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 reserved[3]; +} POSTPACK WMI_RSSI_THRESHOLD_PARAMS_CMD; + +/* + * WMI_SNR_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + */ + +typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 thresholdAbove1_Val; /* lowest of uppper*/ + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; /* highest of upper */ + A_UINT8 thresholdBelow1_Val; /* lowest of bellow */ + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; /* highest of bellow */ + A_UINT8 reserved[3]; +} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD; + +/* + * WMI_LQ_THRESHOLD_PARAMS_CMDID + */ +typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS { + A_UINT8 enable; + A_UINT8 thresholdAbove1_Val; + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; + A_UINT8 thresholdBelow1_Val; + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; + A_UINT8 reserved[3]; +} POSTPACK WMI_LQ_THRESHOLD_PARAMS_CMD; + +typedef enum { + WMI_LPREAMBLE_DISABLED = 0, + WMI_LPREAMBLE_ENABLED +} WMI_LPREAMBLE_STATUS; + +typedef enum { + WMI_IGNORE_BARKER_IN_ERP = 0, + WMI_DONOT_IGNORE_BARKER_IN_ERP +} WMI_PREAMBLE_POLICY; + +typedef PREPACK struct { + A_UINT8 status; + A_UINT8 preamblePolicy; +}POSTPACK WMI_SET_LPREAMBLE_CMD; + +typedef PREPACK struct { + A_UINT16 threshold; +}POSTPACK WMI_SET_RTS_CMD; + +/* + * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + * Sets the error reporting event bitmask in target. Target clears it + * upon an error. Subsequent errors are counted, but not reported + * via event, unless the bitmask is set again. + */ +typedef PREPACK struct { + A_UINT32 bitmask; +} POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK; + +/* + * WMI_SET_TX_PWR_CMDID + */ +typedef PREPACK struct { + A_UINT8 dbM; /* in dbM units */ +} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY; + +/* + * WMI_SET_ASSOC_INFO_CMDID + * + * A maximum of 2 private IEs can be sent in the [Re]Assoc request. + * A 3rd one, the CCX version IE can also be set from the host. + */ +#define WMI_MAX_ASSOC_INFO_TYPE 2 +#define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */ + +#define WMI_MAX_ASSOC_INFO_LEN 240 + +typedef PREPACK struct { + A_UINT8 ieType; + A_UINT8 bufferSize; + A_UINT8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */ +} POSTPACK WMI_SET_ASSOC_INFO_CMD; + + +/* + * WMI_GET_TX_PWR_CMDID does not take any parameters + */ + +/* + * WMI_ADD_BAD_AP_CMDID + */ +#define WMI_MAX_BAD_AP_INDEX 1 + +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_BAD_AP_CMD; + +/* + * WMI_DELETE_BAD_AP_CMDID + */ +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ +} POSTPACK WMI_DELETE_BAD_AP_CMD; + +/* + * WMI_SET_ACCESS_PARAMS_CMDID + */ +#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */ +#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */ +#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */ +#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */ +#define WMI_DEFAULT_AIFSN_ACPARAM 2 +#define WMI_MAX_AIFSN_ACPARAM 15 +typedef PREPACK struct { + A_UINT16 txop; /* in units of 32 usec */ + A_UINT8 eCWmin; + A_UINT8 eCWmax; + A_UINT8 aifsn; + A_UINT8 ac; +} POSTPACK WMI_SET_ACCESS_PARAMS_CMD; + + +/* + * WMI_SET_RETRY_LIMITS_CMDID + * + * This command is used to customize the number of retries the + * wlan device will perform on a given frame. + */ +#define WMI_MIN_RETRIES 2 +#define WMI_MAX_RETRIES 13 +typedef enum { + MGMT_FRAMETYPE = 0, + CONTROL_FRAMETYPE = 1, + DATA_FRAMETYPE = 2 +} WMI_FRAMETYPE; + +typedef PREPACK struct { + A_UINT8 frameType; /* WMI_FRAMETYPE */ + A_UINT8 trafficClass; /* applies only to DATA_FRAMETYPE */ + A_UINT8 maxRetries; + A_UINT8 enableNotify; +} POSTPACK WMI_SET_RETRY_LIMITS_CMD; + +/* + * WMI_SET_ROAM_CTRL_CMDID + * + * This command is used to influence the Roaming behaviour + * Set the host biases of the BSSs before setting the roam mode as bias + * based. + */ + +/* + * Different types of Roam Control + */ + +typedef enum { + WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */ + WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */ + WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */ + WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */ +} WMI_ROAM_CTRL_TYPE; + +#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM +#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS + +/* + * ROAM MODES + */ + +typedef enum { + WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */ + WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */ + WMI_LOCK_BSS_MODE = 3 /* Lock to the Current BSS - no Roam */ +} WMI_ROAM_MODE; + +/* + * BSS HOST BIAS INFO + */ + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 bias; +} POSTPACK WMI_BSS_BIAS; + +typedef PREPACK struct { + A_UINT8 numBss; + WMI_BSS_BIAS bssBias[1]; +} POSTPACK WMI_BSS_BIAS_INFO; + +typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS { + A_UINT16 lowrssi_scan_period; + A_INT16 lowrssi_scan_threshold; + A_INT16 lowrssi_roam_threshold; + A_UINT8 roam_rssi_floor; + A_UINT8 reserved[1]; /* For alignment */ +} POSTPACK WMI_LOWRSSI_SCAN_PARAMS; + +typedef PREPACK struct { + PREPACK union { + A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */ + A_UINT8 roamMode; /* WMI_SET_ROAM_MODE */ + WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */ + WMI_LOWRSSI_SCAN_PARAMS lrScanParams; + } POSTPACK info; + A_UINT8 roamCtrlType ; +} POSTPACK WMI_SET_ROAM_CTRL_CMD; + +/* + * WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID + */ +typedef enum { + BT_WLAN_CONN_PRECDENCE_WLAN=0, /* Default */ + BT_WLAN_CONN_PRECDENCE_PAL, +} BT_WLAN_CONN_PRECEDENCE; + +typedef PREPACK struct { + A_UINT8 precedence; +} POSTPACK WMI_SET_BT_WLAN_CONN_PRECEDENCE; + +/* + * WMI_ENABLE_RM_CMDID + */ +typedef PREPACK struct { + A_BOOL enable_radio_measurements; +} POSTPACK WMI_ENABLE_RM_CMD; + +/* + * WMI_SET_MAX_OFFHOME_DURATION_CMDID + */ +typedef PREPACK struct { + A_UINT8 max_offhome_duration; +} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD; + +typedef PREPACK struct { + A_UINT32 frequency; + A_UINT8 threshold; +} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD; +/*---------------------- BTCOEX RELATED -------------------------------------*/ +/*----------------------COMMON to AR6002 and AR6003 -------------------------*/ +typedef enum { + BT_STREAM_UNDEF = 0, + BT_STREAM_SCO, /* SCO stream */ + BT_STREAM_A2DP, /* A2DP stream */ + BT_STREAM_SCAN, /* BT Discovery or Page */ + BT_STREAM_ESCO, + BT_STREAM_MAX +} BT_STREAM_TYPE; + +typedef enum { + BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1, + BT_PARAM_SCO_PSPOLL_LATENCY_HALF, + BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH, +} BT_PARAMS_SCO_PSPOLL_LATENCY; + +typedef enum { + BT_PARAMS_SCO_STOMP_SCO_NEVER =1, + BT_PARAMS_SCO_STOMP_SCO_ALWAYS, + BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI, +} BT_PARAMS_SCO_STOMP_RULES; + +typedef enum { + BT_STATUS_UNDEF = 0, + BT_STATUS_ON, + BT_STATUS_OFF, + BT_STATUS_MAX +} BT_STREAM_STATUS; + +typedef PREPACK struct { + A_UINT8 streamType; + A_UINT8 status; +} POSTPACK WMI_SET_BT_STATUS_CMD; + +typedef enum { + BT_ANT_TYPE_UNDEF=0, + BT_ANT_TYPE_DUAL, + BT_ANT_TYPE_SPLITTER, + BT_ANT_TYPE_SWITCH, + BT_ANT_TYPE_HIGH_ISO_DUAL +} BT_ANT_FRONTEND_CONFIG; + +typedef enum { + BT_COLOCATED_DEV_BTS4020=0, + BT_COLCATED_DEV_CSR , + BT_COLOCATED_DEV_VALKYRIE +} BT_COLOCATED_DEV_TYPE; + +/*********************** Applicable to AR6002 ONLY ******************************/ + +typedef enum { + BT_PARAM_SCO = 1, /* SCO stream parameters */ + BT_PARAM_A2DP , + BT_PARAM_ANTENNA_CONFIG, + BT_PARAM_COLOCATED_BT_DEVICE, + BT_PARAM_ACLCOEX, + BT_PARAM_11A_SEPARATE_ANT, + BT_PARAM_MAX +} BT_PARAM_TYPE; + + +#define BT_SCO_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_SCO_FORCE_AWAKE_OPT (1 << 1) +#define BT_SCO_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_SCO_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1) +#define BT_SCO_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3)) +#define BT_SCO_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1) +#define BT_SCO_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF) +#define BT_SCO_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF) +#define BT_SCO_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8) +#define BT_SCO_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16) + +typedef PREPACK struct { + A_UINT32 numScoCyclesForceTrigger; /* Number SCO cycles after which + force a pspoll. default = 10 */ + A_UINT32 dataResponseTimeout; /* Timeout Waiting for Downlink pkt + in response for ps-poll, + default = 10 msecs */ + A_UINT32 stompScoRules; + A_UINT32 scoOptFlags; /* SCO Options Flags : + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host supplied RSSI for OPT + 3 If set use host supplied RTS COUNT for OPT + 4..7 Unused + 8..15 Low Data Rate Min Cnt + 16..23 Low Data Rate Max Cnt + */ + + A_UINT8 stompDutyCyleVal; /* Sco cycles to limit ps-poll queuing + if stomped */ + A_UINT8 stompDutyCyleMaxVal; /*firm ware increases stomp duty cycle + gradually uptill this value on need basis*/ + A_UINT8 psPollLatencyFraction; /* Fraction of idle + period, within which + additional ps-polls + can be queued */ + A_UINT8 noSCOSlots; /* Number of SCO Tx/Rx slots. + HVx, EV3, 2EV3 = 2 */ + A_UINT8 noIdleSlots; /* Number of Bluetooth idle slots between + consecutive SCO Tx/Rx slots + HVx, EV3 = 4 + 2EV3 = 10 */ + A_UINT8 scoOptOffRssi;/*RSSI value below which we go to ps poll*/ + A_UINT8 scoOptOnRssi; /*RSSI value above which we reenter opt mode*/ + A_UINT8 scoOptRtsCount; +} POSTPACK BT_PARAMS_SCO; + +#define BT_A2DP_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_A2DP_FORCE_AWAKE_OPT (1 << 1) +#define BT_A2DP_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_A2DP_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1) +#define BT_A2DP_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3)) +#define BT_A2DP_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1) +#define BT_A2DP_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF) +#define BT_A2DP_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF) +#define BT_A2DP_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8) +#define BT_A2DP_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16) + +typedef PREPACK struct { + A_UINT32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for + wlan, after it identifies the idle time + default (30 msecs) */ + A_UINT32 a2dpBurstCntMin; /* Minimum number of bluetooth data frames + to replenish Wlan Usage limit (default 3) */ + A_UINT32 a2dpDataRespTimeout; + A_UINT32 a2dpOptFlags; /* A2DP Option flags: + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host supplied RSSI for OPT + 3 If set use host supplied RTS COUNT for OPT + 4..7 Unused + 8..15 Low Data Rate Min Cnt + 16..23 Low Data Rate Max Cnt + */ + A_UINT8 isCoLocatedBtRoleMaster; + A_UINT8 a2dpOptOffRssi;/*RSSI value below which we go to ps poll*/ + A_UINT8 a2dpOptOnRssi; /*RSSI value above which we reenter opt mode*/ + A_UINT8 a2dpOptRtsCount; +}POSTPACK BT_PARAMS_A2DP; + +/* During BT ftp/ BT OPP or any another data based acl profile on bluetooth + (non a2dp).*/ +typedef PREPACK struct { + A_UINT32 aclWlanMediumUsageTime; /* Wlan usage time during Acl (non-a2dp) + coexistence (default 30 msecs) */ + A_UINT32 aclBtMediumUsageTime; /* Bt usage time during acl coexistence + (default 30 msecs)*/ + A_UINT32 aclDataRespTimeout; + A_UINT32 aclDetectTimeout; /* ACL coexistence enabled if we get + 10 Pkts in X msec(default 100 msecs) */ + A_UINT32 aclmaxPktCnt; /* No of ACL pkts to receive before + enabling ACL coex */ + +}POSTPACK BT_PARAMS_ACLCOEX; + +typedef PREPACK struct { + PREPACK union { + BT_PARAMS_SCO scoParams; + BT_PARAMS_A2DP a2dpParams; + BT_PARAMS_ACLCOEX aclCoexParams; + A_UINT8 antType; /* 0 -Disabled (default) + 1 - BT_ANT_TYPE_DUAL + 2 - BT_ANT_TYPE_SPLITTER + 3 - BT_ANT_TYPE_SWITCH */ + A_UINT8 coLocatedBtDev; /* 0 - BT_COLOCATED_DEV_BTS4020 (default) + 1 - BT_COLCATED_DEV_CSR + 2 - BT_COLOCATED_DEV_VALKYRIe + */ + } POSTPACK info; + A_UINT8 paramType ; +} POSTPACK WMI_SET_BT_PARAMS_CMD; + +/************************ END AR6002 BTCOEX *******************************/ +/*-----------------------AR6003 BTCOEX -----------------------------------*/ + +/* ---------------WMI_SET_BTCOEX_FE_ANT_CMDID --------------------------*/ +/* Indicates front end antenna configuration. This command needs to be issued + * right after initialization and after WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID. + * AR6003 enables coexistence and antenna switching based on the configuration. + */ +typedef enum { + WMI_BTCOEX_NOT_ENABLED = 0, + WMI_BTCOEX_FE_ANT_SINGLE =1, + WMI_BTCOEX_FE_ANT_DUAL=2, + WMI_BTCOEX_FE_ANT_DUAL_HIGH_ISO=3, + WMI_BTCOEX_FE_ANT_TYPE_MAX +}WMI_BTCOEX_FE_ANT_TYPE; + +typedef PREPACK struct { + A_UINT8 btcoexFeAntType; /* 1 - WMI_BTCOEX_FE_ANT_SINGLE for single antenna front end + 2 - WMI_BTCOEX_FE_ANT_DUAL for dual antenna front end + (for isolations less 35dB, for higher isolation there + is not need to pass this command). + (not implemented) + */ +}POSTPACK WMI_SET_BTCOEX_FE_ANT_CMD; + +/* -------------WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID ----------------*/ +/* Indicate the bluetooth chip to the firmware. Firmware can have different algorithm based + * bluetooth chip type.Based on bluetooth device, different coexistence protocol would be used. + */ +typedef PREPACK struct { + A_UINT8 btcoexCoLocatedBTdev; /*1 - Qcom BT (3 -wire PTA) + 2 - CSR BT (3 wire PTA) + 3 - Atheros 3001 BT (3 wire PTA) + 4 - STE bluetooth (4-wire ePTA) + 5 - Atheros 3002 BT (4-wire MCI) + defaults= 3 (Atheros 3001 BT ) + */ +}POSTPACK WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD; + +/* -------------WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID ------------*/ +/* Configuration parameters during bluetooth inquiry and page. Page configuration + * is applicable only on interfaces which can distinguish page (applicable only for ePTA - + * STE bluetooth). + * Bluetooth inquiry start and end is indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID. + * During this the station will be power-save mode. + */ +typedef PREPACK struct { + A_UINT32 btInquiryDataFetchFrequency;/* The frequency of querying the AP for data + (via pspoll) is configured by this parameter. + "default = 10 ms" */ + + A_UINT32 protectBmissDurPostBtInquiry;/* The firmware will continue to be in inquiry state + for configured duration, after inquiry completion + . This is to ensure other bluetooth transactions + (RDP, SDP profiles, link key exchange ...etc) + goes through smoothly without wifi stomping. + default = 10 secs*/ + + A_UINT32 maxpageStomp; /*Applicable only for STE-BT interface. Currently not + used */ + A_UINT32 btInquiryPageFlag; /* Not used */ +}POSTPACK WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD; + +/*---------------------WMI_SET_BTCOEX_SCO_CONFIG_CMDID ---------------*/ +/* Configure SCO parameters. These parameters would be used whenever firmware is indicated + * of (e)SCO profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID). + * Configration of BTCOEX_SCO_CONFIG data structure are common configuration and applies + * ps-poll mode and opt mode. + * Ps-poll Mode - Station is in power-save and retrieves downlink data between sco gaps. + * Opt Mode - station is in awake state and access point can send data to station any time. + * BTCOEX_PSPOLLMODE_SCO_CONFIG - Configuration applied only during ps-poll mode. + * BTCOEX_OPTMODE_SCO_CONFIG - Configuration applied only during opt mode. + */ +#define WMI_SCO_CONFIG_FLAG_ALLOW_OPTIMIZATION (1 << 0) +#define WMI_SCO_CONFIG_FLAG_IS_EDR_CAPABLE (1 << 1) +#define WMI_SCO_CONFIG_FLAG_IS_BT_MASTER (1 << 2) +#define WMI_SCO_CONFIG_FLAG_FW_DETECT_OF_PER (1 << 3) +typedef PREPACK struct { + A_UINT32 scoSlots; /* Number of SCO Tx/Rx slots. + HVx, EV3, 2EV3 = 2 */ + A_UINT32 scoIdleSlots; /* Number of Bluetooth idle slots between + consecutive SCO Tx/Rx slots + HVx, EV3 = 4 + 2EV3 = 10 + */ + A_UINT32 scoFlags; /* SCO Options Flags : + bits: meaning: + 0 Allow Close Range Optimization + 1 Is EDR capable or Not + 2 IS Co-located Bt role Master + 3 Firmware determines the periodicity of SCO. + */ + + A_UINT32 linkId; /* applicable to STE-BT - not used */ +}POSTPACK BTCOEX_SCO_CONFIG; + +typedef PREPACK struct { + A_UINT32 scoCyclesForceTrigger; /* Number SCO cycles after which + force a pspoll. default = 10 */ + A_UINT32 scoDataResponseTimeout; /* Timeout Waiting for Downlink pkt + in response for ps-poll, + default = 20 msecs */ + + A_UINT32 scoStompDutyCyleVal; /* not implemented */ + + A_UINT32 scoStompDutyCyleMaxVal; /*Not implemented */ + + A_UINT32 scoPsPollLatencyFraction; /* Fraction of idle + period, within which + additional ps-polls can be queued + 1 - 1/4 of idle duration + 2 - 1/2 of idle duration + 3 - 3/4 of idle duration + default =2 (1/2) + */ +}POSTPACK BTCOEX_PSPOLLMODE_SCO_CONFIG; + +typedef PREPACK struct { + A_UINT32 scoStompCntIn100ms;/*max number of SCO stomp in 100ms allowed in + opt mode. If exceeds the configured value, + switch to ps-poll mode + default = 3 */ + + A_UINT32 scoContStompMax; /* max number of continous stomp allowed in opt mode. + if excedded switch to pspoll mode + default = 3 */ + + A_UINT32 scoMinlowRateMbps; /* Low rate threshold */ + + A_UINT32 scoLowRateCnt; /* number of low rate pkts (< scoMinlowRateMbps) allowed in 100 ms. + If exceeded switch/stay to ps-poll mode, lower stay in opt mode. + default = 36 + */ + + A_UINT32 scoHighPktRatio; /*(Total Rx pkts in 100 ms + 1)/ + ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms, + if exceeded switch/stay in opt mode and if lower switch/stay in pspoll mode. + default = 5 (80% of high rates) + */ + + A_UINT32 scoMaxAggrSize; /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates + max number of aggregates if it was negogiated to higher value + default = 1 + Recommended value Basic rate headsets = 1, EDR (2-EV3) =4. + */ +}POSTPACK BTCOEX_OPTMODE_SCO_CONFIG; + +typedef PREPACK struct { + A_UINT32 scanInterval; + A_UINT32 maxScanStompCnt; +}POSTPACK BTCOEX_WLANSCAN_SCO_CONFIG; + +typedef PREPACK struct { + BTCOEX_SCO_CONFIG scoConfig; + BTCOEX_PSPOLLMODE_SCO_CONFIG scoPspollConfig; + BTCOEX_OPTMODE_SCO_CONFIG scoOptModeConfig; + BTCOEX_WLANSCAN_SCO_CONFIG scoWlanScanConfig; +}POSTPACK WMI_SET_BTCOEX_SCO_CONFIG_CMD; + +/* ------------------WMI_SET_BTCOEX_A2DP_CONFIG_CMDID -------------------*/ +/* Configure A2DP profile parameters. These parameters would be used whenver firmware is indicated + * of A2DP profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID). + * Configuration of BTCOEX_A2DP_CONFIG data structure are common configuration and applies to + * ps-poll mode and opt mode. + * Ps-poll Mode - Station is in power-save and retrieves downlink data between a2dp data bursts. + * Opt Mode - station is in power save during a2dp bursts and awake in the gaps. + * BTCOEX_PSPOLLMODE_A2DP_CONFIG - Configuration applied only during ps-poll mode. + * BTCOEX_OPTMODE_A2DP_CONFIG - Configuration applied only during opt mode. + */ + +#define WMI_A2DP_CONFIG_FLAG_ALLOW_OPTIMIZATION (1 << 0) +#define WMI_A2DP_CONFIG_FLAG_IS_EDR_CAPABLE (1 << 1) +#define WMI_A2DP_CONFIG_FLAG_IS_BT_ROLE_MASTER (1 << 2) +#define WMI_A2DP_CONFIG_FLAG_IS_A2DP_HIGH_PRI (1 << 3) +#define WMI_A2DP_CONFIG_FLAG_FIND_BT_ROLE (1 << 4) + +typedef PREPACK struct { + A_UINT32 a2dpFlags; /* A2DP Option flags: + bits: meaning: + 0 Allow Close Range Optimization + 1 IS EDR capable + 2 IS Co-located Bt role Master + 3 a2dp traffic is high priority + 4 Fw detect the role of bluetooth. + */ + A_UINT32 linkId; /* Applicable only to STE-BT - not used */ + +}POSTPACK BTCOEX_A2DP_CONFIG; + +typedef PREPACK struct { + A_UINT32 a2dpWlanMaxDur; /* MAX time firmware uses the medium for + wlan, after it identifies the idle time + default (30 msecs) */ + + A_UINT32 a2dpMinBurstCnt; /* Minimum number of bluetooth data frames + to replenish Wlan Usage limit (default 3) */ + + A_UINT32 a2dpDataRespTimeout; /* Max duration firmware waits for downlink + by stomping on bluetooth + after ps-poll is acknowledged. + default = 20 ms + */ +}POSTPACK BTCOEX_PSPOLLMODE_A2DP_CONFIG; + +typedef PREPACK struct { + A_UINT32 a2dpMinlowRateMbps; /* Low rate threshold */ + + A_UINT32 a2dpLowRateCnt; /* number of low rate pkts (< a2dpMinlowRateMbps) allowed in 100 ms. + If exceeded switch/stay to ps-poll mode, lower stay in opt mode. + default = 36 + */ + + A_UINT32 a2dpHighPktRatio; /*(Total Rx pkts in 100 ms + 1)/ + ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms, + if exceeded switch/stay in opt mode and if lower switch/stay in pspoll mode. + default = 5 (80% of high rates) + */ + + A_UINT32 a2dpMaxAggrSize; /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates + max number of aggregates if it was negogiated to higher value + default = 1 + Recommended value Basic rate headsets = 1, EDR (2-EV3) =8. + */ + A_UINT32 a2dpPktStompCnt; /*number of a2dp pkts that can be stomped per burst. + default = 6*/ + +}POSTPACK BTCOEX_OPTMODE_A2DP_CONFIG; + +typedef PREPACK struct { + BTCOEX_A2DP_CONFIG a2dpConfig; + BTCOEX_PSPOLLMODE_A2DP_CONFIG a2dppspollConfig; + BTCOEX_OPTMODE_A2DP_CONFIG a2dpOptConfig; +}POSTPACK WMI_SET_BTCOEX_A2DP_CONFIG_CMD; + +/*------------ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID---------------------*/ +/* Configure non-A2dp ACL profile parameters.The starts of ACL profile can either be + * indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID orenabled via firmware detection + * which is configured via "aclCoexFlags". + * Configration of BTCOEX_ACLCOEX_CONFIG data structure are common configuration and applies + * ps-poll mode and opt mode. + * Ps-poll Mode - Station is in power-save and retrieves downlink data during wlan medium. + * Opt Mode - station is in power save during bluetooth medium time and awake during wlan duration. + * (Not implemented yet) + * + * BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG - Configuration applied only during ps-poll mode. + * BTCOEX_OPTMODE_ACLCOEX_CONFIG - Configuration applied only during opt mode. + */ + +#define WMI_ACLCOEX_FLAGS_ALLOW_OPTIMIZATION (1 << 0) +#define WMI_ACLCOEX_FLAGS_DISABLE_FW_DETECTION (1 << 1) + +typedef PREPACK struct { + A_UINT32 aclWlanMediumDur; /* Wlan usage time during Acl (non-a2dp) + coexistence (default 30 msecs) + */ + + A_UINT32 aclBtMediumDur; /* Bt usage time during acl coexistence + (default 30 msecs) + */ + + A_UINT32 aclDetectTimeout; /* BT activity observation time limit. + In this time duration, number of bt pkts are counted. + If the Cnt reaches "aclPktCntLowerLimit" value + for "aclIterToEnableCoex" iteration continuously, + firmware gets into ACL coexistence mode. + Similarly, if bt traffic count during ACL coexistence + has not reached "aclPktCntLowerLimit" continuously + for "aclIterToEnableCoex", then ACL coexistence is + disabled. + -default 100 msecs + */ + + A_UINT32 aclPktCntLowerLimit; /* Acl Pkt Cnt to be received in duration of + "aclDetectTimeout" for + "aclIterForEnDis" times to enabling ACL coex. + Similar logic is used to disable acl coexistence. + (If "aclPktCntLowerLimit" cnt of acl pkts + are not seen by the for "aclIterForEnDis" + then acl coexistence is disabled). + default = 10 + */ + + A_UINT32 aclIterForEnDis; /* number of Iteration of "aclPktCntLowerLimit" for Enabling and + Disabling Acl Coexistence. + default = 3 + */ + + A_UINT32 aclPktCntUpperLimit; /* This is upperBound limit, if there is more than + "aclPktCntUpperLimit" seen in "aclDetectTimeout", + ACL coexistence is enabled right away. + - default 15*/ + + A_UINT32 aclCoexFlags; /* A2DP Option flags: + bits: meaning: + 0 Allow Close Range Optimization + 1 disable Firmware detection + (Currently supported configuration is aclCoexFlags =0) + */ + A_UINT32 linkId; /* Applicable only for STE-BT - not used */ + +}POSTPACK BTCOEX_ACLCOEX_CONFIG; + +typedef PREPACK struct { + A_UINT32 aclDataRespTimeout; /* Max duration firmware waits for downlink + by stomping on bluetooth + after ps-poll is acknowledged. + default = 20 ms */ + +}POSTPACK BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG; + + +/* Not implemented yet*/ +typedef PREPACK struct { + A_UINT32 aclCoexMinlowRateMbps; + A_UINT32 aclCoexLowRateCnt; + A_UINT32 aclCoexHighPktRatio; + A_UINT32 aclCoexMaxAggrSize; + A_UINT32 aclPktStompCnt; +}POSTPACK BTCOEX_OPTMODE_ACLCOEX_CONFIG; + +typedef PREPACK struct { + BTCOEX_ACLCOEX_CONFIG aclCoexConfig; + BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG aclCoexPspollConfig; + BTCOEX_OPTMODE_ACLCOEX_CONFIG aclCoexOptConfig; +}POSTPACK WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD; + +/* -----------WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID ------------------*/ +typedef enum { + WMI_BTCOEX_BT_PROFILE_SCO =1, + WMI_BTCOEX_BT_PROFILE_A2DP, + WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE, + WMI_BTCOEX_BT_PROFILE_ACLCOEX, +}WMI_BTCOEX_BT_PROFILE; + +typedef PREPACK struct { + A_UINT32 btProfileType; + A_UINT32 btOperatingStatus; + A_UINT32 btLinkId; +}WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD; + +/*--------------------- WMI_SET_BTCOEX_DEBUG_CMDID ---------------------*/ +/* Used for firmware development and debugging */ +typedef PREPACK struct { + A_UINT32 btcoexDbgParam1; + A_UINT32 btcoexDbgParam2; + A_UINT32 btcoexDbgParam3; + A_UINT32 btcoexDbgParam4; + A_UINT32 btcoexDbgParam5; +}WMI_SET_BTCOEX_DEBUG_CMD; + +/*---------------------WMI_GET_BTCOEX_CONFIG_CMDID --------------------- */ +/* Command to firmware to get configuration parameters of the bt profile + * reported via WMI_BTCOEX_CONFIG_EVENTID */ +typedef PREPACK struct { + A_UINT32 btProfileType; /* 1 - SCO + 2 - A2DP + 3 - INQUIRY_PAGE + 4 - ACLCOEX + */ + A_UINT32 linkId; /* not used */ +}WMI_GET_BTCOEX_CONFIG_CMD; + +/*------------------WMI_REPORT_BTCOEX_CONFIG_EVENTID------------------- */ +/* Event from firmware to host, sent in response to WMI_GET_BTCOEX_CONFIG_CMDID + * */ +typedef PREPACK struct { + A_UINT32 btProfileType; + A_UINT32 linkId; /* not used */ + PREPACK union { + WMI_SET_BTCOEX_SCO_CONFIG_CMD scoConfigCmd; + WMI_SET_BTCOEX_A2DP_CONFIG_CMD a2dpConfigCmd; + WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD aclcoexConfig; + WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD btinquiryPageConfigCmd; + } POSTPACK info; +} POSTPACK WMI_BTCOEX_CONFIG_EVENT; + +/*------------- WMI_REPORT_BTCOEX_BTCOEX_STATS_EVENTID--------------------*/ +/* Used for firmware development and debugging*/ +typedef PREPACK struct { + A_UINT32 highRatePktCnt; + A_UINT32 firstBmissCnt; + A_UINT32 psPollFailureCnt; + A_UINT32 nullFrameFailureCnt; + A_UINT32 optModeTransitionCnt; +}BTCOEX_GENERAL_STATS; + +typedef PREPACK struct { + A_UINT32 scoStompCntAvg; + A_UINT32 scoStompIn100ms; + A_UINT32 scoMaxContStomp; + A_UINT32 scoAvgNoRetries; + A_UINT32 scoMaxNoRetriesIn100ms; +}BTCOEX_SCO_STATS; + +typedef PREPACK struct { + A_UINT32 a2dpBurstCnt; + A_UINT32 a2dpMaxBurstCnt; + A_UINT32 a2dpAvgIdletimeIn100ms; + A_UINT32 a2dpAvgStompCnt; +}BTCOEX_A2DP_STATS; + +typedef PREPACK struct { + A_UINT32 aclPktCntInBtTime; + A_UINT32 aclStompCntInWlanTime; + A_UINT32 aclPktCntIn100ms; +}BTCOEX_ACLCOEX_STATS; + +typedef PREPACK struct { + BTCOEX_GENERAL_STATS coexStats; + BTCOEX_SCO_STATS scoStats; + BTCOEX_A2DP_STATS a2dpStats; + BTCOEX_ACLCOEX_STATS aclCoexStats; +}WMI_BTCOEX_STATS_EVENT; + + +/*--------------------------END OF BTCOEX -------------------------------------*/ +typedef PREPACK struct { + A_UINT32 sleepState; +}WMI_REPORT_SLEEP_STATE_EVENT; + +typedef enum { + WMI_REPORT_SLEEP_STATUS_IS_DEEP_SLEEP =0, + WMI_REPORT_SLEEP_STATUS_IS_AWAKE +} WMI_REPORT_SLEEP_STATUS; +typedef enum { + DISCONN_EVT_IN_RECONN = 0, /* default */ + NO_DISCONN_EVT_IN_RECONN +} TARGET_EVENT_REPORT_CONFIG; + +typedef PREPACK struct { + A_UINT32 evtConfig; +} POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD; + + +typedef PREPACK struct { + A_UINT16 cmd_buf_sz; /* HCI cmd buffer size */ + A_UINT8 buf[1]; /* Absolute HCI cmd */ +} POSTPACK WMI_HCI_CMD; + +/* + * Command Replies + */ + +/* + * WMI_GET_CHANNEL_LIST_CMDID reply + */ +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 numChannels; /* number of channels in reply */ + A_UINT16 channelList[1]; /* channel in Mhz */ +} POSTPACK WMI_CHANNEL_LIST_REPLY; + +typedef enum { + A_SUCCEEDED = A_OK, + A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250, + A_SUCCEEDED_MODIFY_STREAM=251, + A_FAILED_INVALID_STREAM = 252, + A_FAILED_MAX_THINSTREAMS = 253, + A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254, +} PSTREAM_REPLY_STATUS; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ +} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 trafficClass; +} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY; + +/* + * List of Events (target to host) + */ +typedef enum { + WMI_READY_EVENTID = 0x1001, + WMI_CONNECT_EVENTID, + WMI_DISCONNECT_EVENTID, + WMI_BSSINFO_EVENTID, + WMI_CMDERROR_EVENTID, + WMI_REGDOMAIN_EVENTID, + WMI_PSTREAM_TIMEOUT_EVENTID, + WMI_NEIGHBOR_REPORT_EVENTID, + WMI_TKIP_MICERR_EVENTID, + WMI_SCAN_COMPLETE_EVENTID, /* 0x100a */ + WMI_REPORT_STATISTICS_EVENTID, + WMI_RSSI_THRESHOLD_EVENTID, + WMI_ERROR_REPORT_EVENTID, + WMI_OPT_RX_FRAME_EVENTID, + WMI_REPORT_ROAM_TBL_EVENTID, + WMI_EXTENSION_EVENTID, + WMI_CAC_EVENTID, + WMI_SNR_THRESHOLD_EVENTID, + WMI_LQ_THRESHOLD_EVENTID, + WMI_TX_RETRY_ERR_EVENTID, /* 0x1014 */ + WMI_REPORT_ROAM_DATA_EVENTID, + WMI_TEST_EVENTID, + WMI_APLIST_EVENTID, + WMI_GET_WOW_LIST_EVENTID, + WMI_GET_PMKID_LIST_EVENTID, + WMI_CHANNEL_CHANGE_EVENTID, + WMI_PEER_NODE_EVENTID, + WMI_PSPOLL_EVENTID, + WMI_DTIMEXPIRY_EVENTID, + WMI_WLAN_VERSION_EVENTID, + WMI_SET_PARAMS_REPLY_EVENTID, + WMI_ADDBA_REQ_EVENTID, /*0x1020 */ + WMI_ADDBA_RESP_EVENTID, + WMI_DELBA_REQ_EVENTID, + WMI_TX_COMPLETE_EVENTID, + WMI_HCI_EVENT_EVENTID, + WMI_ACL_DATA_EVENTID, + WMI_REPORT_SLEEP_STATE_EVENTID, +#ifdef WAPI_ENABLE + WMI_WAPI_REKEY_EVENTID, +#endif + WMI_REPORT_BTCOEX_STATS_EVENTID, + WMI_REPORT_BTCOEX_CONFIG_EVENTID, + WMI_ACM_REJECT_EVENTID, + WMI_THIN_RESERVED_START_EVENTID = 0x8000, + /* Events in this range are reserved for thinmode + * See wmi_thin.h for actual definitions */ + WMI_THIN_RESERVED_END_EVENTID = 0x8fff, + +} WMI_EVENT_ID; + + +typedef enum { + WMI_11A_CAPABILITY = 1, + WMI_11G_CAPABILITY = 2, + WMI_11AG_CAPABILITY = 3, + WMI_11NA_CAPABILITY = 4, + WMI_11NG_CAPABILITY = 5, + WMI_11NAG_CAPABILITY = 6, + // END CAPABILITY + WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY), +} WMI_PHY_CAPABILITY; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_1; + +typedef PREPACK struct { + A_UINT32 sw_version; + A_UINT32 abi_version; + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_2; + +#if defined(ATH_TARGET) +#ifdef AR6002_REV2 +#define WMI_READY_EVENT WMI_READY_EVENT_1 /* AR6002_REV2 target code */ +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* AR6001, AR6002_REV4, AR6002_REV5 */ +#endif +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */ +#endif + + +/* + * Connect Event + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 listenInterval; + A_UINT16 beaconInterval; + A_UINT32 networkType; + A_UINT8 beaconIeLen; + A_UINT8 assocReqLen; + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_CONNECT_EVENT; + +/* + * Disconnect Event + */ +typedef enum { + NO_NETWORK_AVAIL = 0x01, + LOST_LINK = 0x02, /* bmiss */ + DISCONNECT_CMD = 0x03, + BSS_DISCONNECTED = 0x04, + AUTH_FAILED = 0x05, + ASSOC_FAILED = 0x06, + NO_RESOURCES_AVAIL = 0x07, + CSERV_DISCONNECT = 0x08, + INVALID_PROFILE = 0x0a, + DOT11H_CHANNEL_SWITCH = 0x0b, + PROFILE_MISMATCH = 0x0c, + CONNECTION_EVICTED = 0x0d, + IBSS_MERGE = 0xe, +} WMI_DISCONNECT_REASON; + +typedef PREPACK struct { + A_UINT16 protocolReasonStatus; /* reason code, see 802.11 spec. */ + A_UINT8 bssid[ATH_MAC_LEN]; /* set if known */ + A_UINT8 disconnectReason ; /* see WMI_DISCONNECT_REASON */ + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_DISCONNECT_EVENT; + +/* + * BSS Info Event. + * Mechanism used to inform host of the presence and characteristic of + * wireless networks present. Consists of bss info header followed by + * the beacon or probe-response frame body. The 802.11 header is not included. + */ +typedef enum { + BEACON_FTYPE = 0x1, + PROBERESP_FTYPE, + ACTION_MGMT_FTYPE, + PROBEREQ_FTYPE, +} WMI_BI_FTYPE; + +enum { + BSS_ELEMID_CHANSWITCH = 0x01, + BSS_ELEMID_ATHEROS = 0x02, +}; + +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_BI_FTYPE */ + A_UINT8 snr; + A_INT16 rssi; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ieMask; +} POSTPACK WMI_BSS_INFO_HDR; + +/* + * BSS INFO HDR version 2.0 + * With 6 bytes HTC header and 6 bytes of WMI header + * WMI_BSS_INFO_HDR cannot be accomodated in the removed 802.11 management + * header space. + * - Reduce the ieMask to 2 bytes as only two bit flags are used + * - Remove rssi and compute it on the host. rssi = snr - 95 + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_BI_FTYPE */ + A_UINT8 snr; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 ieMask; +} POSTPACK WMI_BSS_INFO_HDR2; + +/* + * Command Error Event + */ +typedef enum { + INVALID_PARAM = 0x01, + ILLEGAL_STATE = 0x02, + INTERNAL_ERROR = 0x03, +} WMI_ERROR_CODE; + +typedef PREPACK struct { + A_UINT16 commandId; + A_UINT8 errorCode; +} POSTPACK WMI_CMD_ERROR_EVENT; + +/* + * New Regulatory Domain Event + */ +typedef PREPACK struct { + A_UINT32 regDomain; +} POSTPACK WMI_REG_DOMAIN_EVENT; + +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; +} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT; + +typedef PREPACK struct { + A_UINT8 reserve1; + A_UINT8 reserve2; + A_UINT8 reserve3; + A_UINT8 trafficClass; +} POSTPACK WMI_ACM_REJECT_EVENT; + +/* + * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform + * the host of BSS's it has found that matches the current profile. + * It can be used by the host to cache PMKs and/to initiate pre-authentication + * if the BSS supports it. The first bssid is always the current associated + * BSS. + * The bssid and bssFlags information repeats according to the number + * or APs reported. + */ +typedef enum { + WMI_DEFAULT_BSS_FLAGS = 0x00, + WMI_PREAUTH_CAPABLE_BSS = 0x01, + WMI_PMKID_VALID_BSS = 0x02, +} WMI_BSS_FLAGS; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 bssFlags; /* see WMI_BSS_FLAGS */ +} POSTPACK WMI_NEIGHBOR_INFO; + +typedef PREPACK struct { + A_INT8 numberOfAps; + WMI_NEIGHBOR_INFO neighbor[1]; +} POSTPACK WMI_NEIGHBOR_REPORT_EVENT; + +/* + * TKIP MIC Error Event + */ +typedef PREPACK struct { + A_UINT8 keyid; + A_UINT8 ismcast; +} POSTPACK WMI_TKIP_MICERR_EVENT; + +/* + * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new) + */ +typedef PREPACK struct { + A_INT32 status; +} POSTPACK WMI_SCAN_COMPLETE_EVENT; + +#define MAX_OPT_DATA_LEN 1400 + +/* + * WMI_SET_ADHOC_BSSID_CMDID + */ +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_SET_ADHOC_BSSID_CMD; + +/* + * WMI_SET_OPT_MODE_CMDID + */ +typedef enum { + SPECIAL_OFF, + SPECIAL_ON, +} OPT_MODE_TYPE; + +typedef PREPACK struct { + A_UINT8 optMode; +} POSTPACK WMI_SET_OPT_MODE_CMD; + +/* + * WMI_TX_OPT_FRAME_CMDID + */ +typedef enum { + OPT_PROBE_REQ = 0x01, + OPT_PROBE_RESP = 0x02, + OPT_CPPP_START = 0x03, + OPT_CPPP_STOP = 0x04, +} WMI_OPT_FTYPE; + +typedef PREPACK struct { + A_UINT16 optIEDataLen; + A_UINT8 frmType; + A_UINT8 dstAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 reserved; /* For alignment */ + A_UINT8 optIEData[1]; +} POSTPACK WMI_OPT_TX_FRAME_CMD; + +/* + * Special frame receive Event. + * Mechanism used to inform host of the receiption of the special frames. + * Consists of special frame info header followed by special frame body. + * The 802.11 header is not included. + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_OPT_FTYPE */ + A_INT8 snr; + A_UINT8 srcAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_OPT_RX_INFO_HDR; + +/* + * Reporting statistics. + */ +typedef PREPACK struct { + A_UINT32 tx_packets; + A_UINT32 tx_bytes; + A_UINT32 tx_unicast_pkts; + A_UINT32 tx_unicast_bytes; + A_UINT32 tx_multicast_pkts; + A_UINT32 tx_multicast_bytes; + A_UINT32 tx_broadcast_pkts; + A_UINT32 tx_broadcast_bytes; + A_UINT32 tx_rts_success_cnt; + A_UINT32 tx_packet_per_ac[4]; + A_UINT32 tx_errors_per_ac[4]; + + A_UINT32 tx_errors; + A_UINT32 tx_failed_cnt; + A_UINT32 tx_retry_cnt; + A_UINT32 tx_mult_retry_cnt; + A_UINT32 tx_rts_fail_cnt; + A_INT32 tx_unicast_rate; +}POSTPACK tx_stats_t; + +typedef PREPACK struct { + A_UINT32 rx_packets; + A_UINT32 rx_bytes; + A_UINT32 rx_unicast_pkts; + A_UINT32 rx_unicast_bytes; + A_UINT32 rx_multicast_pkts; + A_UINT32 rx_multicast_bytes; + A_UINT32 rx_broadcast_pkts; + A_UINT32 rx_broadcast_bytes; + A_UINT32 rx_fragment_pkt; + + A_UINT32 rx_errors; + A_UINT32 rx_crcerr; + A_UINT32 rx_key_cache_miss; + A_UINT32 rx_decrypt_err; + A_UINT32 rx_duplicate_frames; + A_INT32 rx_unicast_rate; +}POSTPACK rx_stats_t; + +typedef PREPACK struct { + A_UINT32 tkip_local_mic_failure; + A_UINT32 tkip_counter_measures_invoked; + A_UINT32 tkip_replays; + A_UINT32 tkip_format_errors; + A_UINT32 ccmp_format_errors; + A_UINT32 ccmp_replays; +}POSTPACK tkip_ccmp_stats_t; + +typedef PREPACK struct { + A_UINT32 power_save_failure_cnt; + A_UINT16 stop_tx_failure_cnt; + A_UINT16 atim_tx_failure_cnt; + A_UINT16 atim_rx_failure_cnt; + A_UINT16 bcn_rx_failure_cnt; +}POSTPACK pm_stats_t; + +typedef PREPACK struct { + A_UINT32 cs_bmiss_cnt; + A_UINT32 cs_lowRssi_cnt; + A_UINT16 cs_connect_cnt; + A_UINT16 cs_disconnect_cnt; + A_INT16 cs_aveBeacon_rssi; + A_UINT16 cs_roam_count; + A_INT16 cs_rssi; + A_UINT8 cs_snr; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; +} POSTPACK cserv_stats_t; + +typedef PREPACK struct { + tx_stats_t tx_stats; + rx_stats_t rx_stats; + tkip_ccmp_stats_t tkipCcmpStats; +}POSTPACK wlan_net_stats_t; + +typedef PREPACK struct { + A_UINT32 arp_received; + A_UINT32 arp_matched; + A_UINT32 arp_replied; +} POSTPACK arp_stats_t; + +typedef PREPACK struct { + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; +} POSTPACK wlan_wow_stats_t; + +typedef PREPACK struct { + A_UINT32 lqVal; + A_INT32 noise_floor_calibation; + pm_stats_t pmStats; + wlan_net_stats_t txrxStats; + wlan_wow_stats_t wowStats; + arp_stats_t arpStats; + cserv_stats_t cservStats; +} POSTPACK WMI_TARGET_STATS; + +/* + * WMI_RSSI_THRESHOLD_EVENTID. + * Indicate the RSSI events to host. Events are indicated when we breach a + * thresold value. + */ +typedef enum{ + WMI_RSSI_THRESHOLD1_ABOVE = 0, + WMI_RSSI_THRESHOLD2_ABOVE, + WMI_RSSI_THRESHOLD3_ABOVE, + WMI_RSSI_THRESHOLD4_ABOVE, + WMI_RSSI_THRESHOLD5_ABOVE, + WMI_RSSI_THRESHOLD6_ABOVE, + WMI_RSSI_THRESHOLD1_BELOW, + WMI_RSSI_THRESHOLD2_BELOW, + WMI_RSSI_THRESHOLD3_BELOW, + WMI_RSSI_THRESHOLD4_BELOW, + WMI_RSSI_THRESHOLD5_BELOW, + WMI_RSSI_THRESHOLD6_BELOW +}WMI_RSSI_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT16 rssi; + A_UINT8 range; +}POSTPACK WMI_RSSI_THRESHOLD_EVENT; + +/* + * WMI_ERROR_REPORT_EVENTID + */ +typedef enum{ + WMI_TARGET_PM_ERR_FAIL = 0x00000001, + WMI_TARGET_KEY_NOT_FOUND = 0x00000002, + WMI_TARGET_DECRYPTION_ERR = 0x00000004, + WMI_TARGET_BMISS = 0x00000008, + WMI_PSDISABLE_NODE_JOIN = 0x00000010, + WMI_TARGET_COM_ERR = 0x00000020, + WMI_TARGET_FATAL_ERR = 0x00000040 +} WMI_TARGET_ERROR_VAL; + +typedef PREPACK struct { + A_UINT32 errorVal; +}POSTPACK WMI_TARGET_ERROR_REPORT_EVENT; + +typedef PREPACK struct { + A_UINT8 retrys; +}POSTPACK WMI_TX_RETRY_ERR_EVENT; + +typedef enum{ + WMI_SNR_THRESHOLD1_ABOVE = 1, + WMI_SNR_THRESHOLD1_BELOW, + WMI_SNR_THRESHOLD2_ABOVE, + WMI_SNR_THRESHOLD2_BELOW, + WMI_SNR_THRESHOLD3_ABOVE, + WMI_SNR_THRESHOLD3_BELOW, + WMI_SNR_THRESHOLD4_ABOVE, + WMI_SNR_THRESHOLD4_BELOW +} WMI_SNR_THRESHOLD_VAL; + +typedef PREPACK struct { + A_UINT8 range; /* WMI_SNR_THRESHOLD_VAL */ + A_UINT8 snr; +}POSTPACK WMI_SNR_THRESHOLD_EVENT; + +typedef enum{ + WMI_LQ_THRESHOLD1_ABOVE = 1, + WMI_LQ_THRESHOLD1_BELOW, + WMI_LQ_THRESHOLD2_ABOVE, + WMI_LQ_THRESHOLD2_BELOW, + WMI_LQ_THRESHOLD3_ABOVE, + WMI_LQ_THRESHOLD3_BELOW, + WMI_LQ_THRESHOLD4_ABOVE, + WMI_LQ_THRESHOLD4_BELOW +} WMI_LQ_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT32 lq; + A_UINT8 range; /* WMI_LQ_THRESHOLD_VAL */ +}POSTPACK WMI_LQ_THRESHOLD_EVENT; +/* + * WMI_REPORT_ROAM_TBL_EVENTID + */ +#define MAX_ROAM_TBL_CAND 5 + +typedef PREPACK struct { + A_INT32 roam_util; + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 rssi; + A_INT8 rssidt; + A_INT8 last_rssi; + A_INT8 util; + A_INT8 bias; + A_UINT8 reserved; /* For alignment */ +} POSTPACK WMI_BSS_ROAM_INFO; + + +typedef PREPACK struct { + A_UINT16 roamMode; + A_UINT16 numEntries; + WMI_BSS_ROAM_INFO bssRoamInfo[1]; +} POSTPACK WMI_TARGET_ROAM_TBL; + +/* + * WMI_HCI_EVENT_EVENTID + */ +typedef PREPACK struct { + A_UINT16 evt_buf_sz; /* HCI event buffer size */ + A_UINT8 buf[1]; /* HCI event */ +} POSTPACK WMI_HCI_EVENT; + +/* + * WMI_CAC_EVENTID + */ +typedef enum { + CAC_INDICATION_ADMISSION = 0x00, + CAC_INDICATION_ADMISSION_RESP = 0x01, + CAC_INDICATION_DELETE = 0x02, + CAC_INDICATION_NO_RESP = 0x03, +}CAC_INDICATION; + +#define WMM_TSPEC_IE_LEN 63 + +typedef PREPACK struct { + A_UINT8 ac; + A_UINT8 cac_indication; + A_UINT8 statusCode; + A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN]; +}POSTPACK WMI_CAC_EVENT; + +/* + * WMI_APLIST_EVENTID + */ + +typedef enum { + APLIST_VER1 = 1, +} APLIST_VER; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 channel; +} POSTPACK WMI_AP_INFO_V1; + +typedef PREPACK union { + WMI_AP_INFO_V1 apInfoV1; +} POSTPACK WMI_AP_INFO; + +typedef PREPACK struct { + A_UINT8 apListVer; + A_UINT8 numAP; + WMI_AP_INFO apList[1]; +} POSTPACK WMI_APLIST_EVENT; + +/* + * developer commands + */ + +/* + * WMI_SET_BITRATE_CMDID + * + * Get bit rate cmd uses same definition as set bit rate cmd + */ +typedef enum { + RATE_AUTO = -1, + RATE_1Mb = 0, + RATE_2Mb = 1, + RATE_5_5Mb = 2, + RATE_11Mb = 3, + RATE_6Mb = 4, + RATE_9Mb = 5, + RATE_12Mb = 6, + RATE_18Mb = 7, + RATE_24Mb = 8, + RATE_36Mb = 9, + RATE_48Mb = 10, + RATE_54Mb = 11, + RATE_MCS_0_20 = 12, + RATE_MCS_1_20 = 13, + RATE_MCS_2_20 = 14, + RATE_MCS_3_20 = 15, + RATE_MCS_4_20 = 16, + RATE_MCS_5_20 = 17, + RATE_MCS_6_20 = 18, + RATE_MCS_7_20 = 19, + RATE_MCS_0_40 = 20, + RATE_MCS_1_40 = 21, + RATE_MCS_2_40 = 22, + RATE_MCS_3_40 = 23, + RATE_MCS_4_40 = 24, + RATE_MCS_5_40 = 25, + RATE_MCS_6_40 = 26, + RATE_MCS_7_40 = 27, +} WMI_BIT_RATE; + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ + A_INT8 mgmtRateIndex; + A_INT8 ctlRateIndex; +} POSTPACK WMI_BIT_RATE_CMD; + + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ +} POSTPACK WMI_BIT_RATE_REPLY; + + +/* + * WMI_SET_FIXRATES_CMDID + * + * Get fix rates cmd uses same definition as set fix rates cmd + */ +#define FIX_RATE_1Mb ((A_UINT32)0x1) +#define FIX_RATE_2Mb ((A_UINT32)0x2) +#define FIX_RATE_5_5Mb ((A_UINT32)0x4) +#define FIX_RATE_11Mb ((A_UINT32)0x8) +#define FIX_RATE_6Mb ((A_UINT32)0x10) +#define FIX_RATE_9Mb ((A_UINT32)0x20) +#define FIX_RATE_12Mb ((A_UINT32)0x40) +#define FIX_RATE_18Mb ((A_UINT32)0x80) +#define FIX_RATE_24Mb ((A_UINT32)0x100) +#define FIX_RATE_36Mb ((A_UINT32)0x200) +#define FIX_RATE_48Mb ((A_UINT32)0x400) +#define FIX_RATE_54Mb ((A_UINT32)0x800) +#define FIX_RATE_MCS_0_20 ((A_UINT32)0x1000) +#define FIX_RATE_MCS_1_20 ((A_UINT32)0x2000) +#define FIX_RATE_MCS_2_20 ((A_UINT32)0x4000) +#define FIX_RATE_MCS_3_20 ((A_UINT32)0x8000) +#define FIX_RATE_MCS_4_20 ((A_UINT32)0x10000) +#define FIX_RATE_MCS_5_20 ((A_UINT32)0x20000) +#define FIX_RATE_MCS_6_20 ((A_UINT32)0x40000) +#define FIX_RATE_MCS_7_20 ((A_UINT32)0x80000) +#define FIX_RATE_MCS_0_40 ((A_UINT32)0x100000) +#define FIX_RATE_MCS_1_40 ((A_UINT32)0x200000) +#define FIX_RATE_MCS_2_40 ((A_UINT32)0x400000) +#define FIX_RATE_MCS_3_40 ((A_UINT32)0x800000) +#define FIX_RATE_MCS_4_40 ((A_UINT32)0x1000000) +#define FIX_RATE_MCS_5_40 ((A_UINT32)0x2000000) +#define FIX_RATE_MCS_6_40 ((A_UINT32)0x4000000) +#define FIX_RATE_MCS_7_40 ((A_UINT32)0x8000000) + +typedef PREPACK struct { + A_UINT32 fixRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY; + +typedef PREPACK struct { + A_UINT8 bEnableMask; + A_UINT8 frameType; /*type and subtype*/ + A_UINT32 frameRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FRAME_RATES_CMD, WMI_FRAME_RATES_REPLY; + +/* + * WMI_SET_RECONNECT_AUTH_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + RECONN_DO_AUTH = 0x00, + RECONN_NOT_AUTH = 0x01 +} WMI_AUTH_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +} POSTPACK WMI_SET_AUTH_MODE_CMD; + +/* + * WMI_SET_REASSOC_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + REASSOC_DO_DISASSOC = 0x00, + REASSOC_DONOT_DISASSOC = 0x01 +} WMI_REASSOC_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +}POSTPACK WMI_SET_REASSOC_MODE_CMD; + +typedef enum { + ROAM_DATA_TIME = 1, /* Get The Roam Time Data */ +} ROAM_DATA_TYPE; + +typedef PREPACK struct { + A_UINT32 disassoc_time; + A_UINT32 no_txrx_time; + A_UINT32 assoc_time; + A_UINT32 allow_txrx_time; + A_UINT8 disassoc_bssid[ATH_MAC_LEN]; + A_INT8 disassoc_bss_rssi; + A_UINT8 assoc_bssid[ATH_MAC_LEN]; + A_INT8 assoc_bss_rssi; +} POSTPACK WMI_TARGET_ROAM_TIME; + +typedef PREPACK struct { + PREPACK union { + WMI_TARGET_ROAM_TIME roamTime; + } POSTPACK u; + A_UINT8 roamDataType ; +} POSTPACK WMI_TARGET_ROAM_DATA; + +typedef enum { + WMI_WMM_DISABLED = 0, + WMI_WMM_ENABLED +} WMI_WMM_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_WMM_CMD; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_QOS_SUPP_CMD; + +typedef enum { + WMI_TXOP_DISABLED = 0, + WMI_TXOP_ENABLED +} WMI_TXOP_CFG; + +typedef PREPACK struct { + A_UINT8 txopEnable; +}POSTPACK WMI_SET_WMM_TXOP_CMD; + +typedef PREPACK struct { + A_UINT8 keepaliveInterval; +} POSTPACK WMI_SET_KEEPALIVE_CMD; + +typedef PREPACK struct { + A_BOOL configured; + A_UINT8 keepaliveInterval; +} POSTPACK WMI_GET_KEEPALIVE_CMD; + +/* + * Add Application specified IE to a management frame + */ +#define WMI_MAX_IE_LEN 255 + +typedef PREPACK struct { + A_UINT8 mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */ + A_UINT8 ieLen; /* Length of the IE that should be added to the MGMT frame */ + A_UINT8 ieInfo[1]; +} POSTPACK WMI_SET_APPIE_CMD; + +/* + * Notify the WSC registration status to the target + */ +#define WSC_REG_ACTIVE 1 +#define WSC_REG_INACTIVE 0 +/* Generic Hal Interface for setting hal paramters. */ +/* Add new Set HAL Param cmdIds here for newer params */ +typedef enum { + WHAL_SETCABTO_CMDID = 1, +}WHAL_CMDID; + +typedef PREPACK struct { + A_UINT8 cabTimeOut; +} POSTPACK WHAL_SETCABTO_PARAM; + +typedef PREPACK struct { + A_UINT8 whalCmdId; + A_UINT8 data[1]; +} POSTPACK WHAL_PARAMCMD; + + +#define WOW_MAX_FILTER_LISTS 1 /*4*/ +#define WOW_MAX_FILTERS_PER_LIST 4 +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + +#define MAC_MAX_FILTERS_PER_LIST 4 + +typedef PREPACK struct { + A_UINT8 wow_valid_filter; + A_UINT8 wow_filter_id; + A_UINT8 wow_filter_size; + A_UINT8 wow_filter_offset; + A_UINT8 wow_filter_mask[WOW_MASK_SIZE]; + A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE]; +} POSTPACK WOW_FILTER; + + +typedef PREPACK struct { + A_UINT8 wow_valid_list; + A_UINT8 wow_list_id; + A_UINT8 wow_num_filters; + A_UINT8 wow_total_list_size; + WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST]; +} POSTPACK WOW_FILTER_LIST; + +typedef PREPACK struct { + A_UINT8 valid_filter; + A_UINT8 mac_addr[ATH_MAC_LEN]; +} POSTPACK MAC_FILTER; + + +typedef PREPACK struct { + A_UINT8 total_list_size; + A_UINT8 enable; + MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST]; +} POSTPACK MAC_FILTER_LIST; + +#define MAX_IP_ADDRS 2 +typedef PREPACK struct { + A_UINT32 ips[MAX_IP_ADDRS]; /* IP in Network Byte Order */ +} POSTPACK WMI_SET_IP_CMD; + +typedef PREPACK struct { + A_BOOL awake; + A_BOOL asleep; +} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD; + +typedef enum { + WOW_FILTER_SSID = 0x1 +} WMI_WOW_FILTER; + +typedef PREPACK struct { + A_BOOL enable_wow; + WMI_WOW_FILTER filter; + A_UINT16 hostReqDelay; +} POSTPACK WMI_SET_WOW_MODE_CMD; + +typedef PREPACK struct { + A_UINT8 filter_list_id; +} POSTPACK WMI_GET_WOW_LIST_CMD; + +/* + * WMI_GET_WOW_LIST_CMD reply + */ +typedef PREPACK struct { + A_UINT8 num_filters; /* number of patterns in reply */ + A_UINT8 this_filter_num; /* this is filter # x of total num_filters */ + A_UINT8 wow_mode; + A_UINT8 host_mode; + WOW_FILTER wow_filters[1]; +} POSTPACK WMI_GET_WOW_LIST_REPLY; + +typedef PREPACK struct { + A_UINT8 filter_list_id; + A_UINT8 filter_size; + A_UINT8 filter_offset; + A_UINT8 filter[1]; +} POSTPACK WMI_ADD_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT16 filter_list_id; + A_UINT16 filter_id; +} POSTPACK WMI_DEL_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_SET_MAC_ADDRESS_CMD; + +/* + * WMI_SET_AKMP_PARAMS_CMD + */ + +#define WMI_AKMP_MULTI_PMKID_EN 0x000001 + +typedef PREPACK struct { + A_UINT32 akmpInfo; +} POSTPACK WMI_SET_AKMP_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_PMKID; + +/* + * WMI_SET_PMKID_LIST_CMD + */ +#define WMI_MAX_PMKID_CACHE 8 + +typedef PREPACK struct { + A_UINT32 numPMKID; + WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; +} POSTPACK WMI_SET_PMKID_LIST_CMD; + +/* + * WMI_GET_PMKID_LIST_CMD Reply + * Following the Number of PMKIDs is the list of PMKIDs + */ +typedef PREPACK struct { + A_UINT32 numPMKID; + A_UINT8 bssidList[ATH_MAC_LEN][1]; + WMI_PMKID pmkidList[1]; +} POSTPACK WMI_PMKID_LIST_REPLY; + +typedef PREPACK struct { + A_UINT16 oldChannel; + A_UINT32 newChannel; +} POSTPACK WMI_CHANNEL_CHANGE_EVENT; + +typedef PREPACK struct { + A_UINT32 version; +} POSTPACK WMI_WLAN_VERSION_EVENT; + + +/* WMI_ADDBA_REQ_EVENTID */ +typedef PREPACK struct { + A_UINT8 tid; + A_UINT8 win_sz; + A_UINT16 st_seq_no; + A_UINT8 status; /* f/w response for ADDBA Req; OK(0) or failure(!=0) */ +} POSTPACK WMI_ADDBA_REQ_EVENT; + +/* WMI_ADDBA_RESP_EVENTID */ +typedef PREPACK struct { + A_UINT8 tid; + A_UINT8 status; /* OK(0), failure (!=0) */ + A_UINT16 amsdu_sz; /* Three values: Not supported(0), 3839, 8k */ +} POSTPACK WMI_ADDBA_RESP_EVENT; + +/* WMI_DELBA_EVENTID + * f/w received a DELBA for peer and processed it. + * Host is notified of this + */ +typedef PREPACK struct { + A_UINT8 tid; + A_UINT8 is_peer_initiator; + A_UINT16 reason_code; +} POSTPACK WMI_DELBA_EVENT; + + +#ifdef WAPI_ENABLE +#define WAPI_REKEY_UCAST 1 +#define WAPI_REKEY_MCAST 2 +typedef PREPACK struct { + A_UINT8 type; + A_UINT8 macAddr[ATH_MAC_LEN]; +} POSTPACK WMI_WAPIREKEY_EVENT; +#endif + + +/* WMI_ALLOW_AGGR_CMDID + * Configures tid's to allow ADDBA negotiations + * on each tid, in each direction + */ +typedef PREPACK struct { + A_UINT16 tx_allow_aggr; /* 16-bit mask to allow uplink ADDBA negotiation - bit position indicates tid*/ + A_UINT16 rx_allow_aggr; /* 16-bit mask to allow donwlink ADDBA negotiation - bit position indicates tid*/ +} POSTPACK WMI_ALLOW_AGGR_CMD; + +/* WMI_ADDBA_REQ_CMDID + * f/w starts performing ADDBA negotiations with peer + * on the given tid + */ +typedef PREPACK struct { + A_UINT8 tid; +} POSTPACK WMI_ADDBA_REQ_CMD; + +/* WMI_DELBA_REQ_CMDID + * f/w would teardown BA with peer. + * is_send_initiator indicates if it's or tx or rx side + */ +typedef PREPACK struct { + A_UINT8 tid; + A_UINT8 is_sender_initiator; + +} POSTPACK WMI_DELBA_REQ_CMD; + +#define PEER_NODE_JOIN_EVENT 0x00 +#define PEER_NODE_LEAVE_EVENT 0x01 +#define PEER_FIRST_NODE_JOIN_EVENT 0x10 +#define PEER_LAST_NODE_LEAVE_EVENT 0x11 +typedef PREPACK struct { + A_UINT8 eventCode; + A_UINT8 peerMacAddr[ATH_MAC_LEN]; +} POSTPACK WMI_PEER_NODE_EVENT; + +#define IEEE80211_FRAME_TYPE_MGT 0x00 +#define IEEE80211_FRAME_TYPE_CTL 0x04 + +/* + * Transmit complete event data structure(s) + */ + + +typedef PREPACK struct { +#define TX_COMPLETE_STATUS_SUCCESS 0 +#define TX_COMPLETE_STATUS_RETRIES 1 +#define TX_COMPLETE_STATUS_NOLINK 2 +#define TX_COMPLETE_STATUS_TIMEOUT 3 +#define TX_COMPLETE_STATUS_OTHER 4 + + A_UINT8 status; /* one of TX_COMPLETE_STATUS_... */ + A_UINT8 pktID; /* packet ID to identify parent packet */ + A_UINT8 rateIdx; /* rate index on successful transmission */ + A_UINT8 ackFailures; /* number of ACK failures in tx attempt */ +#if 0 /* optional params currently ommitted. */ + A_UINT32 queueDelay; // usec delay measured Tx Start time - host delivery time + A_UINT32 mediaDelay; // usec delay measured ACK rx time - host delivery time +#endif +} POSTPACK TX_COMPLETE_MSG_V1; /* version 1 of tx complete msg */ + +typedef PREPACK struct { + A_UINT8 numMessages; /* number of tx comp msgs following this struct */ + A_UINT8 msgLen; /* length in bytes for each individual msg following this struct */ + A_UINT8 msgType; /* version of tx complete msg data following this struct */ + A_UINT8 reserved; /* individual messages follow this header */ +} POSTPACK WMI_TX_COMPLETE_EVENT; + +#define WMI_TXCOMPLETE_VERSION_1 (0x01) + + +/* + * ------- AP Mode definitions -------------- + */ + +/* + * !!! Warning !!! + * -Changing the following values needs compilation of both driver and firmware + */ +#ifdef AR6002_REV2 +#define AP_MAX_NUM_STA 4 +#else +#define AP_MAX_NUM_STA 8 +#endif +#define AP_ACL_SIZE 10 +#define IEEE80211_MAX_IE 256 +#define MCAST_AID 0xFF /* Spl. AID used to set DTIM flag in the beacons */ +#define DEF_AP_COUNTRY_CODE "US " +#define DEF_AP_WMODE_G WMI_11G_MODE +#define DEF_AP_WMODE_AG WMI_11AG_MODE +#define DEF_AP_DTIM 5 +#define DEF_BEACON_INTERVAL 100 + +/* AP mode disconnect reasons */ +#define AP_DISCONNECT_STA_LEFT 101 +#define AP_DISCONNECT_FROM_HOST 102 +#define AP_DISCONNECT_COMM_TIMEOUT 103 + +/* + * Used with WMI_AP_HIDDEN_SSID_CMDID + */ +#define HIDDEN_SSID_FALSE 0 +#define HIDDEN_SSID_TRUE 1 +typedef PREPACK struct { + A_UINT8 hidden_ssid; +} POSTPACK WMI_AP_HIDDEN_SSID_CMD; + +/* + * Used with WMI_AP_ACL_POLICY_CMDID + */ +#define AP_ACL_DISABLE 0x00 +#define AP_ACL_ALLOW_MAC 0x01 +#define AP_ACL_DENY_MAC 0x02 +#define AP_ACL_RETAIN_LIST_MASK 0x80 +typedef PREPACK struct { + A_UINT8 policy; +} POSTPACK WMI_AP_ACL_POLICY_CMD; + +/* + * Used with WMI_AP_ACL_MAC_LIST_CMDID + */ +#define ADD_MAC_ADDR 1 +#define DEL_MAC_ADDR 2 +typedef PREPACK struct { + A_UINT8 action; + A_UINT8 index; + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 wildcard; +} POSTPACK WMI_AP_ACL_MAC_CMD; + +typedef PREPACK struct { + A_UINT16 index; + A_UINT8 acl_mac[AP_ACL_SIZE][ATH_MAC_LEN]; + A_UINT8 wildcard[AP_ACL_SIZE]; + A_UINT8 policy; +} POSTPACK WMI_AP_ACL; + +/* + * Used with WMI_AP_SET_NUM_STA_CMDID + */ +typedef PREPACK struct { + A_UINT8 num_sta; +} POSTPACK WMI_AP_SET_NUM_STA_CMD; + +/* + * Used with WMI_AP_SET_MLME_CMDID + */ +typedef PREPACK struct { + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT16 reason; /* 802.11 reason code */ + A_UINT8 cmd; /* operation to perform */ +#define WMI_AP_MLME_ASSOC 1 /* associate station */ +#define WMI_AP_DISASSOC 2 /* disassociate station */ +#define WMI_AP_DEAUTH 3 /* deauthenticate station */ +#define WMI_AP_MLME_AUTHORIZE 4 /* authorize station */ +#define WMI_AP_MLME_UNAUTHORIZE 5 /* unauthorize station */ +} POSTPACK WMI_AP_SET_MLME_CMD; + +typedef PREPACK struct { + A_UINT32 period; +} POSTPACK WMI_AP_CONN_INACT_CMD; + +typedef PREPACK struct { + A_UINT32 period_min; + A_UINT32 dwell_ms; +} POSTPACK WMI_AP_PROT_SCAN_TIME_CMD; + +typedef PREPACK struct { + A_BOOL flag; + A_UINT16 aid; +} POSTPACK WMI_AP_SET_PVB_CMD; + +#define WMI_DISABLE_REGULATORY_CODE "FF" + +typedef PREPACK struct { + A_UCHAR countryCode[3]; +} POSTPACK WMI_AP_SET_COUNTRY_CMD; + +typedef PREPACK struct { + A_UINT8 dtim; +} POSTPACK WMI_AP_SET_DTIM_CMD; + +typedef PREPACK struct { + A_UINT8 band; /* specifies which band to apply these values */ + A_UINT8 enable; /* allows 11n to be disabled on a per band basis */ + A_UINT8 chan_width_40M_supported; + A_UINT8 short_GI_20MHz; + A_UINT8 short_GI_40MHz; + A_UINT8 intolerance_40MHz; + A_UINT8 max_ampdu_len_exp; +} POSTPACK WMI_SET_HT_CAP_CMD; + +typedef PREPACK struct { + A_UINT8 sta_chan_width; +} POSTPACK WMI_SET_HT_OP_CMD; + +typedef PREPACK struct { + A_UINT32 rateMasks[8]; +} POSTPACK WMI_SET_TX_SELECT_RATES_CMD; + +typedef PREPACK struct { + A_UINT32 sgiMask; + A_UINT8 sgiPERThreshold; +} POSTPACK WMI_SET_TX_SGI_PARAM_CMD; + +#define DEFAULT_SGI_MASK 0x08080000 +#define DEFAULT_SGI_PER 10 + +typedef PREPACK struct { + A_UINT32 rateField; /* 1 bit per rate corresponding to index */ + A_UINT8 id; + A_UINT8 shortTrys; + A_UINT8 longTrys; + A_UINT8 reserved; /* padding */ +} POSTPACK WMI_SET_RATE_POLICY_CMD; + +typedef PREPACK struct { + A_UINT8 metaVersion; /* version of meta data for rx packets <0 = default> (0-7 = valid) */ + A_UINT8 dot11Hdr; /* 1 == leave .11 header intact , 0 == replace .11 header with .3 <default> */ + A_UINT8 defragOnHost; /* 1 == defragmentation is performed by host, 0 == performed by target <default> */ + A_UINT8 reserved[1]; /* alignment */ +} POSTPACK WMI_RX_FRAME_FORMAT_CMD; + + +typedef PREPACK struct { + A_UINT8 enable; /* 1 == device operates in thin mode , 0 == normal mode <default> */ + A_UINT8 reserved[3]; +} POSTPACK WMI_SET_THIN_MODE_CMD; + +/* AP mode events */ +/* WMI_PS_POLL_EVENT */ +typedef PREPACK struct { + A_UINT16 aid; +} POSTPACK WMI_PSPOLL_EVENT; + +typedef PREPACK struct { + A_UINT32 tx_bytes; + A_UINT32 tx_pkts; + A_UINT32 tx_error; + A_UINT32 tx_discard; + A_UINT32 rx_bytes; + A_UINT32 rx_pkts; + A_UINT32 rx_error; + A_UINT32 rx_discard; + A_UINT32 aid; +} POSTPACK WMI_PER_STA_STAT; + +#define AP_GET_STATS 0 +#define AP_CLEAR_STATS 1 + +typedef PREPACK struct { + A_UINT32 action; + WMI_PER_STA_STAT sta[AP_MAX_NUM_STA+1]; +} POSTPACK WMI_AP_MODE_STAT; +#define WMI_AP_MODE_STAT_SIZE(numSta) (sizeof(A_UINT32) + ((numSta + 1) * sizeof(WMI_PER_STA_STAT))) + +#define AP_11BG_RATESET1 1 +#define AP_11BG_RATESET2 2 +#define DEF_AP_11BG_RATESET AP_11BG_RATESET1 +typedef PREPACK struct { + A_UINT8 rateset; +} POSTPACK WMI_AP_SET_11BG_RATESET_CMD; +/* + * End of AP mode definitions + */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_H_ */ diff --git a/drivers/staging/ath6kl/include/common/wmi_thin.h b/drivers/staging/ath6kl/include/common/wmi_thin.h new file mode 100644 index 000000000000..35391edd20ac --- /dev/null +++ b/drivers/staging/ath6kl/include/common/wmi_thin.h @@ -0,0 +1,347 @@ +//------------------------------------------------------------------------------ +// <copyright file="wmi_thin.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to WMI commands + * belongs to the host driver and the WM is not required to validate + * parameters for value, proper range, or any other checking. + * + */ + +#ifndef _WMI_THIN_H_ +#define _WMI_THIN_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef enum { + WMI_THIN_CONFIG_CMDID = 0x8000, // WMI_THIN_RESERVED_START + WMI_THIN_SET_MIB_CMDID, + WMI_THIN_GET_MIB_CMDID, + WMI_THIN_JOIN_CMDID, + /* add new CMDID's here */ + WMI_THIN_RESERVED_END_CMDID = 0x8fff // WMI_THIN_RESERVED_END +} WMI_THIN_COMMAND_ID; + +typedef enum{ + TEMPLATE_FRM_FIRST = 0, + TEMPLATE_FRM_PROBE_REQ =TEMPLATE_FRM_FIRST, + TEMPLATE_FRM_BEACON, + TEMPLATE_FRM_PROBE_RESP, + TEMPLATE_FRM_NULL, + TEMPLATE_FRM_QOS_NULL, + TEMPLATE_FRM_PSPOLL, + TEMPLATE_FRM_MAX +}WMI_TEMPLATE_FRM_TYPE; + +/* TEMPLATE_FRM_LEN... represent the maximum allowable + * data lengths (bytes) for each frame type */ +#define TEMPLATE_FRM_LEN_PROBE_REQ (256) /* Symbian dictates a minimum of 256 for these 3 frame types */ +#define TEMPLATE_FRM_LEN_BEACON (256) +#define TEMPLATE_FRM_LEN_PROBE_RESP (256) +#define TEMPLATE_FRM_LEN_NULL (32) +#define TEMPLATE_FRM_LEN_QOS_NULL (32) +#define TEMPLATE_FRM_LEN_PSPOLL (32) +#define TEMPLATE_FRM_LEN_SUM (TEMPLATE_FRM_LEN_PROBE_REQ + TEMPLATE_FRM_LEN_BEACON + TEMPLATE_FRM_LEN_PROBE_RESP + \ + TEMPLATE_FRM_LEN_NULL + TEMPLATE_FRM_LEN_QOS_NULL + TEMPLATE_FRM_LEN_PSPOLL) + + +/* MAC Header Build Rules */ +/* These values allow the host to configure the + * target code that is responsible for constructing + * the MAC header. In cases where the MAC header + * is provided by the host framework, the target + * has a diminished responsibility over what fields + * it must write. This will vary from framework to framework. + * Symbian requires different behavior from MAC80211 which + * requires different behavior from MS Native Wifi. */ +#define WMI_WRT_VER_TYPE 0x00000001 +#define WMI_WRT_DURATION 0x00000002 +#define WMI_WRT_DIRECTION 0x00000004 +#define WMI_WRT_POWER 0x00000008 +#define WMI_WRT_WEP 0x00000010 +#define WMI_WRT_MORE 0x00000020 +#define WMI_WRT_BSSID 0x00000040 +#define WMI_WRT_QOS 0x00000080 +#define WMI_WRT_SEQNO 0x00000100 +#define WMI_GUARD_TX 0x00000200 /* prevents TX ops that are not allowed for a current state */ +#define WMI_WRT_DEFAULT_CONFIG (WMI_WRT_VER_TYPE | WMI_WRT_DURATION | WMI_WRT_DIRECTION | \ + WMI_WRT_POWER | WMI_WRT_MORE | WMI_WRT_WEP | WMI_WRT_BSSID | \ + WMI_WRT_QOS | WMI_WRT_SEQNO | WMI_GUARD_TX) + +/* WMI_THIN_CONFIG_TXCOMPLETE -- Used to configure the params and content for + * TX Complete messages the will come from the Target. these messages are + * disabled by default but can be enabled using this structure and the + * WMI_THIN_CONFIG_CMDID. */ +typedef PREPACK struct { + A_UINT8 version; /* the versioned type of messages to use or 0 to disable */ + A_UINT8 countThreshold; /* msg count threshold triggering a tx complete message */ + A_UINT16 timeThreshold; /* timeout interval in MSEC triggering a tx complete message */ +} POSTPACK WMI_THIN_CONFIG_TXCOMPLETE; + +/* WMI_THIN_CONFIG_DECRYPT_ERR -- Used to configure behavior for received frames + * that have decryption errors. The default behavior is to discard the frame + * without notification. Alternately, the MAC Header is forwarded to the host + * with the failed status. */ +typedef PREPACK struct { + A_UINT8 enable; /* 1 == send decrypt errors to the host, 0 == don't */ + A_UINT8 reserved[3]; /* align padding */ +} POSTPACK WMI_THIN_CONFIG_DECRYPT_ERR; + +/* WMI_THIN_CONFIG_TX_MAC_RULES -- Used to configure behavior for transmitted + * frames that require partial MAC header construction. These rules + * are used by the target to indicate which fields need to be written. */ +typedef PREPACK struct { + A_UINT32 rules; /* combination of WMI_WRT_... values */ +} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES; + +/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received + * frames as to which frames should get forwarded to the host and which + * should get processed internally. */ +typedef PREPACK struct { + A_UINT32 rules; /* combination of WMI_FILT_... values */ +} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES; + +/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above + * WMI_THIN_CONFIG_... structures. The actual combination is indicated + * by the value of cfgField. Each bit in this field corresponds to + * one of the above structures. */ +typedef PREPACK struct { +#define WMI_THIN_CFG_TXCOMP 0x00000001 +#define WMI_THIN_CFG_DECRYPT 0x00000002 +#define WMI_THIN_CFG_MAC_RULES 0x00000004 +#define WMI_THIN_CFG_FILTER_RULES 0x00000008 + A_UINT32 cfgField; /* combination of WMI_THIN_CFG_... describes contents of config command */ + A_UINT16 length; /* length in bytes of appended sub-commands */ + A_UINT8 reserved[2]; /* align padding */ +} POSTPACK WMI_THIN_CONFIG_CMD; + +/* MIB Access Identifiers tailored for Symbian. */ +enum { + MIB_ID_STA_MAC = 1, // [READONLY] + MIB_ID_RX_LIFE_TIME, // [NOT IMPLEMENTED] + MIB_ID_SLOT_TIME, // [READ/WRITE] + MIB_ID_RTS_THRESHOLD, // [READ/WRITE] + MIB_ID_CTS_TO_SELF, // [READ/WRITE] + MIB_ID_TEMPLATE_FRAME, // [WRITE ONLY] + MIB_ID_RXFRAME_FILTER, // [READ/WRITE] + MIB_ID_BEACON_FILTER_TABLE, // [WRITE ONLY] + MIB_ID_BEACON_FILTER, // [READ/WRITE] + MIB_ID_BEACON_LOST_COUNT, // [WRITE ONLY] + MIB_ID_RSSI_THRESHOLD, // [WRITE ONLY] + MIB_ID_HT_CAP, // [NOT IMPLEMENTED] + MIB_ID_HT_OP, // [NOT IMPLEMENTED] + MIB_ID_HT_2ND_BEACON, // [NOT IMPLEMENTED] + MIB_ID_HT_BLOCK_ACK, // [NOT IMPLEMENTED] + MIB_ID_PREAMBLE, // [READ/WRITE] + /*MIB_ID_GROUP_ADDR_TABLE,*/ + /*MIB_ID_WEP_DEFAULT_KEY_ID */ + /*MIB_ID_TX_POWER */ + /*MIB_ID_ARP_IP_TABLE */ + /*MIB_ID_SLEEP_MODE */ + /*MIB_ID_WAKE_INTERVAL*/ + /*MIB_ID_STAT_TABLE*/ + /*MIB_ID_IBSS_PWR_SAVE*/ + /*MIB_ID_COUNTERS_TABLE*/ + /*MIB_ID_ETHERTYPE_FILTER*/ + /*MIB_ID_BC_UDP_FILTER*/ + +}; + +typedef PREPACK struct { + A_UINT8 addr[ATH_MAC_LEN]; +} POSTPACK WMI_THIN_MIB_STA_MAC; + +typedef PREPACK struct { + A_UINT32 time; // units == msec +} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME; + +typedef PREPACK struct { + A_UINT8 enable; //1 = on, 0 = off +} POSTPACK WMI_THIN_MIB_CTS_TO_SELF; + +typedef PREPACK struct { + A_UINT32 time; // units == usec +} POSTPACK WMI_THIN_MIB_SLOT_TIME; + +typedef PREPACK struct { + A_UINT16 length; //units == bytes +} POSTPACK WMI_THIN_MIB_RTS_THRESHOLD; + +typedef PREPACK struct { + A_UINT8 type; // type of frame + A_UINT8 rate; // tx rate to be used (one of WMI_BIT_RATE) + A_UINT16 length; // num bytes following this structure as the template data +} POSTPACK WMI_THIN_MIB_TEMPLATE_FRAME; + +typedef PREPACK struct { +#define FRAME_FILTER_PROMISCUOUS 0x00000001 +#define FRAME_FILTER_BSSID 0x00000002 + A_UINT32 filterMask; +} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER; + + +#define IE_FILTER_TREATMENT_CHANGE 1 +#define IE_FILTER_TREATMENT_APPEAR 2 + +typedef PREPACK struct { + A_UINT8 ie; + A_UINT8 treatment; +} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE; + +typedef PREPACK struct { + A_UINT8 ie; + A_UINT8 treatment; + A_UINT8 oui[3]; + A_UINT8 type; + A_UINT16 version; +} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_OUI; + +typedef PREPACK struct { + A_UINT16 numElements; + A_UINT8 entrySize; // sizeof(WMI_THIN_MIB_BEACON_FILTER_TABLE) on host cpu may be 2 may be 4 + A_UINT8 reserved; +} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER; + +typedef PREPACK struct { + A_UINT32 count; /* num beacons between deliveries */ + A_UINT8 enable; + A_UINT8 reserved[3]; +} POSTPACK WMI_THIN_MIB_BEACON_FILTER; + +typedef PREPACK struct { + A_UINT32 count; /* num consec lost beacons after which send event */ +} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT; + +typedef PREPACK struct { + A_UINT8 rssi; /* the low threshold which can trigger an event warning */ + A_UINT8 tolerance; /* the range above and below the threshold to prevent event flooding to the host. */ + A_UINT8 count; /* the sample count of consecutive frames necessary to trigger an event. */ + A_UINT8 reserved[1]; /* padding */ +} POSTPACK WMI_THIN_MIB_RSSI_THRESHOLD; + + +typedef PREPACK struct { + A_UINT32 cap; + A_UINT32 rxRateField; + A_UINT32 beamForming; + A_UINT8 addr[ATH_MAC_LEN]; + A_UINT8 enable; + A_UINT8 stbc; + A_UINT8 maxAMPDU; + A_UINT8 msduSpacing; + A_UINT8 mcsFeedback; + A_UINT8 antennaSelCap; +} POSTPACK WMI_THIN_MIB_HT_CAP; + +typedef PREPACK struct { + A_UINT32 infoField; + A_UINT32 basicRateField; + A_UINT8 protection; + A_UINT8 secondChanneloffset; + A_UINT8 channelWidth; + A_UINT8 reserved; +} POSTPACK WMI_THIN_MIB_HT_OP; + +typedef PREPACK struct { +#define SECOND_BEACON_PRIMARY 1 +#define SECOND_BEACON_EITHER 2 +#define SECOND_BEACON_SECONDARY 3 + A_UINT8 cfg; + A_UINT8 reserved[3]; /* padding */ +} POSTPACK WMI_THIN_MIB_HT_2ND_BEACON; + +typedef PREPACK struct { + A_UINT8 txTIDField; + A_UINT8 rxTIDField; + A_UINT8 reserved[2]; /* padding */ +} POSTPACK WMI_THIN_MIB_HT_BLOCK_ACK; + +typedef PREPACK struct { + A_UINT8 enableLong; // 1 == long preamble, 0 == short preamble + A_UINT8 reserved[3]; +} POSTPACK WMI_THIN_MIB_PREAMBLE; + +typedef PREPACK struct { + A_UINT16 length; /* the length in bytes of the appended MIB data */ + A_UINT8 mibID; /* the ID of the MIB element being set */ + A_UINT8 reserved; /* align padding */ +} POSTPACK WMI_THIN_SET_MIB_CMD; + +typedef PREPACK struct { + A_UINT8 mibID; /* the ID of the MIB element being set */ + A_UINT8 reserved[3]; /* align padding */ +} POSTPACK WMI_THIN_GET_MIB_CMD; + +typedef PREPACK struct { + A_UINT32 basicRateMask; /* bit mask of basic rates */ + A_UINT32 beaconIntval; /* TUs */ + A_UINT16 atimWindow; /* TUs */ + A_UINT16 channel; /* frequency in Mhz */ + A_UINT8 networkType; /* INFRA_NETWORK | ADHOC_NETWORK */ + A_UINT8 ssidLength; /* 0 - 32 */ + A_UINT8 probe; /* != 0 : issue probe req at start */ + A_UINT8 reserved; /* alignment */ + A_UCHAR ssid[WMI_MAX_SSID_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_THIN_JOIN_CMD; + +typedef PREPACK struct { + A_UINT16 dtim; /* dtim interval in num beacons */ + A_UINT16 aid; /* 80211 AID from Assoc resp */ +} POSTPACK WMI_THIN_POST_ASSOC_CMD; + +typedef enum { + WMI_THIN_EVENTID_RESERVED_START = 0x8000, + WMI_THIN_GET_MIB_EVENTID, + WMI_THIN_JOIN_EVENTID, + + /* Add new THIN EVENTID's here */ + WMI_THIN_EVENTID_RESERVED_END = 0x8fff +} WMI_THIN_EVENT_ID; + +/* Possible values for WMI_THIN_JOIN_EVENT.result */ +typedef enum { + WMI_THIN_JOIN_RES_SUCCESS = 0, // device has joined the network + WMI_THIN_JOIN_RES_FAIL, // device failed for unspecified reason + WMI_THIN_JOIN_RES_TIMEOUT, // device failed due to no beacon rx in time limit + WMI_THIN_JOIN_RES_BAD_PARAM, // device failed due to bad cmd param. +}WMI_THIN_JOIN_RESULT; + +typedef PREPACK struct { + A_UINT8 result; /* the result of the join cmd. one of WMI_THIN_JOIN_RESULT */ + A_UINT8 reserved[3]; /* alignment */ +} POSTPACK WMI_THIN_JOIN_EVENT; + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_THIN_H_ */ diff --git a/drivers/staging/ath6kl/include/common/wmix.h b/drivers/staging/ath6kl/include/common/wmix.h new file mode 100644 index 000000000000..87046e364bae --- /dev/null +++ b/drivers/staging/ath6kl/include/common/wmix.h @@ -0,0 +1,279 @@ +//------------------------------------------------------------------------------ +// <copyright file="wmix.h" company="Atheros"> +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains extensions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all + * extended commands and events. Extensions include useful commands + * that are not directly related to wireless activities. They may + * be hardware-specific, and they might not be supported on all + * implementations. + * + * Extended WMIX commands are encapsulated in a WMI message with + * cmd=WMI_EXTENSION_CMD. + */ + +#ifndef _WMIX_H_ +#define _WMIX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "dbglog.h" + +/* + * Extended WMI commands are those that are needed during wireless + * operation, but which are not really wireless commands. This allows, + * for instance, platform-specific commands. Extended WMI commands are + * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID. + * Extended WMI events are similarly embedded in a WMI event message with + * WMI_EVENT_ID=WMI_EXTENSION_EVENTID. + */ +typedef PREPACK struct { + A_UINT32 commandId; +} POSTPACK WMIX_CMD_HDR; + +typedef enum { + WMIX_DSETOPEN_REPLY_CMDID = 0x2001, + WMIX_DSETDATA_REPLY_CMDID, + WMIX_GPIO_OUTPUT_SET_CMDID, + WMIX_GPIO_INPUT_GET_CMDID, + WMIX_GPIO_REGISTER_SET_CMDID, + WMIX_GPIO_REGISTER_GET_CMDID, + WMIX_GPIO_INTR_ACK_CMDID, + WMIX_HB_CHALLENGE_RESP_CMDID, + WMIX_DBGLOG_CFG_MODULE_CMDID, + WMIX_PROF_CFG_CMDID, /* 0x200a */ + WMIX_PROF_ADDR_SET_CMDID, + WMIX_PROF_START_CMDID, + WMIX_PROF_STOP_CMDID, + WMIX_PROF_COUNT_GET_CMDID, +} WMIX_COMMAND_ID; + +typedef enum { + WMIX_DSETOPENREQ_EVENTID = 0x3001, + WMIX_DSETCLOSE_EVENTID, + WMIX_DSETDATAREQ_EVENTID, + WMIX_GPIO_INTR_EVENTID, + WMIX_GPIO_DATA_EVENTID, + WMIX_GPIO_ACK_EVENTID, + WMIX_HB_CHALLENGE_RESP_EVENTID, + WMIX_DBGLOG_EVENTID, + WMIX_PROF_COUNT_EVENTID, +} WMIX_EVENT_ID; + +/* + * =============DataSet support================= + */ + +/* + * WMIX_DSETOPENREQ_EVENTID + * DataSet Open Request Event + */ +typedef PREPACK struct { + A_UINT32 dset_id; + A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETOPENREQ_EVENT; + +/* + * WMIX_DSETCLOSE_EVENTID + * DataSet Close Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; +} POSTPACK WMIX_DSETCLOSE_EVENT; + +/* + * WMIX_DSETDATAREQ_EVENTID + * DataSet Data Request Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; + A_UINT32 offset; + A_UINT32 length; + A_UINT32 targ_buf; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETDATAREQ_EVENT; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_dset_handle; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 access_cookie; + A_UINT32 size; + A_UINT32 version; +} POSTPACK WMIX_DSETOPEN_REPLY_CMD; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_buf; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 length; + A_UINT8 buf[1]; +} POSTPACK WMIX_DSETDATA_REPLY_CMD; + + +/* + * =============GPIO support================= + * All masks are 18-bit masks with bit N operating on GPIO pin N. + */ + +#include "gpio.h" + +/* + * Set GPIO pin output state. + * In order for output to be driven, a pin must be enabled for output. + * This can be done during initialization through the GPIO Configuration + * DataSet, or during operation with the enable_mask. + * + * If a request is made to simultaneously set/clear or set/disable or + * clear/disable or disable/enable, results are undefined. + */ +typedef PREPACK struct { + A_UINT32 set_mask; /* pins to set */ + A_UINT32 clear_mask; /* pins to clear */ + A_UINT32 enable_mask; /* pins to enable for output */ + A_UINT32 disable_mask; /* pins to disable/tristate */ +} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD; + +/* + * Set a GPIO register. For debug/exceptional cases. + * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a + * platform-dependent header. + */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register ID */ + A_UINT32 value; /* value to write */ +} POSTPACK WMIX_GPIO_REGISTER_SET_CMD; + +/* Get a GPIO register. For debug/exceptional cases. */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register to read */ +} POSTPACK WMIX_GPIO_REGISTER_GET_CMD; + +/* + * Host acknowledges and re-arms GPIO interrupts. A single + * message should be used to acknowledge all interrupts that + * were delivered in an earlier WMIX_GPIO_INTR_EVENT message. + */ +typedef PREPACK struct { + A_UINT32 ack_mask; /* interrupts to acknowledge */ +} POSTPACK WMIX_GPIO_INTR_ACK_CMD; + +/* + * Target informs Host of GPIO interrupts that have ocurred since the + * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information -- + * the current GPIO input values is provided -- in order to support + * use of a GPIO interrupt as a Data Valid signal for other GPIO pins. + */ +typedef PREPACK struct { + A_UINT32 intr_mask; /* pending GPIO interrupts */ + A_UINT32 input_values; /* recent GPIO input values */ +} POSTPACK WMIX_GPIO_INTR_EVENT; + +/* + * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the mask of GPIO pin inputs and + * reg_id set to GPIO_ID_NONE + * + * + * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the value of the requested register and + * reg_id identifying the register (reflects the original request) + * NB: reg_id supports the future possibility of unsolicited + * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may + * simplify Host GPIO support. + */ +typedef PREPACK struct { + A_UINT32 value; + A_UINT32 reg_id; +} POSTPACK WMIX_GPIO_DATA_EVENT; + +/* + * =============Error Detection support================= + */ + +/* + * WMIX_HB_CHALLENGE_RESP_CMDID + * Heartbeat Challenge Response command + */ +typedef PREPACK struct { + A_UINT32 cookie; + A_UINT32 source; +} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD; + +/* + * WMIX_HB_CHALLENGE_RESP_EVENTID + * Heartbeat Challenge Response Event + */ +#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD + +typedef PREPACK struct { + struct dbglog_config_s config; +} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD; + +/* + * =============Target Profiling support================= + */ + +typedef PREPACK struct { + A_UINT32 period; /* Time (in 30.5us ticks) between samples */ + A_UINT32 nbins; +} POSTPACK WMIX_PROF_CFG_CMD; + +typedef PREPACK struct { + A_UINT32 addr; +} POSTPACK WMIX_PROF_ADDR_SET_CMD; + +/* + * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request + * using a WMIX_PROF_COUNT_EVENT with + * addr set to the next address + * count set to the corresponding count + */ +typedef PREPACK struct { + A_UINT32 addr; + A_UINT32 count; +} POSTPACK WMIX_PROF_COUNT_EVENT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMIX_H_ */ |