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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2017-09-01 09:36:35 -0400
committerMauro Carvalho Chehab <mchehab@s-opensource.com>2017-09-23 15:03:53 -0400
commit90154e130f45f4fcad595058cc2d34ce412bec33 (patch)
treea8ef3b86a1b20e38461c67d186c5b4efb337ce9b /drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h
parent5fc90b632ea9a107ed6b71eb7058bb58e1b5493b (diff)
media: staging: atomisp: Don't override D3 delay settings here
The d3_delay parameter is set by arch/x86/pci/intel_mid_pci.c and drivers/pci/quirks.c. No need to override that settings in unrelated driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Diffstat (limited to 'drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h')
-rw-r--r--drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h b/drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h
index b7c079f3630a..0d7f5c618b56 100644
--- a/drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h
+++ b/drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h
@@ -18,14 +18,6 @@
#define PCI_ROOT_MSGBUS_WRITE 0x11
#define PCI_ROOT_MSGBUS_DWORD_ENABLE 0xf0
-/* In BYT platform for all internal PCI devices d3 delay
- * of 3 ms is sufficient. Default value of 10 ms is overkill.
- */
-#define INTERNAL_PCI_PM_D3_WAIT 3
-
-#define ISP_SUB_CLASS 0x80
-#define SUB_CLASS_MASK 0xFF00
-
u32 intel_mid_msgbus_read32_raw(u32 cmd);
u32 intel_mid_msgbus_read32(u8 port, u32 addr);
void intel_mid_msgbus_write32_raw(u32 cmd, u32 data);