diff options
| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2021-06-07 14:01:51 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-06-09 14:19:22 +0200 |
| commit | cf37f42997a10da6e07d5404fbf4b537d9be32ec (patch) | |
| tree | 159f0c3544bb2d96ae6e6233e5a745b68b55aae2 /drivers/staging/mt7621-dts | |
| parent | 860bce4565b665adb889e61fb6d8227d99753a00 (diff) | |
staging: mt7621-dts: move some properties into root port child nodes
After a review of the bindings 'clocks', 'resets' and 'phys' must
be moved into root port child nodes. Hence, move all of them.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210607120153.24989-5-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-dts')
| -rw-r--r-- | drivers/staging/mt7621-dts/mt7621.dtsi | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 840ba0c3ffed..ecfe2f2cf75a 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -500,15 +500,6 @@ status = "disabled"; - resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>; - reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&sysc MT7621_CLK_PCIE0>, - <&sysc MT7621_CLK_PCIE1>, - <&sysc MT7621_CLK_PCIE2>; - clock-names = "pcie0", "pcie1", "pcie2"; - phys = <&pcie0_phy 1>, <&pcie2_phy 0>; - phy-names = "pcie-phy0", "pcie-phy2"; - reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; pcie@0,0 { @@ -519,6 +510,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 24>; + clocks = <&sysc MT7621_CLK_PCIE0>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy0"; ranges; }; @@ -530,6 +525,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 25>; + clocks = <&sysc MT7621_CLK_PCIE1>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy1"; ranges; }; @@ -541,6 +540,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 26>; + clocks = <&sysc MT7621_CLK_PCIE2>; + phys = <&pcie2_phy 0>; + phy-names = "pcie-phy2"; ranges; }; }; |