diff options
| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2020-03-13 21:09:10 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-03-17 12:53:07 +0100 |
| commit | f2bf082204608abf408a466d7cadc2561b7291a8 (patch) | |
| tree | d5d63cef9d835c55488cc75c0b2e62e18bf2e994 /drivers/staging/mt7621-dts | |
| parent | 475fe234bdfd4d7a9004b79f4f37fc5b47de51ed (diff) | |
staging: mt7621-dts: make use of 'reset-gpios' property for pci
Properly set pins for group pcie as 'gpio' function and declare
gpio's in the pci node to make reset stuff properly functional.
Delete no more needed general reset and previous pers gpio which
is now being used in 'reset-gpios' property.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20200313200913.24321-4-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-dts')
| -rw-r--r-- | drivers/staging/mt7621-dts/mt7621.dtsi | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index d89d68ffa7bc..488474153535 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -286,7 +286,7 @@ pcie_pins: pcie0 { pcie0 { groups = "pcie"; - function = "pcie rst"; + function = "gpio"; }; }; @@ -512,7 +512,6 @@ #address-cells = <3>; #size-cells = <2>; - perst-gpio = <&gpio 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; @@ -532,13 +531,17 @@ status = "disabled"; - resets = <&rstctrl 23 &rstctrl 24 &rstctrl 25 &rstctrl 26>; - reset-names = "pcie", "pcie0", "pcie1", "pcie2"; + resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; + reset-names = "pcie0", "pcie1", "pcie2"; clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; clock-names = "pcie0", "pcie1", "pcie2"; phys = <&pcie0_phy 0>, <&pcie0_phy 1>, <&pcie1_phy 0>; phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>, + <&gpio 8 GPIO_ACTIVE_LOW>, + <&gpio 7 GPIO_ACTIVE_LOW>; + pcie@0,0 { reg = <0x0000 0 0 0 0>; #address-cells = <3>; |