diff options
| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2018-11-04 11:49:58 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-11-11 11:36:16 -0800 |
| commit | b8d97d43bf7a4c1746ecdfa674c3e6ef5c73c11e (patch) | |
| tree | d5505ae473efaac56a0b1e7a18a62723287d6495 /drivers/staging/mt7621-pci | |
| parent | 802a2f7b2fe36b06681f80a54a3eba167a8e500e (diff) | |
staging: mt7621-pci: move some code into 'mt7621_pcie_init_ports'
Some clocks bits related code is in driver probe function and can
perfectly be moved into 'mt7621_pcie_init_ports' function which is
a more accurate place for it.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index a069d7f5d8d9..fb9aa6bbd5dc 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -626,6 +626,14 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) list_del(&port->list); } } + + rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); + rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); + rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN); + rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1); + rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN); + mdelay(50); + rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL); } static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port) @@ -833,16 +841,6 @@ static int mt7621_pci_probe(struct platform_device *pdev) mt7621_pcie_init_ports(pcie); - rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); - rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); - - rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN); - rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1); - rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN); - - mdelay(50); - rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL); - err = mt7621_pcie_init_virtual_bridges(pcie); if (err) { dev_err(dev, "Nothing is connected in virtual bridges. Exiting..."); |