diff options
| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2018-11-29 19:39:55 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-12-05 09:39:45 +0100 |
| commit | 8cfb722bd55ab3879486001797741e879fbc7095 (patch) | |
| tree | 38b6d7043083d12c1481a3264e3d2008059bd515 /drivers/staging/mt7621-pci | |
| parent | f9bb84090777dfee2586aef55d61e2c976ef31bc (diff) | |
staging: mt7621-pci: add comment clarifying inverted reset lines
To avoid people reading this code being very confused, add a comment
clarifying the need for invert resets on some chip revisions.
Suggested-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index c5e33fbdf225..31310b6fb7db 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -589,6 +589,10 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port) u32 slot = port->slot; u32 val = 0; + /* + * Any MT7621 Ralink pcie controller that doesn't have 0x0101 at + * the end of the chip_id has inverted PCI resets. + */ mt7621_reset_port(port); val = read_config(pcie, slot, PCIE_FTS_NUM); |