diff options
| author | Simon Sandström <simon@nikanor.nu> | 2017-12-07 22:15:02 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-12-08 16:34:50 +0100 |
| commit | 9b65e91010b569dc3661a7e67ef0f499518c59ff (patch) | |
| tree | e4422dac91188f5cea664bc454671a5bccfc89fe /drivers/staging/pi433 | |
| parent | 02dd7bc27ae97e8cb8f4df84f9a9068116cfb50e (diff) | |
staging: pi433: Add spaces around & and + operator
Fixes checkpatch warning: "spaces preferred around that '&'".
Signed-off-by: Simon Sandström <simon@nikanor.nu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/pi433')
| -rw-r--r-- | drivers/staging/pi433/rf69.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/drivers/staging/pi433/rf69.c b/drivers/staging/pi433/rf69.c index 5ec225024fe6..70827034f5d0 100644 --- a/drivers/staging/pi433/rf69.c +++ b/drivers/staging/pi433/rf69.c @@ -82,7 +82,6 @@ int rf69_set_mode(struct spi_device *spi, enum mode mode) // we are using packet mode, so this check is not really needed // but waiting for mode ready is necessary when going from sleep because the FIFO may not be immediately available from previous mode //while (_mode == RF69_MODE_SLEEP && (READ_REG(REG_IRQFLAGS1) & RF_IRQFLAGS1_MODEREADY) == 0x00); // Wait for ModeReady - } int rf69_set_data_mode(struct spi_device *spi, u8 data_mode) @@ -173,8 +172,8 @@ int rf69_set_bit_rate(struct spi_device *spi, u16 bitRate) // calculate reg settings bitRate_reg = (F_OSC / bitRate); - msb = (bitRate_reg&0xff00) >> 8; - lsb = (bitRate_reg&0xff); + msb = (bitRate_reg & 0xff00) >> 8; + lsb = (bitRate_reg & 0xff); // transmit to RF 69 retval = rf69_write_reg(spi, REG_BITRATE_MSB, msb); @@ -214,8 +213,8 @@ int rf69_set_deviation(struct spi_device *spi, u32 deviation) f_reg = deviation * factor; do_div(f_reg, f_step); - msb = (f_reg&0xff00) >> 8; - lsb = (f_reg&0xff); + msb = (f_reg & 0xff00) >> 8; + lsb = (f_reg & 0xff); // check msb if (msb & ~FDEVMASB_MASK) { @@ -264,9 +263,9 @@ int rf69_set_frequency(struct spi_device *spi, u32 frequency) f_reg = frequency * factor; do_div(f_reg, f_step); - msb = (f_reg&0xff0000) >> 16; - mid = (f_reg&0xff00) >> 8; - lsb = (f_reg&0xff); + msb = (f_reg & 0xff0000) >> 16; + mid = (f_reg & 0xff00) >> 8; + lsb = (f_reg & 0xff); // write to chip retval = rf69_write_reg(spi, REG_FRF_MSB, msb); @@ -686,8 +685,8 @@ int rf69_set_preamble_length(struct spi_device *spi, u16 preambleLength) /* no value check needed - u16 exactly matches register size */ /* calculate reg settings */ - msb = (preambleLength&0xff00) >> 8; - lsb = (preambleLength&0xff); + msb = (preambleLength & 0xff00) >> 8; + lsb = (preambleLength & 0xff); /* transmit to chip */ retval = rf69_write_reg(spi, REG_PREAMBLE_MSB, msb); @@ -931,14 +930,14 @@ int rf69_read_fifo (struct spi_device *spi, u8 *buffer, unsigned int size) memset(&transfer, 0, sizeof(transfer)); transfer.tx_buf = local_buffer; transfer.rx_buf = local_buffer; - transfer.len = size+1; + transfer.len = size + 1; retval = spi_sync_transfer(spi, &transfer, 1); - #ifdef DEBUG_FIFO_ACCESS - for (i = 0; i < size; i++) - dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i+1]); - #endif +#ifdef DEBUG_FIFO_ACCESS + for (i = 0; i < size; i++) + dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i + 1]); +#endif memcpy(buffer, &local_buffer[1], size); |