diff options
| author | Mike Rapoport <mike.rapoport@gmail.com> | 2016-02-10 18:34:04 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-02-11 19:52:37 -0800 |
| commit | 85e4db5347a96560928d2995a2cd05f10b856d5e (patch) | |
| tree | a1111daebcfde881a288b6622d9512a8efb21bc3 /drivers/staging/sm750fb/ddk750_reg.h | |
| parent | 7755265a9993b836f544aacc7b6a2a474fbde558 (diff) | |
staging: sm750fb: share common bits in display control registers
The display control registers for primary and secondary display share some
of the bits and those bits can be defined in a single place and then used
for manipulations of the relevant registers.
Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/sm750fb/ddk750_reg.h')
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_reg.h | 63 |
1 files changed, 18 insertions, 45 deletions
diff --git a/drivers/staging/sm750fb/ddk750_reg.h b/drivers/staging/sm750fb/ddk750_reg.h index d1e7fc4d50df..4d66f6127207 100644 --- a/drivers/staging/sm750fb/ddk750_reg.h +++ b/drivers/staging/sm750fb/ddk750_reg.h @@ -825,15 +825,15 @@ #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK 15:15 #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0 #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1 -#define PANEL_DISPLAY_CTRL_CLOCK_PHASE 14:14 -#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 -#define PANEL_DISPLAY_CTRL_VSYNC_PHASE 13:13 -#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 -#define PANEL_DISPLAY_CTRL_HSYNC_PHASE 12:12 -#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 +#define DISPLAY_CTRL_CLOCK_PHASE 14:14 +#define DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 +#define DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 +#define DISPLAY_CTRL_VSYNC_PHASE 13:13 +#define DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 +#define DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 +#define DISPLAY_CTRL_HSYNC_PHASE 12:12 +#define DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 +#define DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 #define PANEL_DISPLAY_CTRL_VSYNC 11:11 #define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_HIGH 0 #define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_LOW 1 @@ -843,9 +843,9 @@ #define PANEL_DISPLAY_CTRL_COLOR_KEY 9:9 #define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE 0 #define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE 1 -#define PANEL_DISPLAY_CTRL_TIMING 8:8 -#define PANEL_DISPLAY_CTRL_TIMING_DISABLE 0 -#define PANEL_DISPLAY_CTRL_TIMING_ENABLE 1 +#define DISPLAY_CTRL_TIMING 8:8 +#define DISPLAY_CTRL_TIMING_DISABLE 0 +#define DISPLAY_CTRL_TIMING_ENABLE 1 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR 7:7 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN 0 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP 1 @@ -858,12 +858,12 @@ #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN 4:4 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE 0 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE 1 -#define PANEL_DISPLAY_CTRL_GAMMA 3:3 -#define PANEL_DISPLAY_CTRL_GAMMA_DISABLE 0 -#define PANEL_DISPLAY_CTRL_GAMMA_ENABLE 1 -#define PANEL_DISPLAY_CTRL_PLANE 2:2 -#define PANEL_DISPLAY_CTRL_PLANE_DISABLE 0 -#define PANEL_DISPLAY_CTRL_PLANE_ENABLE 1 +#define DISPLAY_CTRL_GAMMA 3:3 +#define DISPLAY_CTRL_GAMMA_DISABLE 0 +#define DISPLAY_CTRL_GAMMA_ENABLE 1 +#define DISPLAY_CTRL_PLANE 2:2 +#define DISPLAY_CTRL_PLANE_DISABLE 0 +#define DISPLAY_CTRL_PLANE_ENABLE 1 #define PANEL_DISPLAY_CTRL_FORMAT 1:0 #define PANEL_DISPLAY_CTRL_FORMAT_8 0 #define PANEL_DISPLAY_CTRL_FORMAT_16 1 @@ -966,9 +966,6 @@ #define VIDEO_DISPLAY_CTRL_GAMMA 3:3 #define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE 0 #define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE 1 -#define VIDEO_DISPLAY_CTRL_PLANE 2:2 -#define VIDEO_DISPLAY_CTRL_PLANE_DISABLE 0 -#define VIDEO_DISPLAY_CTRL_PLANE_ENABLE 1 #define VIDEO_DISPLAY_CTRL_FORMAT 1:0 #define VIDEO_DISPLAY_CTRL_FORMAT_8 0 #define VIDEO_DISPLAY_CTRL_FORMAT_16 1 @@ -1065,9 +1062,6 @@ #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 -#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE 2:2 -#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0 -#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT 1:0 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 1 @@ -1258,9 +1252,6 @@ #define ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 -#define ALPHA_DISPLAY_CTRL_PLANE 2:2 -#define ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0 -#define ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1 #define ALPHA_DISPLAY_CTRL_FORMAT 1:0 #define ALPHA_DISPLAY_CTRL_FORMAT_16 1 #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2 @@ -1448,28 +1439,10 @@ #define CRT_DISPLAY_CTRL_FIFO_3 1 #define CRT_DISPLAY_CTRL_FIFO_7 2 #define CRT_DISPLAY_CTRL_FIFO_11 3 -#define CRT_DISPLAY_CTRL_CLOCK_PHASE 14:14 -#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 -#define CRT_DISPLAY_CTRL_VSYNC_PHASE 13:13 -#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 -#define CRT_DISPLAY_CTRL_HSYNC_PHASE 12:12 -#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 #define CRT_DISPLAY_CTRL_BLANK 10:10 #define CRT_DISPLAY_CTRL_BLANK_OFF 0 #define CRT_DISPLAY_CTRL_BLANK_ON 1 -#define CRT_DISPLAY_CTRL_TIMING 8:8 -#define CRT_DISPLAY_CTRL_TIMING_DISABLE 0 -#define CRT_DISPLAY_CTRL_TIMING_ENABLE 1 #define CRT_DISPLAY_CTRL_PIXEL 7:4 -#define CRT_DISPLAY_CTRL_GAMMA 3:3 -#define CRT_DISPLAY_CTRL_GAMMA_DISABLE 0 -#define CRT_DISPLAY_CTRL_GAMMA_ENABLE 1 -#define CRT_DISPLAY_CTRL_PLANE 2:2 -#define CRT_DISPLAY_CTRL_PLANE_DISABLE 0 -#define CRT_DISPLAY_CTRL_PLANE_ENABLE 1 #define CRT_DISPLAY_CTRL_FORMAT 1:0 #define CRT_DISPLAY_CTRL_FORMAT_8 0 #define CRT_DISPLAY_CTRL_FORMAT_16 1 |