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authorGil Fine <gil.fine@intel.com>2021-12-17 03:16:41 +0200
committerMika Westerberg <mika.westerberg@linux.intel.com>2021-12-22 17:13:14 +0300
commit23ccd21ccb56fbfd32cb9016dcb1ccb08c662396 (patch)
tree608d48ed5ac4b3e4c616903a7f632c198db86270 /drivers/thunderbolt/tmu.c
parent1639664fb74f30eaf82231fccbcf4e34a6e71f7f (diff)
thunderbolt: Implement TMU time disruption for Intel Titan Ridge
Intel Titan Ridge based routers have slightly different flow for time disruption than USB4 compliant routers. This makes it work on Titan Ridge too. Needed to enable link low power states on Titan Ridge. Signed-off-by: Gil Fine <gil.fine@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt/tmu.c')
-rw-r--r--drivers/thunderbolt/tmu.c20
1 files changed, 13 insertions, 7 deletions
diff --git a/drivers/thunderbolt/tmu.c b/drivers/thunderbolt/tmu.c
index 37048dab5b56..8392d1352c98 100644
--- a/drivers/thunderbolt/tmu.c
+++ b/drivers/thunderbolt/tmu.c
@@ -152,21 +152,27 @@ static int tb_port_tmu_time_sync_enable(struct tb_port *port)
static int tb_switch_tmu_set_time_disruption(struct tb_switch *sw, bool set)
{
+ u32 val, offset, bit;
int ret;
- u32 val;
- ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
- sw->tmu.cap + TMU_RTR_CS_0, 1);
+ if (tb_switch_is_usb4(sw)) {
+ offset = sw->tmu.cap + TMU_RTR_CS_0;
+ bit = TMU_RTR_CS_0_TD;
+ } else {
+ offset = sw->cap_vsec_tmu + TB_TIME_VSEC_3_CS_26;
+ bit = TB_TIME_VSEC_3_CS_26_TD;
+ }
+
+ ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
if (ret)
return ret;
if (set)
- val |= TMU_RTR_CS_0_TD;
+ val |= bit;
else
- val &= ~TMU_RTR_CS_0_TD;
+ val &= ~bit;
- return tb_sw_write(sw, &val, TB_CFG_SWITCH,
- sw->tmu.cap + TMU_RTR_CS_0, 1);
+ return tb_sw_write(sw, &val, TB_CFG_SWITCH, offset, 1);
}
/**