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authorMika Westerberg <mika.westerberg@linux.intel.com>2021-10-27 13:29:09 +0300
committerMika Westerberg <mika.westerberg@linux.intel.com>2022-02-02 13:56:38 +0300
commit3eddfc121f90e174253031594b354e5764f8a318 (patch)
treed3f74e32190c4ca72a8fd88075c186c110a764ce /drivers/thunderbolt
parent97486e981ffb865f8845af3c24d5fb19f1ea37e8 (diff)
thunderbolt: Disable LTTPR on Intel Titan Ridge
Intel Titan Ridge does not disable AUX timers when it gets SET_CONFIG with SET_LTTPR_MODE set which makes DP tunneling to fail. For this reason disable LTTPR on Titan Ridge device side. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt')
-rw-r--r--drivers/thunderbolt/tb_regs.h1
-rw-r--r--drivers/thunderbolt/tunnel.c10
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h
index a74f4878d3e7..9693a6ec5950 100644
--- a/drivers/thunderbolt/tb_regs.h
+++ b/drivers/thunderbolt/tb_regs.h
@@ -389,6 +389,7 @@ struct tb_regs_port_header {
#define DP_COMMON_CAP_1_LANE 0x0
#define DP_COMMON_CAP_2_LANES 0x1
#define DP_COMMON_CAP_4_LANES 0x2
+#define DP_COMMON_CAP_LTTPR_NS BIT(27)
#define DP_COMMON_CAP_DPRX_DONE BIT(31)
/* PCIe adapter registers */
diff --git a/drivers/thunderbolt/tunnel.c b/drivers/thunderbolt/tunnel.c
index a473cc7d9a8d..118742ec93ed 100644
--- a/drivers/thunderbolt/tunnel.c
+++ b/drivers/thunderbolt/tunnel.c
@@ -580,6 +580,16 @@ static int tb_dp_xchg_caps(struct tb_tunnel *tunnel)
out_dp_cap = tb_dp_cap_set_lanes(out_dp_cap, new_lanes);
}
+ /*
+ * Titan Ridge does not disable AUX timers when it gets
+ * SET_CONFIG with SET_LTTPR_MODE set. This causes problems with
+ * DP tunneling.
+ */
+ if (tb_route(out->sw) && tb_switch_is_titan_ridge(out->sw)) {
+ out_dp_cap |= DP_COMMON_CAP_LTTPR_NS;
+ tb_port_dbg(out, "disabling LTTPR\n");
+ }
+
return tb_port_write(in, &out_dp_cap, TB_CFG_PORT,
in->cap_adap + DP_REMOTE_CAP, 1);
}