diff options
| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2019-09-06 12:05:24 +0300 |
|---|---|---|
| committer | Mika Westerberg <mika.westerberg@linux.intel.com> | 2019-11-01 14:31:59 +0300 |
| commit | 778bfca3d14aa93d1e3062835061401b08c258f7 (patch) | |
| tree | 879aa7c6b62695ced80097e79a569118adfad78a /drivers/thunderbolt | |
| parent | 8f57d47806664d9b2e618ea8086adcf76752daaf (diff) | |
thunderbolt: Convert PCIe adapter register names to follow the USB4 spec
Now that USB4 spec has names for these PCIe adapter registers we can use
them instead. This makes it easier to match certain register to the spec.
No functional changes.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt')
| -rw-r--r-- | drivers/thunderbolt/switch.c | 10 | ||||
| -rw-r--r-- | drivers/thunderbolt/tb_regs.h | 4 |
2 files changed, 8 insertions, 6 deletions
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index 9c2e739c79f3..7d05c858423b 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -803,10 +803,11 @@ bool tb_pci_port_is_enabled(struct tb_port *port) { u32 data; - if (tb_port_read(port, &data, TB_CFG_PORT, port->cap_adap, 1)) + if (tb_port_read(port, &data, TB_CFG_PORT, + port->cap_adap + ADP_PCIE_CS_0, 1)) return false; - return !!(data & TB_PCI_EN); + return !!(data & ADP_PCIE_CS_0_PE); } /** @@ -816,10 +817,11 @@ bool tb_pci_port_is_enabled(struct tb_port *port) */ int tb_pci_port_enable(struct tb_port *port, bool enable) { - u32 word = enable ? TB_PCI_EN : 0x0; + u32 word = enable ? ADP_PCIE_CS_0_PE : 0x0; if (!port->cap_adap) return -ENXIO; - return tb_port_write(port, &word, TB_CFG_PORT, port->cap_adap, 1); + return tb_port_write(port, &word, TB_CFG_PORT, + port->cap_adap + ADP_PCIE_CS_0, 1); } /** diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h index d0858db9f904..4be9df354527 100644 --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h @@ -241,8 +241,8 @@ struct tb_regs_port_header { #define TB_DP_REMOTE_CAP 0x5 /* PCIe adapter registers */ - -#define TB_PCI_EN BIT(31) +#define ADP_PCIE_CS_0 0x00 +#define ADP_PCIE_CS_0_PE BIT(31) /* Hop register from TB_CFG_HOPS. 8 byte per entry. */ struct tb_regs_hop { |