diff options
author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-11-12 13:36:06 +0100 |
---|---|---|
committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-12-17 11:18:44 +0100 |
commit | b8bbd6b2923279f1c9c74d59638b38a1eace78e8 (patch) | |
tree | 79601649860cc1b953c44f7eb09b0ed476b05c33 /drivers/tty/serial/sh-sci.h | |
parent | ff8b275f1f0927621cf543c2a6f02761052c360d (diff) |
serial: sh-sci: Add BRG register definitions
Add register definitions for the Baud Rate Generator for External Clock
(BRG), as found in some SCIF and in HSCIF, including a new regtype for
the "SH-4(A)"-derived SCIF variant with BRG.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/sh-sci.h')
-rw-r--r-- | drivers/tty/serial/sh-sci.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h index bf69bbdcc1f9..fb1760250421 100644 --- a/drivers/tty/serial/sh-sci.h +++ b/drivers/tty/serial/sh-sci.h @@ -27,6 +27,8 @@ enum { HSSRR, /* Sampling Rate Register */ SCPCR, /* Serial Port Control Register */ SCPDR, /* Serial Port Data Register */ + SCDL, /* BRG Frequency Division Register */ + SCCKS, /* BRG Clock Select Register */ SCIx_NR_REGS, }; @@ -109,6 +111,14 @@ enum { #define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */ #define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */ +/* + * BRG Clock Select Register (Some SCIF and HSCIF) + * The Baud Rate Generator for external clock can provide a clock source for + * the sampling clock. It outputs either its frequency divided clock, or the + * (undivided) (H)SCK external clock. + */ +#define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */ +#define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */ #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) |