diff options
| author | Yu Tu <yu.tu@amlogic.com> | 2022-02-25 15:39:20 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-02-26 10:03:20 +0100 |
| commit | e5fc2b99840dab2bf870bc3224a8c22445aedf3f (patch) | |
| tree | eda70c2d5710e193d85d37524e43a9490be3bdf3 /drivers/tty | |
| parent | 44023b8e1f14bc72bb773dd84dc3563fc912d210 (diff) | |
tty: serial: meson: Make some bit of the REG5 register writable
Make the internal clock source mux and divider writeable, allowing the
uart to deviate from the settings intially applied by the ROMCode and
using the most appropriate clocks.
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
Link: https://lore.kernel.org/r/20220225073922.3947-5-yu.tu@amlogic.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
| -rw-r--r-- | drivers/tty/serial/meson_uart.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 4768d51fac70..ba8dc203b9cb 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -686,7 +686,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) CLK_SET_RATE_NO_REPARENT, port->membase + AML_UART_REG5, 26, 2, - CLK_DIVIDER_READ_ONLY, + CLK_DIVIDER_ROUND_CLOSEST, xtal_div_table, NULL); if (IS_ERR(hw)) return PTR_ERR(hw); @@ -708,7 +708,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) CLK_SET_RATE_PARENT, port->membase + AML_UART_REG5, 24, 0x1, - CLK_MUX_READ_ONLY, + CLK_MUX_ROUND_CLOSEST, &use_xtal_mux_table, NULL); if (IS_ERR(hw)) |