diff options
| author | Gregory Herrero <gregory.herrero@intel.com> | 2015-11-20 11:49:29 +0100 |
|---|---|---|
| committer | Felipe Balbi <balbi@ti.com> | 2015-12-15 09:12:41 -0600 |
| commit | 95105a998dff0747327f11708ea24480ee0eca54 (patch) | |
| tree | c634437396d62b1672f56b6a1f884374a4980271 /drivers/usb/dwc2/core.c | |
| parent | fbb9e22b15ad3c9a98c66bad801b4d1366e8bf20 (diff) | |
usb: dwc2: host: avoid usage of dma_alloc_coherent with irqs disabled
Use Streaming DMA mappings to handle cache coherency of frame list and
descriptor list. Cache are always flushed before controller access it
or before cpu access it.
Acked-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herrero@intel.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/dwc2/core.c')
| -rw-r--r-- | drivers/usb/dwc2/core.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c index 5568d9c8e213..542c9e6d95db 100644 --- a/drivers/usb/dwc2/core.c +++ b/drivers/usb/dwc2/core.c @@ -1934,6 +1934,9 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, + chan->desc_list_sz, DMA_TO_DEVICE); + hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK; /* Always start from first descriptor */ |