diff options
| author | John Youn <John.Youn@synopsys.com> | 2015-12-17 11:15:35 -0800 |
|---|---|---|
| committer | Felipe Balbi <balbi@ti.com> | 2015-12-22 11:54:45 -0600 |
| commit | b8ccc593eeeacde0e6794c4dcec0a57eba7356e6 (patch) | |
| tree | b9b6fe7aa282f39c496dd920de63b0267a96826a /drivers/usb/dwc2/core.c | |
| parent | 7d56cc2620f523eba7a831daa22186c8ae5bbdfe (diff) | |
usb: dwc2: Reorder AHBIDLE and CSFTRST in dwc2_core_reset()
According to the databook, the core soft reset should be done before
checking for AHBIDLE. The gadget version of core reset had it correct
but the hcd version did not. This fixes the hcd version.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/dwc2/core.c')
| -rw-r--r-- | drivers/usb/dwc2/core.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c index c8f66ad48a55..62505068abf2 100644 --- a/drivers/usb/dwc2/core.c +++ b/drivers/usb/dwc2/core.c @@ -489,32 +489,33 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg) dev_vdbg(hsotg->dev, "%s()\n", __func__); - /* Wait for AHB master IDLE state */ + /* Core Soft Reset */ + greset = dwc2_readl(hsotg->regs + GRSTCTL); + greset |= GRSTCTL_CSFTRST; + dwc2_writel(greset, hsotg->regs + GRSTCTL); do { udelay(1); greset = dwc2_readl(hsotg->regs + GRSTCTL); if (++count > 50) { dev_warn(hsotg->dev, - "%s() HANG! AHB Idle GRSTCTL=%0x\n", + "%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, greset); return -EBUSY; } - } while (!(greset & GRSTCTL_AHBIDLE)); + } while (greset & GRSTCTL_CSFTRST); - /* Core Soft Reset */ + /* Wait for AHB master IDLE state */ count = 0; - greset |= GRSTCTL_CSFTRST; - dwc2_writel(greset, hsotg->regs + GRSTCTL); do { udelay(1); greset = dwc2_readl(hsotg->regs + GRSTCTL); if (++count > 50) { dev_warn(hsotg->dev, - "%s() HANG! Soft Reset GRSTCTL=%0x\n", + "%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__, greset); return -EBUSY; } - } while (greset & GRSTCTL_CSFTRST); + } while (!(greset & GRSTCTL_AHBIDLE)); if (hsotg->dr_mode == USB_DR_MODE_HOST) { gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); |