usb: dwc2: Add ACG support to the driver

Added function for supporting Active Clock Gating functionality
in the driver.

PCGCCTL1 (Power and Clock Control) register will be used
for controlling the core`s active clock gating feature, and
the previously reserved 12th bit in GHWCFG4 now indicates that the
controller supports the Dynamic Power Reduction (Active Clock Gating)
during no traffic scenarios such as L0, idle, resume and suspend
states.

dwc2_enable_acg() function sets GATEEN bit in PCGCCTL1 register
and enables ACG, if it supported.

According to ACG functional specification, enabling of ACG feature
in host mode done in host initialization, before turning Vbus on,
specifically in dwc2_core_host_init function.

Enabling of ACG feature in device mode done in device initialization,
before clearing the SftDiscon bit in DCTL.
This bit was cleared in dwc2_hsotg_core_connect() function.So
dwc2_enable_acg() called before dwc2_core_connect() calls.

Signed-off-by: Razmik Karapetyan <razmik@synopsys.com>
Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>

1 files changed, 14 insertions, 0 deletions

diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index e85f2d230da4..204506f92620 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -498,6 +498,20 @@ int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
 	return 0;
 }
 
+/*
+ * dwc2_enable_acg - enable active clock gating feature
+ */
+void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
+{
+	if (hsotg->params.acg_enable) {
+		u32 pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1);
+
+		dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
+		pcgcctl1 |= PCGCCTL1_GATEEN;
+		dwc2_writel(pcgcctl1, hsotg->regs + PCGCCTL1);
+	}
+}
+
 /**
  * dwc2_dump_host_registers() - Prints the host registers
  *