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author | Stephen Boyd <sboyd@kernel.org> | 2020-05-21 15:52:41 -0700 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2020-05-21 15:52:41 -0700 |
commit | c60037f0d78088f2f542ac23fb30a0bb68b68ed1 (patch) | |
tree | 19890695e2499f3b07a1e3a9b434a0cecc9e6bb7 /drivers/watchdog/pm8916_wdt.c | |
parent | 8f3d9f354286745c751374f5f1fcafee6b3f3136 (diff) | |
parent | dec396322d25ca5ce2f307b6da897060fdf9a782 (diff) |
Merge tag 'for-5.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra
Pull Tegra clk driver updates from Thierry Reding:
These are a couple of changes to implement EMC frequency scaling on
Tegra210, CPU frequency scaling on Tegra20 and Tegra30 as well as a
special clock gate for the CSI test pattern generator on Tegra210.
* tag 'for-5.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: Add Tegra210 CSI TPG clock gate
clk: tegra30: Use custom CCLK implementation
clk: tegra20: Use custom CCLK implementation
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: Add custom CCLK implementation
clk: tegra: Remove the old emc_mux clock for Tegra210
clk: tegra: Implement Tegra210 EMC clock
clk: tegra: Export functions for EMC clock scaling
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
clk: tegra: Rename Tegra124 EMC clock source file
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Diffstat (limited to 'drivers/watchdog/pm8916_wdt.c')
0 files changed, 0 insertions, 0 deletions