Merge tag 'renesas-soc-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

Merge "Renesas ARM Based SoC Updates for v3.15" from Simon Horman:

* r7s72100 SoC (RZ/A1H)
  - Add i2c clocks (portion missing from previous patch due to miss-merge)

* r8a7791 (R-Car M2)
  - Add SATA clocks
  - Add ZS clock
  - Wait for status on all MSTP clocks
 -- Add I2C and VIN clocks

* r8a7790 (R-Car H2)
  - Add PCI USB host clock support
  - Add Audio DMAC, SATA and VIN clocks
  - Add Audio DMAC support

* r8a7779 (R-Car H1)
  - Wait for status on selected MSTP clocks

* tag 'renesas-soc-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7790: Add PCI USB host clock support
  ARM: shmobile: r7s72100: really add i2c clocks
  ARM: shmobile: r8a7791: Add SATA clocks
  ARM: shmobile: r8a7791: Add ZS clock
  ARM: shmobile: r8a7790: Add SATA clocks
  ARM: shmobile: r8a7790: Add VIN clock support
  ARM: shmobile: r8a7790: add Audio DMAC support
  ARM: shmobile: r8a7790: add Audio DMAC clock
  ARM: shmobile: r8a7791: Wait for status on all MSTP clocks
  ARM: shmobile: r8a7791: Add VIN clocks
  ARM: shmobile: r8a7791: Add I2C clocks
  ARM: shmobile: r8a7790: Wait for status on all MSTP clocks
  ARM: shmobile: r8a7779: Wait for status on selected MSTP clocks
  ARM: shmobile: wait for MSTP clock status to toggle, when enabling it

1 files changed, 38 insertions, 0 deletions

diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 1ebe67cd1833..7442bc130055 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -36,9 +36,47 @@ static void sh_clk_write(int value, struct clk *clk)
 		iowrite32(value, clk->mapped_reg);
 }
 
+static unsigned int r8(const void __iomem *addr)
+{
+	return ioread8(addr);
+}
+
+static unsigned int r16(const void __iomem *addr)
+{
+	return ioread16(addr);
+}
+
+static unsigned int r32(const void __iomem *addr)
+{
+	return ioread32(addr);
+}
+
 static int sh_clk_mstp_enable(struct clk *clk)
 {
 	sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
+	if (clk->status_reg) {
+		unsigned int (*read)(const void __iomem *addr);
+		int i;
+		void __iomem *mapped_status = (phys_addr_t)clk->status_reg -
+			(phys_addr_t)clk->enable_reg + clk->mapped_reg;
+
+		if (clk->flags & CLK_ENABLE_REG_8BIT)
+			read = r8;
+		else if (clk->flags & CLK_ENABLE_REG_16BIT)
+			read = r16;
+		else
+			read = r32;
+
+		for (i = 1000;
+		     (read(mapped_status) & (1 << clk->enable_bit)) && i;
+		     i--)
+			cpu_relax();
+		if (!i) {
+			pr_err("cpg: failed to enable %p[%d]\n",
+			       clk->enable_reg, clk->enable_bit);
+			return -ETIMEDOUT;
+		}
+	}
 	return 0;
 }