diff options
author | Russell King <rmk+kernel@armlinux.org.uk> | 2020-06-03 15:34:01 +0100 |
---|---|---|
committer | Russell King <rmk+kernel@armlinux.org.uk> | 2021-01-07 17:52:13 +0000 |
commit | da01c33d67e366a65932e66ba71d9612dc8a659c (patch) | |
tree | f5d87b0a7da4e1630725ac2f3bf8f069eb9d4c43 /drivers | |
parent | 2c85ebc57b3e1817b6ce1a6b703928e113a90442 (diff) |
PCI: mobiveil: fix 5.7 merge errors
Fix errors in the mobiveil version that was merged in 5.7 kernels:
- the type of "root_bus_nr" was changed from "u8" to "char", but
it is compared to values that are typed as "unsigned char".
Depending whether a platform has "char" as signed or unsigned,
this may not do what is intended.
- ls_pcie_g4_reinit_hw() now returns a success/failure value, and
follows the Linux style of return 0 on success and -ve errno on
failure. However, the testing in ls_pcie_g4_reset() expects 0
on failure, so we won't call ls_pcie_g4_enable_interrupt() except
if ls_pcie_g4_reinit_hw() has failed - which is likely not what
was intended.
Fixes: d29ad70a813b ("PCI: mobiveil: Add PCIe Gen4 RC driver for Layerscape SoCs")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c index ee0156921ebc..e00ed73c2355 100644 --- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c @@ -64,6 +64,17 @@ static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); } +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = &pcie->pci; + u32 header_type; + + header_type = mobiveil_csr_readb(mv_pci, PCI_HEADER_TYPE); + header_type &= 0x7f; + + return header_type == PCI_HEADER_TYPE_BRIDGE; +} + static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) { struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); @@ -195,7 +206,7 @@ static void ls_pcie_g4_reset(struct work_struct *work) ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; mobiveil_csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL); - if (!ls_pcie_g4_reinit_hw(pcie)) + if (ls_pcie_g4_reinit_hw(pcie)) return; ls_pcie_g4_enable_interrupt(pcie); @@ -245,6 +256,9 @@ static int __init ls_pcie_g4_probe(struct platform_device *pdev) return ret; } + if (!ls_pcie_g4_is_bridge(pcie)) + return -ENODEV; + ls_pcie_g4_enable_interrupt(pcie); return 0; |