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authorChristoph Hellwig <hch@lst.de>2023-10-18 07:26:52 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2023-10-26 09:42:37 +0200
commitfd962781270e6452dd5b30c8aa0b3b0fbee06244 (patch)
tree5350164b36f1dd1ae931ba57706462274e70aa48 /drivers
parent1531309aa2092a96c092fa662863ffa53da3ba93 (diff)
riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
RISCV_NONSTANDARD_CACHE_OPS is also used for the pmem cache maintenance helpers, which are built into the kernel unconditionally. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231018052654.50074-2-hch@lst.de Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/cache/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index a57677f908f3..d6e5e3abaad8 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -3,7 +3,7 @@ menu "Cache Drivers"
config AX45MP_L2_CACHE
bool "Andes Technology AX45MP L2 Cache controller"
- depends on RISCV_DMA_NONCOHERENT
+ depends on RISCV
select RISCV_NONSTANDARD_CACHE_OPS
help
Support for the L2 cache controller on Andes Technology AX45MP platforms.