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authorFuyun Liang <liangfuyun1@huawei.com>2017-11-08 15:52:22 +0800
committerDavid S. Miller <davem@davemloft.net>2017-11-11 15:17:56 +0900
commit39e2151f1012eb4163b3a9f414c27d92798e4cbe (patch)
tree515b0100c549ee8212212f77924bac2673f5d459 /drivers
parent28033ae4e0f59782b3f3357d9c28852a7e84a894 (diff)
net: hns3: fix a bug when getting phy address from NCL_config file
Driver gets phy address from NCL_config file and uses the phy address to initialize phydev. There are 5 bits for phy address. And C22 phy address has 5 bits. So 0-31 are all valid address for phy. If there is no phy, it will crash. Because driver always get a valid phy address. This patch fixes the phy address to 8 bits, and use 0xff to indicate invalid phy address. Fixes: 46a3df9f9718 (net: hns3: Add HNS3 Acceleration Engine & Compatibility Layer Support) Signed-off-by: Fuyun Liang <liangfuyun1@huawei.com> Signed-off-by: Lipeng <lipeng321@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index 844c83ea549e..ce5ed8845042 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -390,7 +390,7 @@ struct hclge_pf_res_cmd {
#define HCLGE_CFG_TQP_DESC_N_S 16
#define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
#define HCLGE_CFG_PHY_ADDR_S 0
-#define HCLGE_CFG_PHY_ADDR_M GENMASK(4, 0)
+#define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
#define HCLGE_CFG_MEDIA_TP_S 8
#define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
#define HCLGE_CFG_RX_BUF_LEN_S 16