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authorWeijun Yang <Weijun.Yang@csr.com>2015-04-27 08:15:14 +0000
committerUlf Hansson <ulf.hansson@linaro.org>2015-06-01 09:06:49 +0200
commita1b0b977d2b2b9248ae26df0c7987d1696028309 (patch)
tree112e135d7e6dcaa3ba2ef124ad90a0f4e586b68b /drivers
parentd1ba44a4232aa6a95c19b394df53b07b0d61c9c8 (diff)
mmc: sdhci-sirf: fake version and capbility registers
chips have some issues for version and capbility registers, here we fake them. Signed-off-by: Weijun Yang <Weijun.Yang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/host/Kconfig1
-rw-r--r--drivers/mmc/host/sdhci-sirf.c35
2 files changed, 36 insertions, 0 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index b1f837e749fe..d5e107b78d60 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -219,6 +219,7 @@ config MMC_SDHCI_SIRF
tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs"
depends on ARCH_SIRF
depends on MMC_SDHCI_PLTFM
+ select MMC_SDHCI_IO_ACCESSORS
help
This selects the SDHCI support for SiRF System-on-Chip devices.
diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
index 2201f76b539d..0110bae25b7e 100644
--- a/drivers/mmc/host/sdhci-sirf.c
+++ b/drivers/mmc/host/sdhci-sirf.c
@@ -43,6 +43,39 @@ static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
+static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg)
+{
+ u32 val = readl(host->ioaddr + reg);
+
+ if (unlikely((reg == SDHCI_CAPABILITIES_1) &&
+ (host->mmc->caps & MMC_CAP_UHS_SDR50))) {
+ /* fake CAP_1 register */
+ val = SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING;
+ }
+
+ if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) {
+ u32 prss = val;
+ /* fake chips as V3.0 host conreoller */
+ prss &= ~(0xFF << 16);
+ val = prss | (SDHCI_SPEC_300 << 16);
+ }
+ return val;
+}
+
+static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg)
+{
+ u16 ret = 0;
+
+ ret = readw(host->ioaddr + reg);
+
+ if (unlikely(reg == SDHCI_HOST_VERSION)) {
+ ret = readw(host->ioaddr + SDHCI_HOST_VERSION);
+ ret |= SDHCI_SPEC_300;
+ }
+
+ return ret;
+}
+
static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
{
int tuning_seq_cnt = 3;
@@ -113,6 +146,8 @@ retry:
}
static struct sdhci_ops sdhci_sirf_ops = {
+ .read_l = sdhci_sirf_readl_le,
+ .read_w = sdhci_sirf_readw_le,
.platform_execute_tuning = sdhci_sirf_execute_tuning,
.set_clock = sdhci_set_clock,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,