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authorBjorn Helgaas <bhelgaas@google.com>2017-11-13 15:05:50 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-11-14 08:32:32 -0600
commitc00054f540bf81e592e1fee709b0bdbf20f478b5 (patch)
tree1476fcba8019b00ad895c2bd0a8b5d7ffad03024 /drivers
parent94ac327e043ee40d7fc57b54541da50507ef4e99 (diff)
PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD
Previously we programmed the LTR_L1.2_THRESHOLD in the parent (upstream) device using the capability pointer of the *child* (downstream) device, which corrupted some random word of the parent's config space. Use the parent's L1 SS capability pointer to program its LTR_L1.2_THRESHOLD. Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings") Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Vidya Sagar <vidyas@nvidia.com> CC: stable@vger.kernel.org # v4.11+ CC: Rajat Jain <rajatja@google.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/pcie/aspm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 46c59afb8355..a378dd9d2473 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -657,7 +657,7 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
0xFF00, link->l1ss.ctl1);
/* Program LTR L1.2 threshold in both ports */
- pci_clear_and_set_dword(parent, dw_cap_ptr + PCI_L1SS_CTL1,
+ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
0xE3FF0000, link->l1ss.ctl1);
pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
0xE3FF0000, link->l1ss.ctl1);