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authorVenu Byravarasu <vbyravarasu@nvidia.com>2012-03-23 15:02:32 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-23 16:58:39 -0700
commitce9f650636d310e4c8febc821b0038e9918a12db (patch)
tree3165a949b121068c6c62b42bb9c77f20cb53f5e4 /drivers
parentb4f0b880c8d7eb225b79dec663780b4dcdea7fbc (diff)
drivers/rtc/rtc-twl.c: optimize IRQ bit access
As the TWL RTC driver has a cached copy of enabled RTC interrupt bits in variable rtc_irq_bits, that can be checked before really setting or masking any of the interrupt bits. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/rtc/rtc-twl.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index d43b4f6eb4e4..18dff5255670 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -176,6 +176,10 @@ static int set_rtc_irq_bit(unsigned char bit)
unsigned char val;
int ret;
+ /* if the bit is set, return from here */
+ if (rtc_irq_bits & bit)
+ return 0;
+
val = rtc_irq_bits | bit;
val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
@@ -193,6 +197,10 @@ static int mask_rtc_irq_bit(unsigned char bit)
unsigned char val;
int ret;
+ /* if the bit is clear, return from here */
+ if (!(rtc_irq_bits & bit))
+ return 0;
+
val = rtc_irq_bits & ~bit;
ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
if (ret == 0)