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authorPavel Kiryukhin <vksavl@gmail.com>2007-11-27 19:20:47 +0300
committerRalf Baechle <ralf@linux-mips.org>2007-12-01 00:39:37 +0000
commit54fd6441e04696c046d93e4407a9e1ee9b874e51 (patch)
treeb75c48d3779cb136d09ec7610dc275532b9bfa43 /include/asm-mips
parente1cca7e8d484390169777b423a7fe46c7021fec1 (diff)
[MIPS] Fix use of smp_processor_id() in preemptible code.
Freeing prom memory: 956kb freed Freeing firmware memory: 978944k freed Freeing unused kernel memory: 180k freed BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1 caller is r4k_dma_cache_wback_inv+0x144/0x2a0 Call Trace: [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0 [<802e4b84>] debug_smp_processor_id+0xd4/0xf0 [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0 ... CONFIG_DEBUG_PREEMPT is enabled. -- Bug cause is blast_dcache_range() in preemptible code [in r4k_dma_cache_wback_inv()]. blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that uses cpu_dcache_line_size(). It uses current_cpu_data that use smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT smp_processor_id emits BUG if we are executing with preemption enabled. Cpu options of cpu0 are assumed to be the superset of all processors. Can I make the same assumptions for cache line size and fix this issue the following way: Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/cpu-features.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index f6bd308f047f..5ea701fc3425 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -207,13 +207,13 @@
#endif
#ifndef cpu_dcache_line_size
-#define cpu_dcache_line_size() current_cpu_data.dcache.linesz
+#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
#endif
#ifndef cpu_icache_line_size
-#define cpu_icache_line_size() current_cpu_data.icache.linesz
+#define cpu_icache_line_size() cpu_data[0].icache.linesz
#endif
#ifndef cpu_scache_line_size
-#define cpu_scache_line_size() current_cpu_data.scache.linesz
+#define cpu_scache_line_size() cpu_data[0].scache.linesz
#endif
#endif /* __ASM_CPU_FEATURES_H */