diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2018-06-14 16:37:19 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-06-18 10:49:55 -0700 |
| commit | b9be78531d2710f4302545aa80e0678ed0a3dd09 (patch) | |
| tree | 2c4986a6041d0c58c7214633460f4c8a22be84d4 /include/drm/i915_pciids.h | |
| parent | 5ee4a7a6db8eb46aafdfea1f26cbdbbb4cef76b3 (diff) | |
drm/i915/whl: Introducing Whiskey Lake platform
Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.
So, let's just move them to WHL macros that will feed into CFL macro
just to keep it better organized to make easier future code review
but it will be handled as a CFL.
v2:
Fixing GT level of some ids
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180614233720.30517-1-jose.souza@intel.com
Diffstat (limited to 'include/drm/i915_pciids.h')
| -rw-r--r-- | include/drm/i915_pciids.h | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index bab70ff6e78b..d03350a38025 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -388,32 +388,40 @@ INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ -/* CFL U GT1 */ -#define INTEL_CFL_U_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x3EA1, info), \ - INTEL_VGA_DEVICE(0x3EA4, info) - /* CFL U GT2 */ #define INTEL_CFL_U_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x3EA0, info), \ - INTEL_VGA_DEVICE(0x3EA3, info), \ INTEL_VGA_DEVICE(0x3EA9, info) /* CFL U GT3 */ #define INTEL_CFL_U_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x3EA2, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ +/* WHL/CFL U GT1 */ +#define INTEL_WHL_U_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x3EA1, info) + +/* WHL/CFL U GT2 */ +#define INTEL_WHL_U_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x3EA0, info) + +/* WHL/CFL U GT3 */ +#define INTEL_WHL_U_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x3EA2, info), \ + INTEL_VGA_DEVICE(0x3EA3, info), \ + INTEL_VGA_DEVICE(0x3EA4, info) + #define INTEL_CFL_IDS(info) \ INTEL_CFL_S_GT1_IDS(info), \ INTEL_CFL_S_GT2_IDS(info), \ INTEL_CFL_H_GT2_IDS(info), \ - INTEL_CFL_U_GT1_IDS(info), \ INTEL_CFL_U_GT2_IDS(info), \ - INTEL_CFL_U_GT3_IDS(info) + INTEL_CFL_U_GT3_IDS(info), \ + INTEL_WHL_U_GT1_IDS(info), \ + INTEL_WHL_U_GT2_IDS(info), \ + INTEL_WHL_U_GT3_IDS(info) /* CNL */ #define INTEL_CNL_IDS(info) \ |