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authorJiaxun Yang <jiaxun.yang@flygoat.com>2019-10-20 22:43:13 +0800
committerPaul Burton <paulburton@kernel.org>2019-10-31 15:03:10 -0700
commit268a2d60013049cfd9a0aada77284aa6ea8ad26a (patch)
tree20b8b9f6d76adae4ab963c55ad8cf3d43636ca17 /include/drm
parent2409839ab6bfa28b8451cf9ef7df5a8b0e0a82af (diff)
MIPS: Loongson64: Rename CPU TYPES
CPU_LOONGSON2 -> CPU_LOONGSON2EF CPU_LOONGSON3 -> CPU_LOONGSON64 As newer loongson-2 products (2G/2H/2K1000) can share kernel implementation with loongson-3 while 2E/2F are less similar with other LOONGSON64 products. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/drm_cache.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index 987ff16b9420..e9ad4863d915 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -45,7 +45,7 @@ static inline bool drm_arch_can_wc_memory(void)
{
#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
return false;
-#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3)
+#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64)
return false;
#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
/*