diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-08-08 10:27:38 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-08-15 07:50:15 +0200 |
| commit | b3f9581affb03ed28ff1905b649e66904f29b9e4 (patch) | |
| tree | b0c4a61d3e2300d6beb834a239dae1c82fca2345 /include/dt-bindings/clock/exynos5433.h | |
| parent | 901a0c690f547dbe24fd599e7fc58d7cbf69599b (diff) | |
dt-bindings: clock: samsung: remove define with number of clocks
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Remove it entirely from the bindings, once Linux drivers stopped using
them.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-12-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'include/dt-bindings/clock/exynos5433.h')
| -rw-r--r-- | include/dt-bindings/clock/exynos5433.h | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 25ffa53573a5..d12c1a963fa1 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -188,8 +188,6 @@ #define CLK_SCLK_ISP_SPI0_CAM1 252 #define CLK_SCLK_HDMI_SPDIF_DISP 253 -#define TOP_NR_CLK 254 - /* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL 1 @@ -200,8 +198,6 @@ #define CLK_SCLK_MPHY_PLL 11 #define CLK_SCLK_UFS_MPHY 11 -#define CPIF_NR_CLK 12 - /* CMU_MIF */ #define CLK_FOUT_MEM0_PLL 1 #define CLK_FOUT_MEM1_PLL 2 @@ -396,8 +392,6 @@ #define CLK_SCLK_BUS_PLL_APOLLO 199 #define CLK_SCLK_BUS_PLL_ATLAS 200 -#define MIF_NR_CLK 201 - /* CMU_PERIC */ #define CLK_PCLK_SPI2 1 #define CLK_PCLK_SPI1 2 @@ -468,8 +462,6 @@ #define CLK_DIV_SCLK_SCI 70 #define CLK_DIV_SCLK_SC_IN 71 -#define PERIC_NR_CLK 72 - /* CMU_PERIS */ #define CLK_PCLK_HPM_APBIF 1 #define CLK_PCLK_TMU1_APBIF 2 @@ -513,8 +505,6 @@ #define CLK_SCLK_ANTIRBK_CNT 40 #define CLK_SCLK_OTP_CON 41 -#define PERIS_NR_CLK 42 - /* CMU_FSYS */ #define CLK_MOUT_ACLK_FSYS_200_USER 1 #define CLK_MOUT_SCLK_MMC2_USER 2 @@ -621,8 +611,6 @@ #define CLK_SCLK_USBDRD30 114 #define CLK_PCIE 115 -#define FSYS_NR_CLK 116 - /* CMU_G2D */ #define CLK_MUX_ACLK_G2D_266_USER 1 #define CLK_MUX_ACLK_G2D_400_USER 2 @@ -653,8 +641,6 @@ #define CLK_PCLK_G2D 25 #define CLK_PCLK_SMMU_G2D 26 -#define G2D_NR_CLK 27 - /* CMU_DISP */ #define CLK_FOUT_DISP_PLL 1 @@ -771,8 +757,6 @@ #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 -#define DISP_NR_CLK 116 - /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 #define CLK_MOUT_SCLK_AUD_PCM 2 @@ -824,8 +808,6 @@ #define CLK_SCLK_I2S_BCLK 46 #define CLK_SCLK_AUD_I2S 47 -#define AUD_NR_CLK 48 - /* CMU_BUS{0|1|2} */ #define CLK_DIV_PCLK_BUS_133 1 @@ -840,8 +822,6 @@ #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ -#define BUSx_NR_CLK 11 - /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 @@ -865,8 +845,6 @@ #define CLK_PCLK_SYSREG_G3D 18 #define CLK_SCLK_HPM_G3D 19 -#define G3D_NR_CLK 20 - /* CMU_GSCL */ #define CLK_MOUT_ACLK_GSCL_111_USER 1 #define CLK_MOUT_ACLK_GSCL_333_USER 2 @@ -898,8 +876,6 @@ #define CLK_PCLK_SMMU_GSCL1 27 #define CLK_PCLK_SMMU_GSCL2 28 -#define GSCL_NR_CLK 29 - /* CMU_APOLLO */ #define CLK_FOUT_APOLLO_PLL 1 @@ -935,8 +911,6 @@ #define CLK_SCLK_HPM_APOLLO 29 #define CLK_SCLK_APOLLO 30 -#define APOLLO_NR_CLK 31 - /* CMU_ATLAS */ #define CLK_FOUT_ATLAS_PLL 1 @@ -981,8 +955,6 @@ #define CLK_ATCLK 38 #define CLK_SCLK_ATLAS 39 -#define ATLAS_NR_CLK 40 - /* CMU_MSCL */ #define CLK_MOUT_SCLK_JPEG_USER 1 #define CLK_MOUT_ACLK_MSCL_400_USER 2 @@ -1016,8 +988,6 @@ #define CLK_PCLK_SMMU_JPEG 28 #define CLK_SCLK_JPEG 29 -#define MSCL_NR_CLK 30 - /* CMU_MFC */ #define CLK_MOUT_ACLK_MFC_400_USER 1 @@ -1040,8 +1010,6 @@ #define CLK_PCLK_SMMU_MFC_1 17 #define CLK_PCLK_SMMU_MFC_0 18 -#define MFC_NR_CLK 19 - /* CMU_HEVC */ #define CLK_MOUT_ACLK_HEVC_400_USER 1 @@ -1064,8 +1032,6 @@ #define CLK_PCLK_SMMU_HEVC_1 17 #define CLK_PCLK_SMMU_HEVC_0 18 -#define HEVC_NR_CLK 19 - /* CMU_ISP */ #define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 #define CLK_MOUT_ACLK_ISP_400_USER 2 @@ -1147,8 +1113,6 @@ #define CLK_SCLK_PIXELASYNCS_ISPC 76 #define CLK_SCLK_PIXELASYNCM_ISPC 77 -#define ISP_NR_CLK 78 - /* CMU_CAM0 */ #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 @@ -1285,8 +1249,6 @@ #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 -#define CAM0_NR_CLK 134 - /* CMU_CAM1 */ #define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1 @@ -1404,12 +1366,8 @@ #define CLK_ATCLK_ISP 111 #define CLK_SCLK_ISP_CA5 112 -#define CAM1_NR_CLK 113 - /* CMU_IMEM */ #define CLK_ACLK_SLIMSSS 2 #define CLK_PCLK_SLIMSSS 35 -#define IMEM_NR_CLK 36 - #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ |