diff options
| author | Abhishek Sahu <absahu@codeaurora.org> | 2016-11-25 21:11:29 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-12-21 15:57:26 -0800 |
| commit | d83dcacea185da4f664c909e4c04034336b463ab (patch) | |
| tree | bd6baf8a65b45326770347c82dfa90632a1112bc /include/dt-bindings/clock/qcom,gcc-ipq4019.h | |
| parent | 4577aa01a5d12737c6f8109013651c97535a79b5 (diff) | |
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
The current ipq4019 clock driver does not have support for all
the frequency supported by APSS CPU. APSS CPU frequency is
provided with APSS CPU PLL divider which divides down the VCO
frequency. This divider is nonlinear and specific to IPQ4019
so the standard divider code cannot be used for this.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/dt-bindings/clock/qcom,gcc-ipq4019.h')
| -rw-r--r-- | include/dt-bindings/clock/qcom,gcc-ipq4019.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h index a906d46198b4..c629b2b2bb0d 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h @@ -90,6 +90,7 @@ #define GCC_FEPLL500_CLK 71 #define GCC_FEPLL_WCSS2G_CLK 72 #define GCC_FEPLL_WCSS5G_CLK 73 +#define GCC_APSS_CPU_PLLDIV_CLK 74 #define WIFI0_CPU_INIT_RESET 0 #define WIFI0_RADIO_SRIF_RESET 1 |